Abstract: A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a plurality of pad portions; forming a plurality of spacers which extend across the pad portions and the line forming portion; forming, over the spacers, a blocking layer having an opening which blocks the pad portions and exposes the line forming portion; and etching the line forming portion by using the blocking layer and the spacers as a barrier, to form a plurality of line portions.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.

Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes an active region formed over a substrate and a first group of word lines formed over the active region. The first group of word lines includes at least two word lines. The ROM device structure includes a second group of word lines formed on the active region, and the second group of word lines includes at least two word lines. The ROM device structure further includes an isolation line between the first group of word lines and the second group of word lines and over the active region. The first group of word lines, the second group of word lines, and the isolation line are formed in a second metal layer.

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.

Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.

Abstract: A semiconductor device includes a second channel layer in a first column and a second channel layer in a second column disposed biased to one side of a first channel layer in a first column and a first channel layer in a second column, respectively. The one side of the first channel layer in the first column and the one side of the first channel layer in the second column face directions opposite to each other.

Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.

Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode.

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.

Abstract: A 3D semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other and disposed above the substrate. The memory layers are parallel to each other, and the strings are electrically connected to the upper selection layer and the lower selection layer. The bit lines are positioned under the memory layers.

Abstract: In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit lines formed on the second interlayer insulating layer; and a first plurality of channel structures formed through the stack on the substrate. The first plurality of channel structures are electrically connected to respective ones of the plurality of bit lines. A second plurality of channel structures are formed through the stack on the impurity region, and the second plurality of channel structures are electrically insulated from the plurality of bit lines.

Abstract: Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.

Abstract: The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.

Abstract: The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.

Abstract: A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.

Abstract: A TFT substrate and a manufacturing method thereof are provided. The TFT substrate includes a plurality of vias formed in a second insulation layer that is formed on a second metal layer that forms peripheral signal wiring traces of the TFT substrate so as to line up in an extension direction of each of the peripheral signal wiring traces and a third metal layer that is formed on the second insulation layer at a location corresponding to each of the peripheral signal wiring traces such that the third metal layer is connected, through the vias, with each of the peripheral signal wiring traces to thereby reduce the electrical resistance of each of the peripheral signal wiring traces and thus lowering down power consumption of control ICs and improving capability of the TFT substrate for resisting electrostatic discharge.

Abstract: To provide a display device with excellent display quality, in a display device including a signal line, a scan line, a transistor, a pixel electrode, and a common electrode in a pixel, the common electrode is included in which an extending direction of a region overlapping with the signal line differs from an extending direction of a region overlapping with the pixel electrode in a planar shape and the extending directions intersect with each other between the signal line and the pixel electrode. Thus, a change in transmittance of the pixel can be suppressed; accordingly, flickers can be reduced.

Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.

Abstract: Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.

Abstract: An element substrate and a display device are provided. The element substrate includes a substrate and an element layer, and the element layer is disposed on the substrate, wherein the element layer includes a plurality of active elements, each of the active elements includes a gate, a gate insulating layer, a metal oxide semiconductor layer, a source and a drain. The gate is disposed on the substrate. The gate insulating layer is disposed on the substrate and overlaps the gate. The metal oxide semiconductor layer is disposed on the gate insulating layer. The source and the drain are disposed on the metal oxide semiconductor layer, wherein the source and the drain respectively include a first layer and a second layer, the first layer is between the second layer and the metal oxide semiconductor layer, and the material of the first layer includes titanium nitride.

Abstract: To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.

Abstract: A method device is prepared with a patterned thin film that can include one or more metal oxides on a suitable substrate. Initially, a pattern of a deposition inhibitor is provided on a surface of the substrate, which deposition inhibitor comprises at least one cellulose ester. This pattern has both inhibitor areas where the deposition inhibitor is present and open areas where the deposition inhibitor is absent. An inorganic thin film is then deposited on the surface of the substrate by a chemical vapor deposition process only in the open areas of the pattern. Further operations can be carried out including deposit of a second inorganic thin film exactly over the initial inorganic thin film, the deposition inhibitor can be removed from the inhibitor areas of the pattern, or both operations can be carried out in sequence.

Abstract: A display apparatus capable of reducing a defect rate during manufacturing and utilizing thereof, the display apparatus includes a substrate comprising a display area and a peripheral area outside the display area; a display unit over an upper surface of the substrate to correspond to the display area; and a protective film including a protective film base and an adhesive layer, the protective film being attached to the lower surface of the substrate by the adhesive layer, wherein the protective film base includes a first protective film base corresponding at least to the display area, and a second protective film base having physical properties that are different from physical properties of the first protective film base and corresponding to at least a part of the peripheral area.

Abstract: An image-sensing device includes a semiconductor substrate, a passive layer, and a light-collecting element. The semiconductor substrate includes a photo-sensing element, and the passive layer is disposed over the semiconductor substrate. The light-collecting element is disposed over the passive layer, and includes first, second and third loops. The first loop has a first width. The second loop surrounds the first loop and has a second width that is less than the first width. The third loop surrounds the first and second loops, and has a third width that is less than the second width. The light-collecting element aligns with the photo-sensing element, and the first, second, and third loops include different refractive indices.

Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.

Abstract: An image acquisition device includes an imager including a light receiver, a light shield, a light condenser, and a light emitter. The light shield includes a light transmitting substrate, a light shielding layer, and an opening in the light shielding layer. A light transmitting layer having a refractive index smaller than that of the substrate is between the light condenser and the light shield. When a diameter of a light receiving surface of the light reception element is d, a diameter of the opening is a, a pitch of the light reception elements is p, a refractive index of the light transmitting layer is n1, a refractive index of the substrate is n2, and a distance between the light reception element and the light shielding layer is h, Arctan((p-a/2-d/2)/h)?Arcsin(n1/n2).

Abstract: An image sensor may include an array of image pixels coupled to analog-to-digital conversion circuitry formed from pinned photodiode charge transfer circuits. Majority charge carriers for the pinned photodiodes in the charge transfer circuits may be electrons for photodiode wells formed from n-type doped regions and may be holes for photodiode formed from p-type doped regions. Pinned photodiodes may be used for charge integration onto a capacitive circuit node. Pinned photodiodes may also be used for charge subtraction from a capacitive circuit node. Comparator circuitry may be used to determine digital values for the pixel output levels in accordance with single-slope conversion, successive-approximation-register conversion, cyclic conversion, and first or second order delta-sigma conversion techniques. The array of image pixels used for imaging may have a conversion mode wherein at least a portion of the pixel circuitry in the array are operated similar to the charge transfer circuits.

Abstract: Respective first signal holding units of a plurality of sets are commonly connected to an input node of an amplification unit of one set via a second transfer unit of a set to which the first signal holding unit corresponds, and respective second signal holding units of the plurality of sets are commonly connected to the input node of the amplification unit of one set via a fourth transfer unit of a set to which the second signal holding unit corresponds.

Abstract: Methods of forming an image sensor chip scale package. Implementations may include providing a semiconductor wafer having a pixel array, forming a first cavity through the wafer and/or one or more layers coupled over the wafer, filling the first cavity with a fill material, planarizing the fill material and/or the one or more layers to form a first surface of the fill material coplanar with a first surface of the one or more layers, and bonding a transparent cover over the fill material and the one or more layers. The bond may be a fusion bond between the transparent cover and a passivation oxide; a fusion bond between the transparent cover and an anti-reflective coating; a bond between the transparent cover and an organic adhesive coupled over the fill material, and/or; a bond between a first metallized surface of the transparent cover and a metallized layer coupled over the wafer.

Abstract: The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips.

Abstract: A display device with a semiconductor layer sequence includes an active region provided for generating radiation and a plurality of pixels. The display device also includes a carrier. The active region is arranged between a first semiconductor layer and a second semiconductor layer. The semiconductor layer sequence includes a recess, which extends from a major face of the semiconductor layer sequence facing the carrier through the active region into the first semiconductor layer and is provided for electrical contacting of the first semiconductor layer. The carrier includes a number of switches, which are each provided for controlling at least one pixel.

Abstract: The present invention is directed to an MTJ memory element, which comprises a magnetic fixed layer structure formed on top of a seed layer structure that includes a first seed layer and a second seed layer. The first seed layer includes one or more layers of nickel interleaved with one or more layers of a transition metal, which may be tantalum, titanium, or vanadium. The second seed layer is made of an alloy or compound comprising nickel and another transition metal, which may be chromium, tantalum, or titanium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first type material interleaved with layers of a second type material with at least one of the first and second type materials being magnetic. The first and second type materials may be cobalt and nickel, respectively.

Abstract: Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

Abstract: The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.

Abstract: A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.

Abstract: A display apparatus including a substrate, a display portion disposed on an active area defined at the substrate, a buffer layer disposed on the active area and a pad area defined at the substrate, a touch sensing portion disposed on the buffer layer, and a pad portion disposed between the pad area and the buffer layer. The touch sensing portion includes a first pad pattern, a middle layer disposed on the first pad pattern, and a second pad pattern disposed on the middle layer. The first pad pattern is connected to the pad portion through a first contact hole defined on the pad portion in the buffer layer. The second pad pattern is connected to the first pad pattern through a second contact hole defined on the first contact hole in the middle layer.

Abstract: A display panel including first and second sub pixel electrodes, a first light emitting unit, first and second charge generation layers, a second light emitting unit, and an upper electrode. The first light emitting unit is provided with a first contact hole. The first charge generation layer includes a first contact part being in the first contact hole and coupled to a portion of the first sub pixel electrode exposed by the first contact hole, and a first extension part extending from the first contact part and being on the first light emitting unit. The second charge generation layer and the second light emitting unit are provided with a second contact hole. The upper electrode includes a first upper electrode part being in the second contact hole and coupled to a second contact part of the second charge generation layer exposed by the second contact hole.

Abstract: An organic EL display panel including: a substrate; pixel electrodes that are arrayed in a matrix above the substrate; first organic functional layers that are on or above the pixel electrodes in one-to-one correspondence with the pixel electrodes, the first organic functional layers spaced apart from one another; a second organic functional layer that continuously covers the first organic functional layers; and a counter electrode that opposes the pixel electrodes and covers the second organic functional layer. In the organic EL display panel, the first organic functional layers each include a hole injection layer, and the second organic functional layer has greater electric resistance than each of the first organic functional layers and has a portion extending into an absence region, the absence region being a space between adjacent ones of the first organic functional layers.

Abstract: Full-color pixel arrangements for use in displays and other devices, and devices including the same, are provided. The pixel arrangement includes a patterned electrode layer including multiple electrodes, a patterned emissive layer disposed over the electrode layer, a blanket organic emissive layer disposed over the patterned emissive layer, a second electrode layer disposed between the organic emissive layers, and a third electrode layer disposed over the second blanket organic emissive layer. Electrodes within each of the electrode layers are individually addressable.

Abstract: An OLED pixel arrangement structure includes multiple first sub-pixels, multiple second sub-pixels and multiple third sub-pixels. Four adjacent ones of the first sub-pixels and four adjacent ones of the second sub-pixels are alternately arranged and surround one of the third sub-pixels. Centers of the four adjacent first sub-pixels and centers of the four adjacent second sub-pixels form vertexes of a virtual octagonal cell, and the virtual octagonal cell has at least two orthogonal symmetry axes, a basic pixel unit is formed by the first sub-pixels and the second sub-pixels forming the virtual octagonal cell and a part of the third sub-pixel inside the virtual octagonal cell which are located on one side of one of the at least two orthogonal symmetry axes of the virtual octagonal cell. A center of the third sub-pixel coincides with a center of the virtual octagonal cell.

Abstract: The present invention provides a manufacture method of a TFT backplate and a TFT backplate. By utilizing the oxide semiconductor to manufacture the switch TFT, and utilizing the advantages of rapid switch and lower leakage current of the oxide semiconductor, the switch speed of the switch TFT is raised and the leakage current is lowered; by utilizing the polysilicon to manufacture the drive TFT, and utilizing the properties of higher electron mobility and the uniform grain of the polysilicon, the electron mobility and the current output consistency of the drive TFT is promoted. These are beneficial for the promotion of the light uniformity of the OLED element.

Abstract: An organic light-emitting display apparatus including a substrate; a pixel electrode on the substrate; a pixel-defining layer including an opening exposing at least a portion of the pixel electrode; an intermediate layer including a center area on the pixel electrode and a side area extending from the center area and arranged on the pixel-defining layer, the intermediate layer including one or more common layers and an emission layer; a protective layer covering top surfaces of the center area and the side area of the intermediate layer and exposing at least a portion of the pixel-defining layer; and an opposite electrode spaced apart from the intermediate layer by the protective layer and arranged on the protective layer and portions of the pixel-defining layer, the portions being exposed by the protective layer.

Abstract: An organic light emitting diode display panel is disclosed, which includes: a first substrate, having a display region and a non-display region; an organic light emitting layer disposed above the first substrate; and a plurality of spacers disposed above the first substrate, the spacers including a first spacer, a second spacer, a third spacer and a fourth spacer, the first spacer and the second spacer being adjacently located in the display region, and the third spacer and the fourth spacer being adjacently located in the non-display region, wherein a first minimum distance is between the first spacer and the second spacer, a second minimum distance is between the third spacer and the fourth spacer, and the first minimum distance is different from the second minimum distance. In addition, the present invention also disclosed an organic light emitting diode display device including the same.

Abstract: A display device includes at least one light-emitting element configured to emit blue light, a red conversion layer disposed on an upper or lower portion of the at least one light-emitting element and including a red light-emitting quantum dot, a green conversion layer disposed on the upper or lower portion of the at least one light-emitting element and including a green light-emitting phosphor, and a substrate comprising thin film transistors electrically connected to the light-emitting element.

Abstract: A thin film transistor (TFT) array substrate structure based on organic light-emitting diodes (OLEDs) may include multiple sets of TFT components, capacitors, common electrodes, and data signal lines, all of which are formed on a substrate. Each set of TFT components includes a driving TFT, and the driving TFT has a gate, a source, and a drain. A drain frame extends from the drain and surrounds a pixel block of the TFT array substrate structure, and a transparent conductive film is arranged in a region surrounded by the drain frame and is in contact with the drain frame.

Abstract: An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.