Abstract: A display apparatus capable of reducing defects such as disconnections during manufacturing processes, while ensuring longer lifespan thereof. The display apparatus includes: a substrate including a bending area between a first area and a second area, the bending area of the substrate being bent or bendable about a bending axis; an organic material layer positioned on the substrate corresponding at least to the bending area; a conductive layer extending from the first area to the second area through the bending area, positioned over the organic material layer, and including a plurality of through holes positioned corresponding to the bending area; and first protective layers spaced apart from one another so as to at least partially cover sides of the plurality of through holes.

Abstract: An organic light emitting diode display includes a substrate, a semiconductor, a gate electrode, a source electrode connected to a first portion of the semiconductor, a drain electrode connected to a second portion of the semiconductor, and a pixel electrode connected to the drain electrode. Each of the source electrode, the drain electrode, and the pixel electrode includes a barrier metal layer, a low resistance metal layer, a metal oxide layer, and a contact assistant layer disposed between the low resistance metal layer and the metal oxide layer. The source electrode, the drain electrode, and the pixel electrode each have a step shape.

Abstract: A metal-oxide-metal (MOM) capacitor is provided in the present invention. The MOM capacitor includes a capacitor element, wherein the capacitor element includes a first electrode and a second electrode. A projection of the first electrode includes a closed pattern in the vertical projection direction. A projection of the second electrode is surrounded by the closed pattern of the projection of the first electrode in the vertical projection direction.

Abstract: Measurements on organic single crystals reveal remarkable optical and electrical characteristics compared to disordered films but practical device applications require uniform, pinhole-free films. Disclosed herein is a process to reliably convert as-deposited amorphous thin films to ones that are highly crystalline, with grains on the order of hundreds of microns. The disclosed method results in films that are pinhole-free and that possess grains that individually are single crystal domains.

Abstract: A C-plane GaN substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed. In the C-plane GaN substrate: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on the main surface; the number density of the facet growth area accompanied by a core among the plurality of facet growth areas is less than 5 cm?2 on the main surface; and, when any circular area of 4 cm diameter is selected from an area which is on the main surface and is distant by 5 mm or more from the outer peripheral edge of the substrate, the variation widths of an a-axis direction component and an m-axis direction component of an off-angle within the circular area is each 0.25 degrees or less.

Abstract: A semiconductor rectifying device and a method of manufacturing the same. The semiconductor rectifying device includes: a substrate of a first conductivity type (100), an epitaxial layer of a first conductivity type (200) formed on the substrate of the first conductivity type (100), wherein the epitaxial layer of the first conductivity type (200) defines a plurality of trenches (310) thereon; a filling structure (300) comprising an insulating material formed on the inner surface of the trench (310) and a conductive material filled in the trench (310); a doped region of a second conductivity type (400) formed in the surface of the epitaxial layer of the first conductivity type (200) located between the filling structures (300); an upper electrode (600) formed on a surface of the epitaxial layer of the first conductivity type (200); a guard ring (700) formed in the surface layer of the epitaxial layer of the first conductivity type (200); and a guard layer (800).

Abstract: A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

Abstract: Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region.

Abstract: Methods for forming fin structures with desired profile and dimensions for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. The methods include a structure reshaping process to reshape a shaped structure, such as a diamond like structure formed on a fin structure. In one embodiment, a method for forming a structure on a substrate includes performing an epitaxial deposition process to form a shaped structure on a fin structure disposed on a substrate, performing a mask layer deposition process to form a mask layer having a first width on the shaped structure, and performing a mask trimming process to trim the mask layer from the first width from a second width.

Abstract: In one aspect, a method of forming a finFET device includes: partially forming fins in first/second regions of a substrate; selectively forming spacers on opposite sides of only the fins in a second region; completing formation of the fins such that, based on the spacers, the fins in the second region have a wider base; depositing an insulator between the fins; recessing the insulator to expose a top portion of the fins; forming at least one gate over the fins; further recessing the insulator in the source and drain regions to expose a bottom portion of the fins; and growing an epitaxial material in the source and drain regions that is un-merged in the first region yet is merged in the second region due to the base of the fins in the second region having a wider base. A finFET device is also provided.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.

Abstract: A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.

Abstract: The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N? drift layer. A concentration slope ?, which is derived from displacements in a depth TB (?m) and an impurity concentration CB (cm?3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03???0.7}.

Abstract: The present disclosure relates to a high voltage transistor device having a thin polysilicon film field plate, and an associated method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed between source and drain regions and separated from a substrate by a gate dielectric. A spacer is disposed along an upper surface of the substrate. The spacer extends along a first gate sidewall closer to the drain region, crosses over an upper edge of the gate electrode, and further extends laterally to cover a portion of an upper surface of the gate electrode. A field plate including a polysilicon thin film is disposed along upper and sidewall surfaces of the spacer so that the polysilicon thin film is separated from the gate electrode and the substrate by the spacer. The thin polysilicon film field plate improves the breakdown voltage of the transistor device.

Abstract: A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one embodiment, the multi-layer charge-trapping region includes a first deuterated layer overlying the tunnel dielectric layer and a first nitride-containing layer overlying the first deuterated layer. Other embodiments are also described.

Abstract: In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.

Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.

Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.

Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.

Abstract: In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD.

Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure over the substrate. There is a gap between the first fin structure and the second fin structure. The semiconductor device structure includes an isolation structure having a thin portion and a thick portion. A first upper portion of the first fin structure and a second upper portion of the second fin structure protrude from the thin portion. The thick portion is partially between the first upper portion and the second upper portion. The semiconductor device structure includes a dummy gate electrode over the thick portion, the first upper portion, and the second upper portion. The semiconductor device structure includes a gate electrode over the first fin structure and the thin portion.

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a substrate, a first source/drain layer including a plurality of pillar structures, and a plurality of fins disposed on and in contact with the plurality of pillar structures. A doped layer epitaxially grown from the first source/drain layer is in contact with the plurality of fins and the plurality of pillar structures. A gate structure is disposed in contact with two or more fins in the plurality of fins. The gate structure includes a dielectric layer and a gate layer. A second source/drain layer is disposed on the gate structure. The method includes epitaxially growing a doped layer in contact with a plurality of fins and a plurality of pillar structures. A gate structure is formed in contact with two or more fins. A second source/drain layer is formed on the gate structure.

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

Abstract: Described is a technique for uniformly doping a silicon substrate having a Fin structure with a dopant. A method of manufacturing a semiconductor device may includes: (a) forming a dopant-containing film containing a dopant on a silicon film by performing a cycle a predetermined number of times, the, cycle including: (a-1) forming a first dopant-containing film by supplying a first dopant-containing gas containing the dopant and a first ligand to a substrate having thereon the silicon film and one of a silicon oxide film and a silicon nitride film; and (a-2) forming a second dopant-containing film by supplying a second dopant-containing gas containing the dopant and a second ligand different from and reactive with the first ligand to the substrate; and (b) forming a doped silicon film by annealing the substrate having the dopant-containing film thereon to diffuse the dopant into the silicon film.

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed. For at least one of the first gate insulating film and the insulating film, three signals in Electron Spin Resonance Measurement are each observed in a certain range of g-factor. Reducing the sum of the spin densities of the signals will improve reliability of the semiconductor device.

Abstract: A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.

Abstract: The invention relates to a modulation device created on a substrate (1), comprising at least one nanodiode in the form of a T fitted into a U, the channel (31) of said nanodiode being the leg of the T that is inserted into the U. The device is characterised in that it comprises at least one electrically conductive line (37) that passes over at least part of said channel (31).

Abstract: A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

Abstract: Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

Abstract: Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

Abstract: A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode, the first oxidized region having an oxygen concentration higher than an oxygen concentration of a region near an interface with a region of the insulating film other than below the gate electrode.

Abstract: A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode that are disposed on the nitride semiconductor layer at an interval; a first gate electrode that is located between the source electrode and the drain electrode and performs a normally-on operation; and a second gate electrode that is located between the first gate electrode and the source electrode and performs a normally-off operation. The first gate electrode is disposed to surround the drain electrode in plan view. The second gate electrode is disposed to surround the source electrode in plan view.

Abstract: A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Qgd). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.

Abstract: A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed from a p-type nitride semiconductor in which Mg or Zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.

Abstract: A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.

Abstract: A Field Effect Transistor including: a channel with one end designated the source and the other end designated the drain; a means for connecting to said source end of said channel; a means for connecting to said drain end of said channel; a gate divided into a plurality of segments each insulated from one another; a means for adjusting the bias of each of said segments independently of one another, whereby the depletion region in said channel can be adjusted to avoid pinch-off and to maximize the efficiency of said Field Effect Transistor.

Abstract: The present disclosure relates to the technical field of semiconductors and discloses a semiconductor device and a manufacturing method therefor. Forms of the method may include: providing a substrate structure, where the substrate structure includes: a semiconductor substrate, a semiconductor fin on the semiconductor substrate, isolation regions at two sides of the semiconductor fin, a gate dielectric layer on a surface of the semiconductor fin above the isolation regions, and a gate on a part of the gate dielectric layer; and performing threshold voltage adjustment ion implantation on a part of the semiconductor fin that is not covered by the gate, so as to enable implanted impurities to diffuse into a part of the semiconductor fin that is covered by the gate. Forms of the present disclosure can reduce loss of impurities implanted by the threshold voltage adjustment ion implantation.

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

Abstract: A method of fabricating a semiconductor device comprises providing a substrate with a shallow trench isolation (STI) within the substrate and a gate stack. A cavity is formed between the gate stack and the STI. The cavity comprises one sidewall formed by the STI, one sidewall formed by the substrate, and a bottom surface formed by the substrate. A film is grown in the cavity and thereafter an opening formed by removing a first portion of the strained film until exposing the bottom surface of the substrate while a second portion of the strained film adjoins the STI sidewall. Another epitaxial layer is then grown in the opening.

Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.

Abstract: A novel oxide semiconductor, a novel oxynitride semiconductor, a transistor including them, or a novel sputtering target is provided. A composite target includes a first region and a second region. The first region includes an insulating material and the second region includes a conductive material. The first region and the second region each include a microcrystal whose diameter is greater than or equal to 0.5 nm and less than or equal to 3 nm or a value in the neighborhood thereof. A semiconductor film is formed using the composite target.

Abstract: An optical sensing device includes a thin film transistor disposed on a substrate, an optical sensor, a planar layer, and an organic light emitting diode. The optical sensor includes a metal electrode disposed on a gate dielectric layer of the thin film transistor and connecting to a drain electrode of the thin film transistor, an optical sensing layer disposed on the metal electrode, and a first transparent electrode disposed on the optical sensing layer. The planar layer covers at least a part of the thin film transistor and the optical sensor. The organic light emitting diode is disposed on the planar layer. The anode electrode and the cathode electrode of the organic light emitting diode are electrically coupled to a gate line and a data line respectively.

Abstract: A semiconductor device (100) includes: a substrate (10); and a thin film transistor (5) supported on the substrate, the thin film transistor including a gate electrode (12), an oxide semiconductor layer (18), a gate insulating layer (20) provided between the gate electrode and the oxide semiconductor layer, and a source electrode (14) and a drain electrode (16) electrically connected to the oxide semiconductor layer, wherein: the drain electrode is shaped so as to project toward the oxide semiconductor layer; a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects; and the width W1 and the width W2 are 3 ?m or more and 6 ?m or less.

Abstract: Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.