Abstract: A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, a layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

Abstract: A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns, and forming a second cell pattern and a peripheral pattern on the first layer. The second cell pattern includes first holes in a cell region and the peripheral pattern is located in a peripheral region. The method also includes filling the first holes, removing the second cell pattern to expose pillars, and forming second holes. Each of the second holes corresponds to adjacent cell spacers of the pillars. The method also includes removing the pillars to form third holes corresponding to respective ones of the cell spacers, and etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench.

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

Abstract: In one example, the method includes removing a portion of at least a layer of a bottom spacer material positioned above a first bottom source/drain (S/D) region of a first vertical transistor so as to thereby form a gate-to-source/drain contact opening that exposes a portion of the first bottom S/D region, forming a continuous conductive gate electrode material layer above the first bottom S/D region and a second bottom S/D region and within the gate-to-source/drain contact opening, and removing a portion of the continuous gate electrode material layer so as to form first and second separate gate structures for the first and second vertical transistors, respectively, wherein a portion of the second gate structure is positioned within the gate-to-source/drain contact opening, thereby conductively coupling the second gate structure to the first bottom S/D region.

Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. A first portion of the plurality of doped semiconductor material layers may be doped with a first dopant having a first dopant parameter. A second portion of the plurality of doped semiconductor material layers may be doped with a second dopant having a second dopant parameter. In embodiments, the first portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than a defined threshold. In embodiments, the second portion of the plurality of doped semiconductor layers may include a dopant at a concentration less than the defined threshold. The differing dopant concentrations have been found to beneficially and advantageously affect the etch rate in the respective semiconductor layers when forming control gate recesses in the semiconductor layers.

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

Abstract: A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.

Abstract: According to one embodiment, columnar portions extend through an insulating layer and through a stacked body under the insulating layer. The columnar portions are of an insulating material different from the insulating layer. Contact portions include a first contact portion disposed inside a first terrace portion and a second contact portion disposed inside a second terrace portion. The columnar portions including a first columnar portion disposed inside the first terrace portion and a second columnar portion disposed inside the second terrace portion. A shortest distance between the first contact portion and the first columnar portion, and a shortest distance between the second contact portion and the second columnar portion are substantially equal to each other.

Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.

Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.

Abstract: A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

Abstract: A method of fabricating a three-dimensional semiconductor device is provided. The method includes providing a substrate with a peripheral circuit region and a cell array region; forming a peripheral structure on the peripheral circuit region, and forming an electrode structure on the cell array region. The electrode structure includes a lower electrode, a lower insulating planarized layer on the lower electrode, and upper electrodes and upper insulating layers vertically and alternatingly stacked on the lower insulating planarized layer, and the lower insulating planarized layer may be extended to cover the peripheral structure on the peripheral circuit region. An upper insulating planarized layer is formed to cover the electrode structure and the lower insulating planarized layer on the peripheral circuit region.

Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.

Abstract: An electrical connection structure providing better optical properties in a display includes an electrical connection unit, an interference layer, and an electrically insulating cover. The interference layer is positioned on a side of the electrical connection unit. The electrically insulating cover is positioned on the other side of the electrical connection unit and formed to cover the electrical connection unit. The electrical connection unit includes a metal layer to reflect light. The interference layer reflects light emitted from the electrically insulating cover towards a first side of the interference layer. A degree of reflectance of the first side of the interference layer is equal to the reflectance of the metal layer.

Abstract: To provide a peeling method that achieves low cost and high mass productivity. The peeling method includes the steps of: forming a first layer with a photosensitive material over a formation substrate; forming a first region and a second region having a smaller thickness than the first region in the first layer by photolithography to form a resin layer having the first region and the second region; forming a transistor including an oxide semiconductor in a channel formation region over the first region in the resin layer; forming a conductive layer over the second region in the resin layer; and irradiating the resin layer with laser light to separate the transistor and the formation substrate.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.

Abstract: A thin film transistor (TFT) includes a scan line on a substrate, the scan line including a straight portion extending along a first direction, an active layer including an oxide semiconductor and overlapping the straight portion of the scan line, the active layer having a first region, a second region, and a third region that are linearly and sequentially aligned along the first direction, a first insulating layer between the active layer and the scan line, a first electrode connected to the first region of the active layer, and a second electrode connected to the third region of the active layer.

Abstract: A pixel array includes first signal lines, second signal lines, active elements, pixel electrodes, and selection lines. The second signal lines are intersected with and electrically insulated to the first signal lines to define pixel regions. The active element and the pixel electrode are disposed in the pixel regions. The active elements are electrically connected to the first signal lines and the second signal lines. The pixel electrodes are electrically connected to the active elements. The selection lines are disposed over the first signal lines and intersected with the first signal lines to form first intersections and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections and electrically insulated to the first signal lines at the second intersections. The selection lines and the pixel electrodes are leveled. The selection lines are electrically insulated to the second signal lines.

Abstract: A pixel array substrate includes a display area, signal lines, transmission lines, selection lines, and jumper wires. The selection lines intersect with the signal lines to form intersection regions. The selection lines have first contacts, second contacts, and third contacts. The first contacts are respectively located on the intersection regions. Each of the first contacts is between one of the second contacts and one of the third contacts. A first portion of the first contacts are passed by a line of the display area. The jumper wires respectively pass the first contacts, and two ends of each of the jumper wires are respectively located on one of the second contacts and one of the third contacts. A first portion of the jumper wires electrically connect the first portion of the first contacts and the second contacts, but electrically isolate the third contacts.

Abstract: Provided is a novel semiconductor device. A switching element, specifically a transistor having a well potential structure is manufactured by utilizing a structure including at least a composite material in which a first region and a second region are stacked over a base like a superlattice. The thickness of each of the first region and the second region is greater than or equal to 0.5 nm and less than or equal to 5 nm. A band structure can be controlled by adjusting the number of stacks, which enables application to a variety of semiconductor elements.

Abstract: A semiconductor device (1001) includes a thin-film transistor (101) including a gate electrode (3), an oxide semiconductor layer (7), a gate insulating layer (5), a source electrode (9s), and a drain electrode (9d); a metal oxide layer (8) including a conductor region (70c) and formed from an oxide film from which the oxide semiconductor layer (7) is also formed; an interlayer insulating layer (13) covering the thin-film transistor and the metal oxide layer (8); and a transparent conductive layer (15) disposed on the interlayer insulating layer and electrically connected to the drain electrode, wherein the oxide semiconductor layer (7) and the metal oxide layer (8) contain indium, tin, and zinc, and the transparent conductive layer (15) overlaps at least a portion of the conductor region (70c) with the interlayer insulating layer (13) therebetween.

Abstract: A photodetector according to an embodiment includes: a substrate with a first and second faces; pixels disposed to the substrate, each pixel including: light detection cells disposed on the first face, each light detection cell being surrounded by a first opening having a continuous closed curve shape formed on the second face when viewed from a side of the second face; a first wiring line disposed on the first face to connect to each of the light detection cells; first electrodes, each of the first electrodes being disposed in corresponding one of third openings and connected to the second face, the third openings being disposed in a first insulating film and exposing a part of respective regions of the light detection cells in the second face; a second electrode disposed on the second surface and connecting the first electrodes; and a light blocking material filled to the first opening.

Abstract: Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed.

Abstract: An image sensor includes a substrate having a first pixel region and a second pixel region adjacent to the first pixel region, a device isolation layer between the first pixel region and the second pixel region and isolating the first pixel region and the second pixel region from each other, a first transistor disposed in the first pixel region, a second transistor disposed in the second pixel region, and a wiring structure electrically connecting the first transistor and the second transistor. The device isolation layer has a deep trench isolation (DTI) structure which extends from a top surface toward a bottom surface of the substrate.

Abstract: An image sensor includes: a light receiving section suitable for generating photocharges in response to incident light; and a driving section including a source follower transistor suitable for generating an output voltage corresponding to a reference voltage in response to the photocharges. The source follower transistor includes: a stack structure formed by sequentially stacking a first conductive layer, an insulating layer and a second conductive layer; an open portion formed through the second conductive layer and the insulating layer so as to expose the first conductive layer; a channel layer formed along the surface of the open portion so as to be connected to the first conductive layer and the second conductive layer; and a gate is connected to the light receiving section and which is formed over the channel layer so as to overlap the second conductive layer.

Abstract: An image sensor includes a light receiving element, an anti-reflection layer, a high refractive pattern, a color filter, and a micro lens. The light receiving element is formed on a semiconductor substrate to generate charges responsive to incident light. The anti-reflection layer is formed on the semiconductor substrate. The high refractive pattern is formed on the anti-reflection layer in correspondence with the light receiving element. The color filter is formed on the anti-reflection layer while covering a top surface and lateral sides of the high refractive pattern. The micro lens is formed on the color filter. The image sensor provides an image having high quality.

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.

Abstract: A light field imaging device includes an image sensor having a plurality of pixels arranged two-dimensionally therein; a microlens array formed over the image sensor, the microlens array having a plurality of microlenses arranged two-dimensionally therein; and a plurality of support structures formed between the image sensor and the microlens array for providing an air gap therebetween.

Abstract: A pixel of a complementary metal-oxide-semiconductor (CMOS) image sensor includes a semiconductor substrate having a first surface and a third surface formed by removing part of the semiconductor substrate from a second surface, an active region which is formed between the first surface and the third surface and which contains a photoelectric conversion element generating charges in response to light incident on the substrate at the third surface, and a trench-type isolation region formed from either of the first and third surfaces to isolate the active region from an adjacent active region. The trench-type isolation region is filled with first material in a process that leaves a void in the material, the void is filled or partially filled with second material, and then a layer of third material is formed over the resulting structure composed of the first and second materials.

Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.

Abstract: A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another.

Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.

Abstract: According to one embodiment, a CMOS image sensor includes a photoelectric conversion element and an amplifier transistor. The photoelectric conversion element converts incident light into an electric signal. The amplifier transistor has a heterojunction in which a Ge layer and an SiGeSn layer are joined together, as a channel region and amplifies the electric signal resulting from conversion by the photoelectric conversion element.

Abstract: Provided are a photoelectric conversion device, a method of manufacturing the photoelectric conversion device, and an X-ray image detector. A photoelectric conversion device at least includes a photodiode device. The photodiode device includes a lower electrode and an upper electrode, and a photoelectric conversion layer put between the lower and upper electrodes, where the photoelectric conversion layer includes a patterned edge surface, is smaller in size than the lower electrode and is placed on a surface of the lower electrode. The photodiode device further includes a protecting film covering at least the patterned edge surface of the photoelectric conversion layer. The protecting film except for an area where a contact hole is formed and the lower electrode are formed with a same-shaped pattern.

Abstract: A packaging structure and a packaging method for a fingerprint identification chip are provided. The packaging structure includes a substrate, a sensing chip, a wire and a plastic encapsulation layer. The substrate is provided with a first solder pad layer. The sensing chip has a first surface and a second surface opposite to the first surface, the first surface comprises a sensing area and a peripheral area surrounding the sensing area, and the surface of the sensing chip in the peripheral area is provided with a second solder pad layer. Two ends of the wire are electrically connected to the first solder pad layer and the second solder pad layer respectively. The plastic encapsulation layer is made of a polymer, the plastic encapsulation layer surrounds the wire and the sensing chip.

Abstract: A method for manufacturing one or more optical devices, each comprising a first member and a second member, and a spacer arranged between the first and second members. The method includes manufacturing a spacer wafer including a multitude of the spacers. Manufacturing the spacer wafer includes providing a replication tool having spacer replication sections; bringing the replication tool in contact with a first surface of another wafer; bringing a vacuum sealing chuck into contact with a second surface of the other wafer while the other wafer remains in contact with the replication tool; and injecting a liquid, viscous or plastically deformable material through an inlet of the vacuum sealing chuck so as to substantially fill the spacer replication sections.

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond pad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding strength between the sensor and the ASIC.

Abstract: To provide a light-emitting unit having a semiconductor light-emitting device with a good responsiveness and a sufficient light emission quantity. The light-emitting unit comprises a plurality of semiconductor light-emitting devices, an n-wiring electrode and a p-wiring electrode respectively connecting the semiconductor light-emitting devices in parallel, an n-pad electrode connected to the n-wiring electrode, and a p-pad electrode connected to the p-wiring electrode. At least one of the Group III nitride semiconductor light-emitting devices has a light emission volume of 1 ?m3 to 14 ?m3.

Abstract: A display apparatus including a light emitting diode part including a plurality of regularly arranged light emitting diodes, and a TFT panel part configured to drive the light emitting diode part. The light emitting diode part includes a transparent electrode, the light emitting diodes regularly disposed on a first surface of the transparent electrode and electrically connected to the transparent electrode, a plurality of first reflective electrodes disposed at sides of the light emitting diodes, surrounding the light emitting diodes, and electrically connected to the transparent electrode, and a plurality of second reflective electrodes electrically connected to the light emitting diodes, respectively, and reflecting light emitted from the light emitting diodes.

Abstract: An integrated circuit system, structure and/or component is provided that includes an integrated electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. An energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase a power output of the electric harvesting component.

Abstract: Aspects disclosed include reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices. In one example, a width of a bottom electrode of an MTJ device is provided to be less than a width of the MTJ stack of the MTJ device. In this manner, etching of the bottom electrode may be reduced or avoided to reduce or avoid metal redeposition as a result of over-etching the MTJ device to avoid horizontal shorts between an adjacent device(s). In another example, a seed layer is embedded in a bottom electrode of the MTJ device. In this manner, the MTJ stack is reduced in height to reduce or avoid metal redeposition as a result of over-etching the MTJ device. In another example, an MTJ device includes an embedded seed layer in a bottom electrode which also has a width less than a width of the MTJ stack.