Abstract: A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer. The pinned layer structure contacts the tunnel barrier layer and includes at least one pinned layer. The vertical polarizer structure contacts the insulation barrier layer and includes a plurality of magnetization multi-layered structures sequentially stacked. Each magnetization multi-layered structure includes a non-magnetic layer and a magnetic layer sequentially stacked. The pinned layer and the magnetic layer have magnetization directions anti-parallel to each other.

Abstract: A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.

Abstract: A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.

Abstract: Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.

Abstract: An alternating material stack of insulator lines and first electrically conductive material layers is formed over a substrate, and is patterned to provide alternating stacks of insulating layers and first electrically conductive lines. A metal can be selectively deposited on the physically exposed sidewalls of the first electrically conductive material layers to form metal lines, while not growing from the surfaces of the insulator lines. The metal lines are oxidized to form metal oxide lines that are self-aligned to the sidewalls of the first electrically conductive lines. Vertically extending second electrically conductive lines can be formed as a two-dimensional array of generally pillar-shaped structures between the alternating stacks of the insulator lines and the first electrically conductive lines. Each portion of the metal oxide lines at junctions of first and second electrically conductive lines constitute a resistive memory element for a resistive random access memory (ReRAM) device.

Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

Abstract: The invention provides a manufacturing method for complementary TFT device. The manufacturing method for complementary TFT device uses a solution method to continuously form a metal oxide semiconductor TFT and an organic semiconductor TFT; the metal oxide semiconductor TFT and the organic semiconductor TFT are electrically connected, and one of the metal oxide semiconductor TFT and the organic semiconductor TFT is an N-type channel TFT, and the other is a P-type channel TFT. The method can reduce the use of vacuum apparatus and high temperature apparatus, and explore the advantages of the solution method to realize large area and low-cost to reduce production costs and increase product competitiveness. The invention also provides a manufacturing method for OLED display panel, able to reduce production cost and increase product competitiveness.

Abstract: A solid-state image pickup device includes at least two stacked first and second photoelectric conversion sections in each of a plurality of pixels. Sensitivity of the first photoelectric conversion section to a light incident angle is equivalent to sensitivity of the second photoelectric conversion section to a light incident angle, for each of the pixels.

Abstract: Providing a light-emitting element emitting light in a broad emission spectrum. A combination of a first organic compound and a second organic compound forms an exciplex. The first organic compound has a function of converting triplet-excitation energy into light emission. The lowest triplet excitation level of the second organic compound is higher than or equal to the lowest triplet excitation level of the first organic compound, and the lowest triplet excitation level of the first organic compound is higher than or equal to the lowest triplet excitation level of the exciplex. Light emission from a light-emitting layer includes light emission from the first organic compound and light emission from the exciplex.

Abstract: The present disclosure includes a top emission type organic light emitting diode display device. The top emission type organic light emitting diode display device of the disclosed present disclosure includes an overcoating layer disposed on a substrate and including a plurality of convex portions or a plurality of concave portions in which a full width at half maximum is greater than a radius, a first electrode disposed on the overcoating layer, an organic light emitting layer disposed on the first electrode, and a second electrode disposed on the organic light emitting layer.

Abstract: The present disclosure relates to an array substrate, a method for manufacturing the array substrate and a display device. The array substrate may include a plurality of pixel groups. Each of the pixel groups may include a plurality of sub-pixels. Each of the sub-pixels may include a light-emitting region and a light-emitting layer absent region. And the light-emitting layer absent regions of the plurality of sub-pixels included in each of the pixel groups may define a first region. A photosensitive unit may be arranged on each first region and configured to generate an electrical signal based on an intensity of the light being sensed.

Abstract: A display device includes: a display panel including a display area for displaying an image; a window provided on an upper portion of the display panel; a protection plate provided on a lower portion of the display panel; and a photosensor provided at least one of between the display panel and the window and between the display panel and the protection plate, wherein the photosensor includes a shutter for controlling light emitted by the display panel to transmit through the window or the protection plate, and a photodetector for receiving the light reflected after transmitting through the window or the protection plate.

Abstract: An organic light emitting display (OLED) device includes a substrate including a light emitting region and a peripheral region. An auxiliary power supply wire is disposed in the peripheral region. A lower electrode is disposed in the light emitting region. A pixel defining layer, disposed on the substrate, exposes a portion of the lower electrode and a portion of the auxiliary power supply wire. A first common layer, disposed on the pixel defining layer and the lower electrode, exposes the auxiliary power supply wire. A light emitting structure is disposed on the first common layer. The light emitting structure exposes the auxiliary power supply wire. A second common layer is disposed on the light emitting structure, the second common layer covering the light emitting structure and exposing the auxiliary power supply wire. An upper electrode is disposed on the second common layer and contacts the auxiliary power supply wire.

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.

Abstract: A method for manufacturing a flexible organic light emitting display is disclosed. The method is: sequentially forming a first buffer layer, a switch array layer, a display unit layer, and a thin film package layer on a flexible underlay substrate. When the flexible organic light emitting display bends along the flexible underlay substrate, a first bending deformation force is generated. The first buffer layer is used to absorb the first bending deformation force, and the material of the first buffer layer is an organic insulating material.

Abstract: A second data transfer line that is coupled to a gate layer of a drive transistor is formed in a layer higher than the gate layer, and a transfer capacitor is formed in a layer higher than a layer having the second data transfer line. A first data transfer line to which a data signal is supplied is formed in a layer higher than a layer having the transfer capacitor.

Abstract: A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display region from an outside of the display region for transmitting a signal to drive the respective pixel portions; connection pads provided on the outside of the display region and serving as input portions to provide the wires with a signal while electrically conducting with the wires; switch elements provided on the outside of the display region in a middle of the wires; and a light shielding covering portion shielding the switch elements from light and formed to cover the connection pads while electrically conducting with the connection pads.

Abstract: A display device includes a substrate including a display area and a non-display area disposed at a peripheral area of the display area. A plurality of pixels is disposed in the display area of the substrate. A plurality of signal lines is disposed on the substrate and is connected to the plurality of pixels. The plurality of signal lines include a plurality of gate lines and a plurality of data lines disposed on the substrate. A crack detecting line is disposed in the non-display area and is connected to a first data line of the plurality of data lines. The crack detecting line includes a first portion disposed below an insulating layer and a second portion disposed above the insulating layer. The first portion and the second portion are connected with each other through a contact hole formed in the insulating layer.

Abstract: A display device includes: a substrate including a bending area located between a first region and a second region; an organic layer disposed over the substrate, an upper surface of the organic layer including an uneven surface in the bending area, the uneven surface including a plurality of protrusions; and a conductive layer extending from the first region to the second region across the bending area, the conductive layer being located over the organic layer and including a plurality of through holes.

Abstract: One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential can be supplied stably is provided. Further, a bendable display device to which a signal or a power supply potential can be supplied stably is provided. The display device includes, over a flexible substrate, a display portion, a plurality of connection terminals to which a signal from an outside can be input, and a plurality of wirings. One of the plurality of wirings electrically connects one of the plurality of connection terminals to the display portion. The one of the plurality of wirings includes a first portion including a plurality of separate lines and a second portion in which the plurality of lines converge.

Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.

Abstract: An organic light emitting device includes a base substrate having a pixel region and a non-pixel region, an organic light emitting element on the pixel region, and an auxiliary line in the non-pixel region. The organic light emitting element includes an anode, a first organic light emitting layer disposed on the anode, a first cathode, and a second cathode. The first cathode is on the first organic light emitting layer to be thereby electrically connected to the auxiliary line. The second cathode is on the first cathode to be thereby electrically connected to the first cathode. The first cathode may include a metal and the second cathode may include a transparent conductive oxide (TCO).

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanowires of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

Abstract: A processor includes a transistor pair of a first transistor and a second transistor. The first transistor of the transistor pair is coupled to a Spaser and configured to output a drive current to the Spaser to pump the Spaser. Responsive to the drive current, the Spaser outputs surface plasmon polaritons (SPPs) which are fed to a plasmonic interconnect wire. The plasmonic interconnect wire propagates the SPPs. Further, the SPPs propagated on the plasmonic interconnect wire are detected by a phototransistor. Responsive to detecting the SPPs, the phototransistor generates an output current that is fed to a gate terminal of the second transistor to charge the second transistor.

Abstract: A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed on the semiconductor substrate; a first-conductivity-type source layer formed in a surface part of the epitaxial layer; two second-conductivity-type gate layers formed in the surface part of the epitaxial layer so as to sandwich the source layer; a first-conductivity-type channel forming layer formed so as to be sandwiched between the two gate layers, the first-conductivity-type channel forming layer being formed on an inner side of the source layer in the epitaxial layer; and an electrode connected to one of the drain layer, the source layer, and the gate layer. In the channel forming layer, two first-conductivity-type impurity layers each having a substantially predetermined width are formed adjacent to each other in a direction crossing a channel.

Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.

Abstract: A coated quantum dot and methods of making coated quantum dots are provided.

Abstract: A method of restricting diffusion of miscible materials across a barrier, including, forming a 2-dimensional material on a substrate surface, wherein the 2-dimensional material includes one or more defects through which a portion of the substrate surface is exposed, forming a plug selectively on the exposed substrate surface, and forming a cover layer on the plug and 2-dimensional material, wherein the cover layer material is miscible in the substrate material.

Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to disconnected or connected shielding regions that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a widest portion of the JFET region between adjacent device cells such that a distance between a shielding region and well regions surrounding device cell is less than a parallel JFET width between two adjacent device cells, while maintaining a channel region width and/or a JFET region density that is greater than that of a comparable conventional stripe device. As such, the disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g.

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract: Embodiments of the present disclosure disclose a thin film transistor, a fabrication method thereof, a repair method thereof, and an array substrate. The thin film transistor comprises a gate electrode (12), a gate insulating layer (13), an active layer (14), a source electrode (16) and a drain electrode (17). The source electrode (16) comprises a first source electrode portion (161) and a second source electrode portion (162) independent from each other, the first source electrode portion (161) and the second source electrode portion (162) are electrically connected with the active layer (14), respectively; and/or, the drain electrode (17) comprises a first drain electrode portion (171) and a second drain electrode portion (172) independent from each other, the first drain electrode portion (171) and the second drain electrode portion (172) are electrically connected with the active layer (14), respectively.

Abstract: Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to bc separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type.

Abstract: An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer st

Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a gate structure and depositing an insulating material around the gate structure; selectively etching an active device area; forming a set of spacers on the sides of the gate structure; growing a doped source and drain region; depositing an insulator over an upper surface of a deposited etch stop layer; and depositing a metal into a contact opening to form one or more contacts.

Abstract: A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a AlxGa(1-X)N (AlGaN) layer over the III-V semiconductor compound, a gate over the AlGaN layer, a passivation film over the gate and over a portion of the AlGaN layer, a source structure, and a drain structure on an opposite side of the gate from the source structure, wherein X ranges from 0.1 to 1. The source structure has a source contact portion and an overhead portion. The overhead portion is over at least a portion of the passivation film between the source contact portion and the gate. A distance between the source contact portion and the gate is less than a distance between the gate and the drain structure.

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

Abstract: Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes a bottom spacer formed on a lower part of a sidewall of the gate structure and an upper spacer formed on an upper part of the sidewall of the gate structure. In addition, the upper spacer includes an air gap formed in a dielectric material.

Abstract: A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.

Abstract: A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.

Abstract: An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the semiconductor fin and having upper surfaces below an uppermost surface of the semiconductor fin. Another embodiment of a transistor has first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

Abstract: A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.

Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).