Patents Issued in November 12, 2020
  • Publication number: 20200357727
    Abstract: Packaging methods and structures for lateral high voltage gallium nitride (GaN) devices achieve electrical isolation while also maintaining thermal dissipation. The electrical isolation reduces or eliminates vertical leakage current, improving high voltage performance. The packages may use or be compatible standards such as JEDEC, which reduces packaging cost and facilitates implementation of the packaged devices in conventional circuit design approaches.
    Type: Application
    Filed: May 10, 2020
    Publication date: November 12, 2020
    Inventors: Zhanming Li, Yue Fu, Yan-Fei Liu
  • Publication number: 20200357728
    Abstract: This disclosure relates to a flank wettable semiconductor device, having: a lead frame including a plurality of leads with a lead end portion and a semiconductor die mounted on the lead frame. The lead end portion comprises a recess portion having a height that corresponds to a thickness of the lead end portion, and a plate member mounted on the leadframe at the lead end portion.
    Type: Application
    Filed: May 4, 2020
    Publication date: November 12, 2020
    Applicant: NEXPERIA B.V.
    Inventors: Kan Wae Lam, Wai Hung William Hor, Sven Walczyk, Hans-Juergen Funke
  • Publication number: 20200357729
    Abstract: A packaged electronic device includes a package structure that encloses first and second semiconductor dies, a die attach pad with a first side attached to one of the dies, and a second side exposed along a side of the package structure, and a substrate that includes a first metal layer exposed along another side of the package structure, a second metal layer soldered to contacts of the dies, and an isolator layer that extends between and separates the first and second metal layers.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Woochan Kim, Anindya Poddar, Vivek Kishorechand Arora
  • Publication number: 20200357730
    Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Publication number: 20200357731
    Abstract: A power semiconductor module arrangement includes a semiconductor substrate arranged in a housing, and a mounting arrangement including a frame or body, and at least one terminal element coupled to the frame or body. The mounting arrangement is inserted in and coupled to the housing. The mounting arrangement has a lower surface which, when the mounting arrangement is inserted in and coupled to the housing, rests on at least one contact surface of the housing. When the mounting arrangement is inserted in and coupled to the housing, the at least one terminal element mechanically and electrically contacts the semiconductor substrate with a first end, and a distance between an upper surface of the semiconductor substrate and the at least one contact surface in a vertical direction equals a length of the first end between the upper surface of the semiconductor substrate and the lower surface of the mounting arrangement.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 12, 2020
    Inventor: Alexander Hoehn
  • Publication number: 20200357732
    Abstract: The present disclosure provides a package device including a conductive pad, a protecting block, and a redistribution layer. The protecting block is disposed on the conductive pad. The redistribution layer is disposed on the protecting block, and the conductive pad is electrically connected to the redistribution layer through the protecting block.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Inventors: Hsueh-Hsuan Chou, Chia-Chieh Fan, Kuan-Jen Wang, Cheng-Chi Wang, Yi-Hung Lin, Li-Wei Sung
  • Publication number: 20200357733
    Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Satoru KURAMOCHI, Sumio KOIWA, Hidenori YOSHIOKA
  • Publication number: 20200357734
    Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: TOPPAN PRINTING CO.,LTD.
    Inventors: Osamu KOGA, Yasuyuki HITSUOKA, Yoshito AKUTAGAWA
  • Publication number: 20200357735
    Abstract: A discrete tapering interconnection is disclosed that forms an interconnection between a first electronic circuit and a second electronic circuit within an integrated circuit. The discrete tapering interconnection includes a first set of multiple parallel conductors situated in a first metal layer of the metal layers of a semiconductor layer stack and a second set of multiple parallel conductors situated in a second metal layer of the metal layers of the semiconductor layer stack. The first set of multiple parallel conductors effectively taper the discrete tapering interconnection as the discrete tapering interconnection traverse between the first electronic circuit and/or the second electronic circuit. This tapering of the discrete tapering interconnection can be an asymmetric tapering or a symmetric tapering. The second set of multiple parallel conductors is arranged to form various interconnections between various parallel conductors from among the first set of multiple parallel conductors.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaskirat BINDRA, Kumar LALGUDI
  • Publication number: 20200357736
    Abstract: A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.
    Type: Application
    Filed: December 5, 2018
    Publication date: November 12, 2020
    Inventors: Minoru AKUTSU, Kentaro CHIKAMATSU
  • Publication number: 20200357737
    Abstract: An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Charles L. Arvin, Bhupender Singh, Mark Kapfhammer, Brian W. Quinlan, Sylvain Pharand
  • Publication number: 20200357738
    Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Publication number: 20200357739
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, source region, a gate electrode, a source contact, and a source via. The semiconductor fin has a length extending above the substrate. The source region is on the semiconductor fin. The gate electrode has a length across the semiconductor fin. The source contact is above the source region. The source via lands on the source contact and has a first dimension along a lengthwise direction of the semiconductor fin and has a second dimension along a lengthwise direction of the gate electrode from a top view. A ratio of the second dimension to the first dimension of the source via is greater than about 2.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy LIAW
  • Publication number: 20200357740
    Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Inventors: Jorge A. Kittl, Ganesh Hegde, Harsono Simka
  • Publication number: 20200357741
    Abstract: An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 12, 2020
    Inventor: Chih Cheng LIU
  • Publication number: 20200357742
    Abstract: Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.
    Type: Application
    Filed: September 28, 2017
    Publication date: November 12, 2020
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Tristan A. TRONIC, Rajat K. PAUL
  • Publication number: 20200357743
    Abstract: A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Nam Hoon Kim, Woon Seong Kwon, Teckgyu Kang
  • Publication number: 20200357744
    Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Khang Choong YONG, Eng Huat GOH, Min Suet LIM, Robert SANKMAN, Telesphor KAMGAING, Wil Choon SONG, Boon Ping KOH
  • Publication number: 20200357745
    Abstract: A flexible three-dimensional electronic device includes a polymer layer having a first side and a second side that is opposite of the first side. A first flexible substrate carrying a first electronic component is arranged on the first side of the polymer layer. A second flexible substrate carries a second electronic component. The second flexible substrate is a flexible silicon substrate arranged on the second side of the polymer layer. An electrically conductive via passes through the polymer layer to electrically connect the first and second electronic components.
    Type: Application
    Filed: March 4, 2019
    Publication date: November 12, 2020
    Inventor: Muhammad Mustafa HUSSAIN
  • Publication number: 20200357746
    Abstract: The objective of the invention is to provide a semiconductor module allowing the bandwidth between an MPU and a DRAM to be improved. This semiconductor module 1 comprises a logic chip 20, a RAM unit 40 which is a multi-layer RAM module, a spacer 60 disposed stacked over the RAM unit 40 in the layering direction thereof, an interposer 10 electrically connected to each of the logic chip 20 and the RAM unit 40, and a connection part 50 establishing a connection allowing for communication between the logic chip 20 and the RAM unit 40. The logic chip 20 and the spacer 60 are disposed to be adjacent to one another in a direction intersecting with the layering direction of the RAM unit 40, and the RAM unit 40 is placed on the interposer 10 while one end portion thereof overlaps with one end portion of the logic chip 20 in the layering direction. The connection part 50 connects the one end portion of the RAM unit 40 to the one end portion of the logic chip 20.
    Type: Application
    Filed: November 21, 2017
    Publication date: November 12, 2020
    Inventors: Yasuji KOSHIKAWA, Fumitake OKUTSU
  • Publication number: 20200357747
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Publication number: 20200357748
    Abstract: An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 12, 2020
    Inventors: Ashim DUTTA, Ekmini Anuja De Silva
  • Publication number: 20200357749
    Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
    Type: Application
    Filed: November 18, 2019
    Publication date: November 12, 2020
    Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Giorgio CELLERE, Diego TONINI, Vincent DICAPRIO, Kyuil CHO
  • Publication number: 20200357750
    Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
    Type: Application
    Filed: January 17, 2020
    Publication date: November 12, 2020
    Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Giorgio CELLERE, Diego TONINI, Vincent DICAPRIO, Kyuil CHO
  • Publication number: 20200357751
    Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng LIN, Takashi NOMA, Francis J. CARNEY
  • Publication number: 20200357752
    Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.
    Type: Application
    Filed: September 27, 2017
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Kyle Yazzie, Naga Sivakumar Yagnamurthy, Pramod Malatkar, Chia-Pin Chiu, Mohit Mamodia, Mark J. Gallina, Rajesh Kumar Neerukatti, Joseph Bautista, Michael Gregory Drake
  • Publication number: 20200357753
    Abstract: A flat plate frame is formed, which is flat plate-shaped, which has an opening penetrating its front and rear surfaces and groove terminal patterns formed on its front surface, and which contains a semi-cured thermosetting resin. Then, an insulating substrate is disposed on the rear surface so as to cover the opening of the flat plate frame, external connection terminals are disposed on the terminal patterns, and heating is carried out. As a result, a terminal package to which the insulating substrate and external connection terminals are firmly joined is produced using the flat plate frame. The external connection terminals included in the terminal package are reliably and firmly joined to the terminal package. Therefore, the external connection terminals are not displaced when wires are bonded to the external connection terminals.
    Type: Application
    Filed: March 31, 2020
    Publication date: November 12, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Toshio DENTA, Yuji ICHIMURA
  • Publication number: 20200357754
    Abstract: To generate a value unique to a device in a more preferable mode. A solid-state image sensor includes a plurality of unit pixels disposed in a two-dimensional array, and a drive control unit that controls a first drive to output signals from the unit pixels included in a first unit pixel group of the plurality of unit pixels as an image signal, and a second drive to detect variations in respective signals from two or more of the unit pixels included in a second unit pixel group of the plurality of unit pixels, in which the first unit pixel group and the second unit pixel group have different structures from each other.
    Type: Application
    Filed: November 15, 2018
    Publication date: November 12, 2020
    Inventors: Marie Toyoshima, Taishin Yoshida
  • Publication number: 20200357755
    Abstract: A transistor and method of manufacturing an electrically active chip seal ring surrounding the gate, gate insulator and source structure of the active core area of the transistor. The chip seal ring can be electrically coupled to the gate to seal the active core area from intrusions of contaminants, impurities, defects and or the like.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Inventors: M. Ayman SHIBIB, Kyle TERRILL
  • Publication number: 20200357756
    Abstract: Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such packaged module includes a low noise amplifier in an interior of a radio frequency shielding structure and an antenna external to the radio frequency shielding structure. The low noise amplifier includes a first inductor, an amplification circuit, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier. The radio frequency shielding structure can extend above a package substrate. The antenna can be on the package substrate. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.
    Type: Application
    Filed: March 16, 2020
    Publication date: November 12, 2020
    Inventors: Leslie Paul Wallis, Hoang Mong Nguyen, Anthony James LoBianco, Gregory Edward Babcock, Darren Roger Frenette, George Khoury, René Rodríguez
  • Publication number: 20200357757
    Abstract: An antenna module includes a fan-out semiconductor package including an IC, an encapsulant encapsulating at least a portion of the IC, a core member having a first side surface facing the IC or the encapsulant, and a connection member including at least one wiring layer electrically connected to the IC and the core member and at least one insulating layer; and an antenna package including a plurality of first directional antenna members configured to transmit or receive a first RF signal. The fan-out semiconductor package further includes at least one second directional antenna member disposed on a second side surface of the core member opposing the first side surface of the core member, stood up from a position electrically connected to at least one wiring layer, and configured to transmit or receive a second RF signal.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Il KIM, Yong Ho BAEK, Jin Seon PARK, Young Sik HUR
  • Publication number: 20200357758
    Abstract: A semiconductor substrate has, on an Au electrode pad, an electrolessly-plated Ni film/an electrolessly-plated Pd film/an electrolessly-plated Au film or an electrolessly-plated Ni film/an electrolessly-plated Au and a method of manufacturing the semiconductor substrate by the steps indicated in (1) to (6) below: (1) a degreasing step; (2) an etching step; (3) a pre-dipping step; (4) a Pd catalyst application step; (5) an electroless Ni plating step; (6) an electroless Pd plating step and electroless Au plating step or an electroless Au plating step.
    Type: Application
    Filed: October 25, 2018
    Publication date: November 12, 2020
    Inventors: Takuto WATANABE, Katsuyuki TSUCHIDA
  • Publication number: 20200357759
    Abstract: Even in a case where a pad becomes smaller, solder connection strength is improved. A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.
    Type: Application
    Filed: October 19, 2018
    Publication date: November 12, 2020
    Inventor: TAKUYA NAKAMURA
  • Publication number: 20200357760
    Abstract: A semiconductor package includes a semiconductor substrate, an interconnect structure disposed over the substrate, a first passivation layer disposed over an interconnect structure, a contact pad disposed over the first passivation layer, a dummy disposed around the contact pad and over the first passivation layer, and a second passivation layer overlaying the dummy and the contact pad.
    Type: Application
    Filed: May 6, 2020
    Publication date: November 12, 2020
    Inventors: Yao-Chun CHUANG, Hong-Seng SHUE, Chen-Nan CHIU, Li-Huan CHU, Mirng-Ji LII
  • Publication number: 20200357761
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Inventors: John Moore, Joseph F. Brooks
  • Publication number: 20200357762
    Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern including a single via. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first via surrounding a second via. The first and second vias are concentric with one another about a central point of the second via layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Inventors: Chia-Chan Chen, Yueh-Chuan Lee
  • Publication number: 20200357763
    Abstract: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Inventors: Glenn Rinne, Daniel Richter
  • Publication number: 20200357764
    Abstract: Embodiments may relate to a microelectronic package comprising that includes a solder thermal interface material (STIM). The STIM may include indium and a dopant material which may provide a number of benefits to the STIM. The STIM may physically and thermally couple a die and an integrated heat spreader (IHS). Other embodiments may be described or claimed.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Susmriti Das Mahapatra, Bamidele Daniel Falola, Amitesh Saha, Peng Li
  • Publication number: 20200357765
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: PEI-JHEN WU, HSIH-YANG CHIU, CHIANG-LIN SHIH, CHING-HUNG CHANG, YI-JEN LO
  • Publication number: 20200357766
    Abstract: A semiconductor package includes a plurality of intermediate dies and an encapsulant layer. The intermediate dies are stacked on a base die, in which the edge regions of the base die are exposed. The encapsulant layer is disposed to cover side surfaces of the intermediate dies as well as a surface of the exposed edge regions of the base die. The surface of the edge regions of the base die includes an adhesion enhancement layer.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventor: Kuo-Hui SU
  • Publication number: 20200357767
    Abstract: A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base.
    Type: Application
    Filed: August 14, 2019
    Publication date: November 12, 2020
    Applicant: Microchip Technology Incorporated
    Inventors: Justin Sato, Bomy Chen
  • Publication number: 20200357768
    Abstract: A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ching Shih, Chih-Wei Wu, Szu-Wei Lu
  • Publication number: 20200357769
    Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Publication number: 20200357770
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a top semiconductor die, a bottom semiconductor die, a first encapsulant, a second encapsulant, a third encapsulant, a first redistribution layer and a second redistribution layer. The top semiconductor die is stacked on the bottom semiconductor die. The bottom semiconductor die is laterally encapsulated by the third encapsulant, and the third encapsulant is laterally surrounded by the first encapsulant. The top semiconductor die is laterally encapsulated by the second encapsulant. The first redistribution layer is disposed between the top and bottom semiconductor dies. The bottom semiconductor die, the first encapsulant and the third encapsulant are located between the first and second redistribution layers.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Publication number: 20200357771
    Abstract: A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.
    Type: Application
    Filed: November 8, 2019
    Publication date: November 12, 2020
    Applicant: SK hynix Inc.
    Inventor: Jin Ha KIM
  • Publication number: 20200357772
    Abstract: A method for constructing a ramp-stacked chip assembly starts by obtaining a set of semiconductor chips, including a first chip and a set of additional chips. Next, the method stacks the set of additional chips one at a time over the first chip, wherein each additional chip is horizontally offset from a preceding additional chip to form a ramp-stack. While stacking each additional chip, the method: applies an adhesive layer to a surface of a preceding chip in the ramp-stack; and uses a vacuum tool to pick up the additional chip and place the additional chip on the adhesive layer of the preceding chip. During this pick-and-place process, the vacuum tool spans most of a surface of the additional chip and also provides planar support for the additional chip, which causes a holding force of the vacuum tool to flatten the additional chip prior to placement on the preceding chip.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: Oracle International Corporation
    Inventors: Yue Zhang, Michael H. S. Dayringer, Nyles Nettleton
  • Publication number: 20200357773
    Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
  • Publication number: 20200357774
    Abstract: Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 12, 2020
    Inventors: Stefano OGGIONI, Thomas BRUNSCHWILER, Gerd SCHLOTTIG
  • Publication number: 20200357775
    Abstract: A light-emitting apparatus and a method for manufacturing the same are provided in which heat dissipation from an LED package to a heat sinking substrate is improved while electrical insulation therebetween is ensured. The light-emitting apparatus includes a circuit board having an opening, an LED package inserted into the opening from the back side of the circuit board and having an edge connected to the back side of the circuit board, and a heat sinking substrate disposed on the back side of the circuit board so as to be in contact with the LED package.
    Type: Application
    Filed: May 30, 2017
    Publication date: November 12, 2020
    Applicants: Citzen Electronics Co., Ltd., Citzen Watch Co., Ltd.
    Inventors: Koki HIRASAWA, Nodoka OYAMADA, Yuji OMORI
  • Publication number: 20200357776
    Abstract: A display module comprises a circuit board, a plurality of light-emitting elements coupled to a front surface of the circuit board and arranged in an array configured to produce at least a portion of a display image at the front surface of the circuit board, and a contrast mask directly coupled to the front surface of the circuit board, the contrast mask defining a plurality of windows, with each window surrounding a group of one or more of the plurality of light-emitting elements.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Inventors: Ryan Joseph Nielsen, Gregory Lynn Rauen, Matthew Craig Buisker