Abstract: A display unit of the present disclosure includes a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor. One channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.

Abstract: A display device including a display portion with an extremely high resolution is provided. The display device includes a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.

Abstract: A method of fabricating an array substrate, an array substrate, and a display device is disclosed. The array substrate comprises a display area and a wiring area. The display area is disposed with a first thin film transistor and a second thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor comprises first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove comprises a first sub-groove and a second sub-groove that are stacked. The method includes simultaneously forming the first vias and the first sub-groove, and simultaneously forming the second vias and the second sub-groove.

Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.

Abstract: The invention discloses a global shutter CMOS image sensor. Each pixel unit of the global shutter CMOS image sensor includes a photo diode, a storage region and a first reset region, wherein the photo diode includes a first photosensitive doped region; a gate structure of a first transfer transistor is formed between the storage region and the first photosensitive doped region; a gate structure of a global shutter transistor is formed between the first reset region and the first photosensitive doped region; and inhomogeneous potentials are formed in the first photosensitive doped region through a doping structure. According to the invention, photo-induced carriers in the PDs of the pixel units, especially photo-induced carriers in the PDs of large pixel units, can be simultaneously and completely transferred to the storage region and the first reset region, and the overall performance of the device is improved.

Abstract: A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions.

Abstract: Disclosed are methods of fabricating short-wave infrared detector arrays including readout and absorption wafers connected by a recrystallized a-Si layer. The absorber wafer includes a SWIR conversion layer with a Ge1-xSnx alloy composition. Process steps realize the readout wafer and a portion of the absorption wafer, including bonding the readout wafer and a first portion of the absorption wafer. The a-Si intermediate layer linking the readout wafer and the first portion of the absorption wafer the a-Si intermediate layer is recrystallized by applying heat by a light source. The method assures a temperature profile between the light entrance surface and the CMOS electronic layer of the readout wafer maintaining readout layer temperature <350° C. during recrystallization. After the recrystallization process step the absorption wafer is completed by depositing the SWIR conversion layer. Also disclosed is a SWIR detector array realized by the method and SWIR detector array applications.

Abstract: A method of manufacturing an image sensing apparatus includes: forming a first substrate structure including a first region of a pixel region, the first substrate structure having a first surface and a second surface; forming a second substrate structure including a circuit region for driving the pixel region, the second substrate structure having a third surface and a fourth surface; bonding the first substrate structure to the second substrate structure, such that the first surface is connected to the third surface; forming a second region of the pixel region on the second surface; forming a first connection via, the first connection via extending from the second surface to pass through the first substrate structure; mounting semiconductor chips on the fourth surface, using a conductive bump; and separating a stack structure of the first substrate structure, the second substrate structure, and the semiconductor chips into unit image sensing apparatuses.

Abstract: An image sensor (e.g., an image sensor pixel) includes floating diffusion to receive charge, an output node to provide a voltage corresponding to the charge in the floating diffusion, a current supply, and a MOSFET in a source-follower configuration: the MOSFET includes a source coupled to the current supply and to the output node and a drain coupled to a voltage supply. The MOSFET also includes a gate coupled to the floating diffusion and a channel region disposed beneath the gate and having a length that extends between a source end where the channel region contacts the source and a drain end where the channel region contacts the drain. The channel region has a varying width; the drain-end width is wider than the source-end width.

Abstract: A structure has first pixels constituted of a laminate including a light-receiving element, a color filter, and a near-infrared cut filter, and second pixels including a near-infrared transmitting filter. The near-infrared cut filter includes a predetermined near-infrared absorbing colorant, a resin having a glass transition temperature of 100° C. or higher, and a surfactant.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a light pipe structure. A photodetector disposed within a semiconductor substrate. A gate electrode is over the semiconductor substrate and borders the photodetector. An inter-level dielectric (ILD) layer overlies the semiconductor substrate. A conductive contact is disposed within the ILD layer such that a bottom surface of the conductive contact is below a top surface of the gate electrode. The light pipe structure overlies the photodetector such that a bottom surface of the light pipe structure is recessed below a top surface of the conductive contact.

Abstract: Provided is a laminated lens structure capable of corresponding various optical parameters. The laminated lens structure includes at least one or more sheets of first lens-attached substrates and at least one or more sheets of second lens-attached substrates as a lens-attached substrate including a lens resin portion that forms a lens, and a carrier substrate that carries the lens resin portion. The carrier substrate of the first lens-attached substrates is constituted by laminating a plurality of sheets of carrier configuration substrates in a thickness direction, and the carrier substrate of the second lens-attached substrates is constituted by one sheet of carrier configuration substrate. For example, the present technology is applicable to a camera module and the like.

Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable further downsizing of device size. The device includes: a first structural body and a second structural body that are layered, the first structural body including a pixel array unit, the second structural body including an input/output circuit unit, and a signal processing circuit; a first through-via, a signal output external terminal, a second through-via, and a signal input external terminal that are arranged below the pixel array, the first through-via penetrating through a semiconductor substrate constituting a part of the second structural body, the second through-via penetrating through the semiconductor substrate; a substrate connected to the signal output external terminal and the signal input external terminal; and a circuit board connected to a first surface of the substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.

Abstract: Disclosed herein is an apparatus comprising: an array of avalanche photodiodes (APDs), each of the APDs comprising an absorption region and an amplification region; wherein the absorption region is configured to generate charge carriers from a photon absorbed by the absorption region; wherein the absorption region comprises a silicon epitaxial layer; wherein the amplification region comprises a junction with an electric field in the junction; wherein the electric field is at a value sufficient to cause an avalanche of charge carriers entering the amplification region, but not sufficient to make the avalanche self-sustaining; wherein the junctions of the APDs are discrete.

Abstract: Disclosed is a low temperature method of fabrication of short-wave infrared (SWIR) detector arrays (FPA) including a readout wafer and absorption layer connected for improved performances. The absorber layer includes a SWIR conversion layer with a GeSn or SiGeSn alloy. A first series of process steps realizes a CMOS processed readout wafer. A buffer layer is transferred on the readout wafer and annealed at temperatures compatible with the CMOS substrate, achieving a high quality crystalline buffer layer. The method assures a temperature profile between the light entrance surface of the buffer layer, and the readout electronics so the annealing temperature remains compatible with the CMOS. The buffer layer is used for further growth of a GeSn or SiGeSn structure to create the conversion layer and achieve the final structure of the SWIR FPA. Also disclosed is a SWIR FPA detector as realized by such method, and SWIR FPA applications.

Abstract: An image sensor module comprises: a substrate having a first side and second side, the first side being an opposite of the second side, an image sensor attached to the first side of the substrate, bonding wires to bond the image sensor to pads on the first side of the substrate, a protective structure disposed on the first side of the substrate surrounding the image sensor, the bonding wires, and the pads, the protective structure having a dam and a lid, a cover glass disposed on the protective structure, and a set of solder balls attached to the second side of the substrate.

Abstract: The present invention provides a foldable display panel, the foldable display panel includes a first display region, a second display region, and a folding region. The first display region includes a plurality of first pixel units. The second display region includes a plurality of second pixel units corresponding to the plurality of first pixel units. The second display region covers the first display region along the folding region when the folding region is deformed, and each of the plurality of second pixel units is located above corresponding each of the plurality of first pixel units.

Abstract: An optoelectronic circuit including a substrate and display pixels, each display pixel having a first light-emitting diode adapted to emit a first radiation and a second light-emitting diode adapted to emit a second radiation, the first light-emitting diode having a planar structure and resting on the substrate and the second light-emitting diode having a tridimensional structure and resting on the first light-emitting diode or crossing at least partially through the first light-emitting diode.

Abstract: A method of assembling a display area includes selecting a first tile from a plurality of tiles, each tile of the plurality of tiles includes a predetermined parameter and a plurality of microLEDs defining a plurality of pixels. The selecting the first tile based on a value of the predetermined parameter of the first tile. The method includes selecting a second tile from the plurality of tiles based on a value of the predetermined parameter of the second tile. The method further includes positioning the first tile and the second tile into an array defining at least a portion of the display area. A first edge of the first tile facing a second edge of the second tile. A display device including the display area assembled by the method is also provided.

Abstract: A light-emitting diode unit for a display including a plurality of pixels each including: first, second, and third light-emitting cells respectively including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; pads electrically connected to the first through third light-emitting cells to independently drive the first through third light-emitting cells; a first wavelength converter for converting a wavelength of light emitted from the first light-emitting cell; and a second wavelength converter for converting a wavelength of light emitted from the second light-emitting cell, in which the first wavelength converter converts a wavelength of light to a longer wavelength than the second wavelength converter, the second light-emitting cell has a greater area than the third light-emitting cell, and the first light-emitting cell has a greater area than the second light-emitting cell.

Abstract: A light emitting diode (LED) light source substrate includes a substrate, a plurality of LEDs of a flip-chip type, a bonding sheet, a plurality of reflective layers, and a substrate reflective layer, formed on the substrate, configured to reflect a first light that passes between the plurality of reflective layers and is incident on the bonding sheet. A reflectivity of the substrate reflective layer configured to reflect the first light is substantially equal to a reflectivity of the plurality of reflective layers configured to reflect a second light incident on the plurality of reflective layers from a side opposite to the substrate.

Abstract: A pseudosubstrate for an optoelectronic device suitable for the growth of light-emitting diodes including a substrate and a buffer structure formed on an upper face of the substrate. The buffer structure includes at least one first portion wherein one layer made of solid gallium nitride (GaN) delimits at least one free surface of a first type facing away from the upper face of the substrate, each free surface of the first type being suitable for the growth on same of at least one light-emitting diode mostly based on a III-V compound capable of emitting light at a first wavelength.

Abstract: A family of composite resonator devices having improved performance properties for use in electronic circuits. Each composite device includes two or more resonator electrodes on a single crystal or other resonant material. The two resonators may be connected in series or parallel, based on application requirements. The two resonators have different surface areas or some other type of asymmetry, causing the response of the composite device to have suppressed spurious modes, reduced insertion loss, or both. This is accomplished by designing the electrodes to have different frequency response curves, where the responses can be tuned and combined to reduce undesirable modes. Improvements in acceleration sensitivity and temperature sensitivity are also achieved. Both physically-applied and projected electrode types are disclosed, along with several crystal shapes. The family of composite resonator devices includes both passive and active devices, such as resonators, filters and oscillators.

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

Abstract: Some embodiments relate to a memory device. The memory device includes a top electrode overlying a bottom electrode. A data storage layer overlies the bottom electrode. The bottom electrode cups an underside of the data storage layer. The top electrode overlies the data storage layer. A top surface of the bottom electrode is aligned with a top surface of the top electrode.

Abstract: Embodiments of the present invention are directed to forming a Resistive Random Access Memory (RRAM) device with a spacer for electrode isolation. In a non-limiting embodiment of the invention, a memory stack including a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode is formed. A portion of the memory stack is removed to expose a sidewall of the top electrode and a spacer is formed on the sidewall of the top electrode. The spacer is positioned to encapsulate the top electrode, physically preventing a short between the top electrode and the bottom electrode.

Abstract: An organic light emitting diode display substrate includes a light emitting unit layer, a first band gap layer and a color conversion layer. The first band gap layer and the color conversion layer are on a light exit path of the light emitting unit layer. The light emitting unit layer includes first, second and third light emitting units periodically arranged on a driving substrate and emitting light of a first color. The color conversion layer converts a part of the light of the first color into light of a second color and a third color. The first band gap layer is between the light emitting unit layer and the color conversion layer. The first band gap layer transmits the light of the first color in a light exit direction, and reflects the light of the second color and the light of the third color.

Abstract: A display device according to the present disclosure includes a substrate, a lens layer including a lens, a pixel electrode disposed between the substrate and the lens layer, and a color filter disposed between the pixel electrode and the lens layer. The color filter includes a colored portion that overlaps a part of the pixel electrode in plan view and is disposed between the substrate and the lens layer. The pixel electrode is provided in a display region in which an image is displayed. The lens overlaps a part of the pixel electrode in the plan view. A distance between the center of the pixel electrode and the display center of the display region is shorter than a distance between the center of the lens and the display center in the plan view.

Abstract: The present invention teaches an OLED display panel which includes an array substrate, an encapsulation cover, and an organic lighting unit sealed in between by encapsulation adhesive. The OLED display panel is characterized in that a chip bonding element is configured on the array substrate. The encapsulation cover is configured with electrically connected touch electrode layer and first connection electrodes. The organic lighting unit includes a pixel definition layer. Insulating support columns are disposed on the pixel definition layer. A second connection electrode is disposed on each support column electrically connecting the chip bonding element. Each support column reaches a first connection electrode so that the first connection electrode is electrically connected to the chip bonding element. The present invention also teaches a display device incorporating the above-described OLED display panel.

Abstract: A display apparatus includes a substrate including a display area configured by a plurality of emission areas and a non-emission area between the plurality of emission areas; an encapsulation part which covers a display area; a touch part including a plurality of insulating layers disposed on the encapsulation part and a touch line in the non-emission area; and a plurality of light extraction patterns disposed between the touch line and the plurality of emission areas, in which the plurality of light extraction patterns includes grooves at at least a portion of the plurality of insulating layers.

Abstract: An input sensor includes a first pattern and a second pattern overlapping with the first pattern with an intermediate insulating layer interposed therebetween. The second pattern is disposed on the intermediate insulating layer and connected to the first pattern via a contact hole defined through the intermediate insulating layer. The first pattern includes a first mesh line extending along a reference direction, and the second pattern includes a second mesh line extending along the reference direction and overlapping with the first mesh line. An edge of the first mesh line and an edge of the second mesh line are not aligned with each other along a direction perpendicular to a line width direction and the reference direction.

Abstract: Disclosed is a display device with integrated touch screen, which prevents external light from being reflected by touch electrodes without a polarizer. The display device includes an organic light emitting device layer disposed on a substrate, a plurality of color filters disposed on the organic light emitting device layer, a plurality of first touch electrodes and a plurality of second touch electrodes disposed on the plurality of color filters to overlap a boundary portion between the plurality of color filters, and a black matrix disposed on the plurality of first touch electrodes and the plurality of second touch electrodes to overlap the plurality of first touch electrodes and the plurality of second touch electrodes.

Abstract: A display apparatus including an organic light-emitting display panel and a touch sensing unit disposed on the organic light-emitting display panel is disclosed. The touch sensing unit includes a touch electrode and a wiring part connected to the touch electrode. The wiring part of the touch sensing unit passes a protruding member disposed on a non-display region of the organic light-emitting display panel, and forms a first wiring part which does not overlap the protruding member, a second wiring part overlapping the protruding part, and a connection wiring part disposed between the first and second wiring parts and having a wiring width less than the first and second wiring parts so as to overlap an edge of the protruding member.

Abstract: A full-color display and techniques for fabrication thereof are provided. The display includes first and second continuous independently addressable organic emissive layers disposed over a single substrate or between two substrates or portions of a flexible substrate. The use of continuous emissive layers of a limited number of colors allows for a relatively high resolution display to be achieved without the use of fine metal masks or similar components.

Abstract: A pixel arrangement including first groups of sub-pixels arranged in a first direction, each of the first groups including first sub-pixels and third sub-pixels arranged alternately, and second groups of sub-pixels arranged in the first direction, each of the second groups including third sub-pixels and second sub-pixels arranged alternately. The first groups and the second groups are alternately arranged in a second direction perpendicular to the first direction. The first groups and the second groups are arranged to form third groups of sub-pixels arranged in the second direction and fourth groups of sub-pixels arranged in the second direction. The third groups and the fourth groups are alternately arranged in the first direction. Each of the third groups includes first sub-pixels and third sub-pixels arranged alternately. Each of the fourth groups includes third sub-pixels and second sub-pixels arranged alternately.

Abstract: A pixel arrangement includes a plurality of first groups of sub-pixels arranged in a first direction, each first group including first sub-pixels and third sub-pixels arranged alternately. A plurality of second groups of sub-pixels are arranged in the first direction, each second group including third sub-pixels and second sub-pixels arranged alternately. The first groups and the second groups are alternately arranged in a second direction substantially perpendicular to the first direction. The first groups and the second groups are arranged to form a plurality of third group sub-pixels arranged in the second direction and a plurality of fourth groups arranged in the second direction, the third groups and the fourth groups being alternately arranged in the first direction. Each of the third groups includes first sub-pixels and third sub-pixels alternately arranged, and each of the fourth groups includes third sub-pixels and second sub-pixels alternately arranged.

Abstract: Display unevenness in a display panel is suppressed. A display panel with a high aperture ratio of a pixel is provided. The display panel includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a first light-emitting layer, a second light-emitting layer, a third light-emitting layer, a first common layer, a second common layer, a common electrode, and an auxiliary wiring. The first common layer is positioned over the first pixel electrode and the second pixel electrode. The first common layer has a portion overlapping with the first light-emitting layer and a portion overlapping with the second light-emitting layer. The second common layer is positioned over the third pixel electrode. The second common layer has a portion overlapping with the third light-emitting layer.

Abstract: A pixel arrangement structure of display panel and a display apparatus, which are used to solve the technical problem of low pixel aperture ratio of an organic light emitting diode display panel. Herein, a pixel arrangement structure of display panel includes: a plurality of sub-pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel; where the first sub-pixel, the second sub-pixel, and the third sub-pixel have a polygonal structure with different numbers of sides, and distances between any adjacent two of the plurality of sub-pixels are equal.

Abstract: A display device includes a cover window that includes a first plane portion and first side portions that form curved sides, and a display panel that includes a first plane area corresponding to the first plane portion and first curved areas corresponding to the first side portions, where the display panel further includes a substrate, a plurality of first type pixels that are disposed in the first plane area and each including a first light emitting diode that is parallel with one side of the substrate, and a plurality of second type pixels that are disposed in the first curved areas, and each including a second light emitting diode that includes at least one non-flat portion forming a non-flat side that is not parallel with one side of the substrate.

Abstract: A display panel includes at least two pixel repeating units arranged in an array. Each of the pixel repeating units at least includes a first pixel, a second pixel, and a third pixel. A shape of the first pixel includes a convex arc, and each of shapes of the second pixel and the third pixel includes a convex arc and a concave arc. Shapes of edges of two of the first pixel, the second pixel, and the third pixel are complementary in at least one of a first direction, a second direction, a third direction, and a fourth direction, the first direction is perpendicular to the second direction, the third direction is a direction having an angle of less than 90 degrees with the first direction, and the fourth direction is perpendicular to the third direction.

Abstract: An array substrate and display device are disclosed. The array substrate includes signal lines; IC connection lines; the IC connection lines include at least two IC connection line groups, the at least two IC connection line groups include a first IC connection line group and a second IC connection line group, the base substrate further includes a dummy area, the dummy area is provided with a floating pattern, the dummy area includes a separation area and two sub-dummy areas, an extending line of the signal line corresponding to a first IC connection line and an extending line of the signal line corresponding to a second IC connection line respectively fall into the separation area, at least in the separation area, the floating pattern only includes first floating lines substantially extending along the second direction.

Abstract: A display substrate including a base substrate and a pixel defining layer is provided. The pixel defining layer includes a first defining layer and a second defining layer, which define a plurality of lower openings and a plurality of upper openings corresponding to the plurality of lower openings, respectively. An orthographic projection of a bottom surface of each upper opening on the base substrate covers that of a corresponding lower opening on the base substrate, orthographic projections of bottom surfaces of the plurality of upper openings on the base substrate have an equal area. The plurality of lower openings include a first lower opening, a second lower opening and a third lower opening, which form a first cavity, a second cavity and a third cavity respectively together with a corresponding upper opening.

Abstract: A display apparatus includes: a substrate that includes a display area, an opening area formed in the display area, and a non-display area that surrounds at least a portion of the opening area; a pixel defining area formed on the substrate and that includes at least one opening; an intermediate layer disposed on the at least one opening; an opposite electrode that covers the intermediate layer and the pixel defining layer; and a capping layer that covers the opposite electrode. An end portion of at least one of the intermediate layer, the opposite electrode, or the capping layer is formed on the pixel defining layer and has a thickness that decreases away from the at least one opening.

Abstract: An array substrate includes a base substrate including a plurality of pixel regions arranged in an array, a plurality of thin film transistors distributed within respective ones of the plurality of pixel regions, each of the thin film transistors including an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode including a first portion located in a second via, a passivation layer located on the source electrodes and the drain electrodes. The passivation layer is on the first portions of the drain electrode. A plurality of pixel electrodes are distributed within respective ones of the plurality of pixel regions and located on the passivation layer. Each of the pixel electrodes are electrically connected to a respective one of the drain electrodes through a respective third via that extends through the passivation layer.

Abstract: A display device includes a display panel and an optical member. The display panel includes a lower substrate and an upper substrate. The display panel forms a light-transmitting area and a display area near the light-transmitting area. The optical member is adjacent to a rear surface of the display panel and overlaps with a portion corresponding to the light-transmitting area. The display area includes a thin film transistor and an organic light emitting element configured to receive a current from the thin film transistor. The light-transmitting area does not include a metal layer, which is disposed in the display area. The upper substrate and the lower substrate do not have a through-hole structure in the light-transmitting area.

Abstract: An organic light emitting diode display includes: a substrate; a scan line formed over the substrate and transmitting a scan signal; a data line crossing the scan line and transmitting a data voltage; a driving voltage line crossing the scan line and transmitting a driving voltage; a switching transistor connected to the scan line and the data line; a driving transistor connected to the switching transistor; a driving connection member connected to a driving gate electrode of the driving transistor; a storage capacitor including a first storage electrode and a second storage electrode; a pixel electrode electrically connected to the driving transistor; and a contact hole connecting the first storage electrode and the driving connection member. The second storage electrode may include a cut-out by a curved edge at least partially surrounding the contact hole, and the pixel electrode may be formed not to overlap the cut-out.

Abstract: An OLED display panel and a method of manufacturing same are provided. The OLED display panel is provided with a light shielding layer between an OLED back plate and a package cover plate above a pixel spaced area to block lateral light leakage of pixels, thereby limiting light emitted by each of the top emission OLEDs to be emitted in a corresponding pixel, thereby effectively avoiding issue of lateral light leakage and color mixing of the pixels. In the method of manufacturing the OLED display panel, a light shielding layer is provided between an OLED back plate and a package cover plate above the pixel spaced area to block lateral light leakage of pixels, thereby limiting light emitted by each of the top emission OLEDs to be emitted in a corresponding pixel, thereby effectively avoiding issue of lateral light leakage and color mixing of the pixels.

Abstract: A method for repairing a display substrate includes detecting whether there is a fault point on signal lines. If a fault point is detected on a signal line, short-circuiting is performed of two sides of the at least one fault point through line portions of two drive power lines respectively located at two sides of the at least one fault point and perpendicular to the signal line where the at least one fault point is located and a line portion of a drive power line located at one side of the at least one fault point and parallel to the signal line where the at least one fault point is located.

Abstract: An organic light emitting display panel and a display device are provided. The organic light emitting display panel includes: an anode power wire, the anode power wire including a first extension segment and a second extension segment, a head end of the first extension segment being electrically connected to the driving power supply, a tail end of the first extension segment being electrically connected to a head end of the second extension segment; each sub-pixel includes a light emitting device and two pixel driving circuits, anode connection terminals of the two pixel driving circuits are electrically connected to an anode of the light emitting device; anode power wire connection terminals of the two pixel driving circuits are electrically connected to the first extension segment and the second extension segment, respectively.

Abstract: A display device including a display panel including a display substrate having a display area and a pad area around the display area, and a plurality of signal wirings disposed in the pad area of the display substrate, a base film attached to the pad area of the display substrate, a plurality of lead wirings disposed on the base film and connected to the plurality of signal wirings, and a first curable pattern disposed between adjacent ones of the lead wirings, in which a surface height of the first curable pattern from a surface of the base film is less than a surface height of the lead wirings from the surface of the base film.