Patents Issued in November 12, 2020
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Publication number: 20200357677Abstract: An example of a printed structure comprises a target substrate and a structure protruding from a surface of the target substrate. A component comprising a component substrate separate and independent from the target substrate is disposed in alignment with the structure on the surface of the target substrate within 1 micron of the structure. An example method of making a printed structure comprises providing the target substrate with the structure protruding from the target substrate, a transfer element, and a component adhered to the transfer element. The component comprises a component substrate separate and independent from the target substrate. The transfer element and adhered component move vertically toward the surface of the target substrate and horizontally towards the structure until the component physically contacts the structure or is adhered to the surface of the target substrate. The transfer element is separated from the component.Type: ApplicationFiled: May 12, 2020Publication date: November 12, 2020Inventors: Ronald S. Cok, David Gomez, Tanya Yvette Moore, Matthew Alexander Meitl, Christopher Andrew Bower
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Publication number: 20200357678Abstract: The invention discloses an ejector device for ejecting a chip disposed on a thin film. The chip has a first length in a first direction and a first width in a second direction. The ejector device comprises a pin cover defining a contacting surface. A pin hole, disposed on the contacting surface, has a second length in the first direction and a second width in the second direction. The contacting surface is configured to come into contact with the thin film. When the first length is larger than the second length, the first width is not larger than the second width. When the first width is larger than the second width, the first length is not larger than the second length.Type: ApplicationFiled: April 22, 2020Publication date: November 12, 2020Inventor: Chun-Wei TSAI
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Publication number: 20200357679Abstract: Embodiments of the present disclosure provide a heated support pedestal including a body comprising a ceramic material, a support arm extending radially outward from a periphery of the body that is coupled to a shaft, and a vacuum conduit disposed within the shaft and through the body to connect with a surface of the body.Type: ApplicationFiled: September 19, 2018Publication date: November 12, 2020Inventor: Vijay D. PARKHE
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Publication number: 20200357680Abstract: An electronic device comprises a dielectric structure, interconnect structures extending into the dielectric structure and having uppermost vertical boundaries above uppermost vertical boundaries of the dielectric structure, an additional barrier material covering surfaces of the interconnect structures above the uppermost vertical boundaries of the dielectric structure, an isolation material overlying the additional barrier material, and at least one air gap laterally intervening between at least two of the interconnect structures laterally-neighboring one another. Each of the interconnect structures comprises a conductive material, and a barrier material intervening between the conductive material and the dielectric structure. The at least one air gap vertically extends from a lower portion of the isolation material, through the additional barrier material, and into the dielectric structure. Electronic systems and method of forming an electronic device are also described.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Toyonori Eto, Kuo-Chen Wang
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Publication number: 20200357681Abstract: Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: TallannQuest LLC DBA Apogee SemiconductorInventor: Emily Ann Donnelly
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Publication number: 20200357682Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.Type: ApplicationFiled: July 28, 2020Publication date: November 12, 2020Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Scott L. Light, John A. Smythe, Sony Varghese
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Publication number: 20200357683Abstract: Semiconductor structure and method for forming semiconductor structure are provided. A substrate is provided, including a first dielectric layer, a first conductive layer and a second conductive layer. A first stop layer is formed on a top surface of the first conductive layer and a top surface of the second conductive layer, and a second stop layer is formed on a surface of the first dielectric layer. A second dielectric layer is formed on a surface of the first stop layer and a surface of the second stop layer. A first opening and a second opening are formed in the second dielectric layer by etching a portion of the second dielectric layer until the surface of the first stop layer is exposed. The first opening exposes the first stop layer on the first conductive layer, and the second opening exposes the first stop layer on the second conductive layer.Type: ApplicationFiled: May 4, 2020Publication date: November 12, 2020Inventor: Jiquan LIU
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Publication number: 20200357684Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Meng-Hsuan HSIAO, Yee-Chia YEO, Tung Ying LEE, Chih Chieh YEH
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Publication number: 20200357685Abstract: A method includes: forming a first conductive structure in a first dielectric layer; forming a conductive protection structure that is coupled to at least part of the first conductive structure; forming a second dielectric layer over the first dielectric layer; forming a via hole extending through at least part of the second dielectric layer to expose a portion of the conductive protection structure; cleaning the via hole; and refilling the via hole with a conductive material to form a via structure.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Hung-Chih YU, Chien-Mao Chen
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Publication number: 20200357686Abstract: A method is presented for constructing a dual metal interconnect structure. The method includes forming a trilayer stack over a dielectric layer, forming a plurality of vias extending through the trilayer stack and into the dielectric layer, depositing a first conductive material to fill the plurality of vias, etching the first conductive material to form first conductive regions, depositing a spacer, etching the spacer to form spacer portions adjacent the first conductive regions, and depositing a second conductive material.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Yann Mignot, Hsueh-Chung Chen
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Publication number: 20200357687Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Sean KING, Hui Jae YOO, Sreenivas KOSARAJU, Timothy GLASSMAN
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Publication number: 20200357688Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.Type: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
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Publication number: 20200357689Abstract: An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Paul Merle Emerson, Benjamin Stassen Cook
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Publication number: 20200357690Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Su-jeong PARK, Dong-chan LIM, Kwang-jin MOON, Ju Bin SEO, Ju-Il CHOI, Atsushi FUJISAKI
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Publication number: 20200357691Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU
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Publication number: 20200357692Abstract: A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu, Joe Lee
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Publication number: 20200357693Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Tang WU, Pao-Sheng CHEN, Pei-Hsuan LEE, Szu-Hua WU, Chih-Chien CHI
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Publication number: 20200357694Abstract: A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Inventors: You-Hua CHOU, Kuo-Sheng CHUANG
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Publication number: 20200357695Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet.Type: ApplicationFiled: May 8, 2020Publication date: November 12, 2020Inventors: Shigenori HARADA, Minoru MATSUZAWA, Hayato KIUCHI, Yoshiaki YODO, Taro ARAKAWA, Masamitsu AGARI, Emiko KAWAMURA, Yusuke FUJII, Toshiki MIYAI, Makiko OHMAE
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Publication number: 20200357696Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of heating the polyolefin sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyolefin sheet, then picking up each device chip from the polyolefin sheet.Type: ApplicationFiled: May 8, 2020Publication date: November 12, 2020Inventors: Shigenori HARADA, Minoru MATSUZAWA, Hayato KIUCHI, Yoshiaki YODO, Taro ARAKAWA, Masamitsu AGARI, Emiko KAWAMURA, Yusuke FUJII, Toshiki MIYAI, Makiko OHMAE
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Publication number: 20200357697Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Publication number: 20200357698Abstract: A semiconductor device production method includes providing a first electrode and a second electrode on a rear surface of a substrate where an active region emitting light is formed and providing a laminated object formed of a material less brittle than the substrate at part of a region between the first electrode and the second electrode so as to position directly below the active region; and exposing a plane on which the active region appears by cleavage of the substrate together with the laminated object in a state where the laminated object is located directly above the active region.Type: ApplicationFiled: March 29, 2018Publication date: November 12, 2020Applicant: Mitsubishi Electric CorporationInventors: Tatsuro YOSHINO, Masato SUZUKI, Masato NEGISHI, Kenji YOSHIKAWA
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Publication number: 20200357699Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.Type: ApplicationFiled: May 7, 2020Publication date: November 12, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU, Kaoru IDENO
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Publication number: 20200357700Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.Type: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventor: Wei-E Wang
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Publication number: 20200357701Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the VFET devices are provided. The methods may include forming a first channel region and a second channel region on a substrate, forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate, forming a bottom source/drain region in the recess of the substrate, forming a capping layer on the bottom source/drain region, removing the liner and the capping layer, forming a spacer on the substrate and the bottom source/drain region, and forming a gate structure on side surfaces of the first and second channel regions.Type: ApplicationFiled: December 23, 2019Publication date: November 12, 2020Inventors: Min Gyu KIM, Sa Hwan HONG
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Publication number: 20200357702Abstract: Disclosed is a manufacturing method of a complementary metal oxide semiconductor transistor, comprising a step of implementing a channel doping to an N-type channel region. The step comprises: preparing a low temperature polysilicon layer on a substrate, and patterning the low temperature polysilicon layer to form the N-type channel region correspondingly above a light shielding pattern; coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development; implementing the channel doping to the N-type channel region with shielding of the negative photoresist mask plate. Further disclosed is a manufacturing method of an array substrate, applied with the aforesaid manufacturing method of the complementary metal oxide semiconductor transistor.Type: ApplicationFiled: April 20, 2018Publication date: November 12, 2020Inventors: Yuxia CHEN, Chao HE
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Publication number: 20200357703Abstract: A method of forming a semiconductor structure includes forming a recess within a semiconductor substrate, the recess is located between adjacent fins of a plurality of fins on the semiconductor substrate, forming a first liner above a perimeter including the recess, top surfaces of the semiconductor substrate, and top surfaces and sidewalls of the plurality of fins, the first liner includes a first oxide material, forming a second liner directly above the first liner, and forming a third liner directly above the second liner, the third liner includes a nitride material, the second liner includes a second oxide material capable of creating a dipole effect that neutralizes positive charges generated within the third liner and between the third liner and the first liner.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Choonghyun Lee, Xin Miao, Alexander Reznicek, Jingyun Zhang
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Publication number: 20200357704Abstract: Systems and methods for measuring a dimension of a 3D structure of a semiconductor device, such as height of a pad or bump supported by a film layer. The methods can include obtaining raw data implicating a height of the 3D structure with a laser triangulation sensor and adjusting the raw data with a compensation factor that accounts for effects of the film layer and a thickness of the film layer.Type: ApplicationFiled: November 6, 2018Publication date: November 12, 2020Applicant: Onto Innovation Inc.Inventor: John Schaefer
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Publication number: 20200357705Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.Type: ApplicationFiled: October 30, 2019Publication date: November 12, 2020Applicant: SK hynix Inc.Inventors: Jee Won CHUNG, Dong Jin KIM, Byeung Ho KIM, Chang Hyun KIM
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Publication number: 20200357706Abstract: A method of manufacturing component carriers includes carrying out a test for each of multiple sections of a component-carrier structure, inserting at least one functional component in each of further sections of a further component-carrier structure to be connected with the component-carrier structure so that each further section assigned to a respective section having successfully passed the test is provided with at least one functional component, and inserting at least one functionally inactive dummy component in each of the further sections assigned to a respective section having failed the test.Type: ApplicationFiled: April 27, 2020Publication date: November 12, 2020Inventors: Marco Gavagnin, Gernot Schulz
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Publication number: 20200357707Abstract: A device and methods for forming the device is provided. The device includes a substrate and circuit elements thereon. The device further includes a metallization layer over the substrate. The metallization layer includes interconnects interconnecting the circuit elements. A test pad is disposed over an uppermost interconnect in the metallization layer. The test pad is coupled to one or more circuit elements via the interconnects. The test pad is configured for testing the one or more circuit elements. A crack stop protection seal surrounding the test pad is provided. The crack stop protection seal confines damage caused by probing at the test pad from propagating to an area beyond the crack stop protection seal.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Ramasamy CHOCKALINGAM, Juan Boon TAN, Wanbing YI
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Publication number: 20200357708Abstract: A substrate is orientated parallel to a plane and includes pads that are located at a bottom surface of the substrate and external to the electrical device. A first integrated circuit die is orientated parallel to the plane and disposed above the substrate in a vertical direction. The first integrated circuit die is electrically coupled to at least some of the pads of the substrate. A packaging material is disposed above the first integrated circuit die around at least a top surface and side surfaces of the first integrated circuit die. Test pads are orientated parallel to the plane and disposed above the first integrated circuit die in the vertical direction. The test pads are electrically coupled to the first integrated circuit die and encased within the packaging material.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Inventor: Joseph A. De La Cerda
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Publication number: 20200357709Abstract: A semiconductor device includes a first semiconductor portion and a second semiconductor portion. The first semiconductor portion provides a plurality of memory components, including a first substrate layer, a plurality of first interconnect conductive layers, a plurality of first conductive vias, and a plurality of first conductive contacts. The first conductive contacts electrically connect to the first conductive vias, and the first conductive contacts in combination with the first conductive vias are formed on a top first interconnect conductive layer of the first interconnect conductive layers. The second semiconductor portion provides a control circuit, including a second substrate layer and a plurality of second interconnect conductive layers.Type: ApplicationFiled: June 11, 2020Publication date: November 12, 2020Applicant: AP Memory Technology Corp.Inventors: Wen Liang CHEN, Lin MA, Chien-An YU, Chun Yi LIN
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Publication number: 20200357710Abstract: A power semiconductor module arrangement includes a semiconductor substrate arranged in a housing, at least one semiconductor body being arranged on the semiconductor substrate, and a mounting arrangement including a frame or body, a first terminal element, and a second terminal element. The mounting arrangement is inserted in and coupled to the housing. Each terminal element mechanically and electrically contacts the semiconductor substrate with a first end. A middle part of each terminal element extends through the frame or body. A second end of each terminal element extends outside the housing. The first terminal element is dielectrically insulated from the second terminal element by a portion of the frame or body. The first terminal element is injected into and inextricably coupled to the frame or body. The second terminal element is arranged within a hollow space inside the frame or body and is detachably coupled to the frame or body.Type: ApplicationFiled: May 5, 2020Publication date: November 12, 2020Inventor: Alexander Hoehn
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Publication number: 20200357711Abstract: A power semiconductor module arrangement includes a first switching element and a second switching element, each having a control terminal and a controllable load path between two load terminals, the load paths being operatively coupled in series and between a first supply node, and a second supply node. The switching elements are connected with each other via a first common node. An output node configured to be coupled to an output potential is coupled to the first common node. The first supply node is formed by a plurality of first terminals, the second supply node is formed by a plurality of second terminals, and the output node is formed by a plurality of third terminals. The switching elements are arranged inside a housing.Type: ApplicationFiled: May 5, 2020Publication date: November 12, 2020Inventor: Alexander Hoehn
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Publication number: 20200357712Abstract: An electronic component built-in wiring board includes a substrate having a cavity, an electronic component accommodated in the cavity of the substrate and having pads on a surface of the component, a coating insulating layer formed on the substrate such that the insulating layer is covering the component and has via holes, via conductors formed in the via holes such that the via conductors are penetrating through the insulating layer, and a resin coating formed between the component and the insulating layer and having through holes such that the through holes are partially exposing the pads in the via holes and that the coating has adhesion to the component that is stronger than adhesion of the insulating layer to the component. The via conductors are formed in the via holes and the through holes such that the via conductors are connected to the pads on the surface of the component.Type: ApplicationFiled: May 8, 2020Publication date: November 12, 2020Applicant: IBIDEN CO., LTD.Inventors: Yusuke TANAKA, Tomohiro Futatsugi, Yuichi Nakamura, Yoshiki Matsui, Keinosuke Ino, Tomohiro Fuwa, Seiji Izawa
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Publication number: 20200357713Abstract: A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member via bumps, the mounting member having a space between the first circuit member and the second circuit member; a step of preparing a sheet having a space maintaining layer; a disposing step of disposing the sheet on the mounting member such that the space maintaining layer faces the second circuit members; and a sealing step of pressing the sheet against the first circuit member and heating the sheet, to seal the second circuit members so as to maintain the space, and to cure the sheet. The bumps are solder bumps. The space maintaining layer after curing has a glass transition temperature of higher than 125° C., and a coefficient of thermal expansion at 125° C. or lower of 20 ppm/K or less.Type: ApplicationFiled: October 30, 2018Publication date: November 12, 2020Applicant: NAGASE CHEMTEX CORPORATIONInventors: Takayuki HASHIMOTO, Takuya ISHIBASHI, Kazuki NISHIMURA
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Publication number: 20200357714Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
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Publication number: 20200357715Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, where a packaged semiconductor device includes a package body having a recess in which a pressure sensor is exposed; a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and a protection layer including a plurality of beads embedded within a top region of the polymeric gel.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventor: Michael B. Vincent
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Publication number: 20200357716Abstract: The present disclosure relates to an air-cavity semiconductor package, which includes a thermal carrier, a ring structure, a package lid, and at least one semiconductor device. The thermal carrier has a carrier body, a heat slug residing within the carrier body, a top coating layer formed over a top surface of the heat slug, and a bottom coating layer formed over a bottom surface of the heat slug. The ring structure includes a ring body with an interior opening, which resides over the thermal carrier, such that a portion of a top surface of the thermal carrier is exposed through the interior opening. The package lid resides over the ring structure and has a recess conjoined with the interior opening forming an enclosed cavity. The at least one semiconductor device is attached to the exposed portion of the top surface of the thermal carrier and encapsulated in the enclosed cavity.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Robert Charles Dry, Christine Blair
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Publication number: 20200357717Abstract: A power module has a plurality of packaged power semiconductors, a printed circuit board, a heat sink, and possibly a sealing compound. The power semiconductors have electrically conductive connection elements and heat removal areas on respective outer sides. The power semiconductors are arranged on a cooling surface of the heat sink and has its heat removal area connected to the cooling surface of the heat sink to conduct heat, and the printed circuit board is arranged on a side of the power semiconductors that is opposite the heat sink in an orthogonal direction, wherein the connection elements of the power semiconductors make electrical contact with pads on the printed circuit board regions, for example, laterally beside an edge of the heat sink, in which a projection of the heat sink onto the printed circuit board in the orthogonal direction does not cover the connection elements.Type: ApplicationFiled: May 6, 2020Publication date: November 12, 2020Applicant: ZF Friedrichshafen AGInventor: Thomas Maier
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Publication number: 20200357718Abstract: In order to provide a conductive heat radiation film that can stabilize the shape, a conductive heat radiation film 30 includes: a first heated film 28 including a plurality of first metal particles 27b; and a plurality of carbon nanotubes 24 including tips 24a adhered to the first heated film 28.Type: ApplicationFiled: April 6, 2020Publication date: November 12, 2020Applicant: FUJITSU LIMITEDInventors: Shinichi Hirose, Daiyu Kondo
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Publication number: 20200357719Abstract: A power semiconductor device includes a frame, a semiconductor element, a substrate, and a sealing resin. The semiconductor element is disposed on the frame. The substrate is disposed on a side of the frame opposite to a side on which the semiconductor element is disposed. The sealing resin seals the semiconductor element and the substrate. The substrate includes a metal sheet, a first insulating sheet on one main surface side of the metal sheet, and a second insulating sheet on the other main surface side of the metal sheet. The metal sheet has flexibility at a normal temperature.Type: ApplicationFiled: April 2, 2020Publication date: November 12, 2020Applicant: Mitsubishi Electric CorporationInventors: Shinya NAKAGAWA, Takuya SHIRAISHI
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Publication number: 20200357720Abstract: A spacer structure, which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, includes: a conductive material layer which is composed of a composite material; an underlying plating layer disposed on the conductive material layer; and a copper plating layer disposed on the underlying plating layer, in which the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.Type: ApplicationFiled: November 26, 2019Publication date: November 12, 2020Inventors: Sung-Won PARK, Hyeon-Uk KIM, Tae-Hwa KIM, Jun-Hee PARK, Hyun-Koo LEE
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Publication number: 20200357721Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.Type: ApplicationFiled: May 9, 2019Publication date: November 12, 2020Applicant: Intel CorporationInventors: Robert Sankman, MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
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Publication number: 20200357722Abstract: An improved, liquid cooled, power semiconductor heat dissipation apparatus configured to accommodate surface-mount power semiconductor devices mounted on direct bond copper plates which are in thermal communication with a heat transfer surface and electrical communication with a printed circuit board or other surface on which the apparatus is mounted.Type: ApplicationFiled: July 10, 2019Publication date: November 12, 2020Inventors: Paul F. Carosa, David L. Bogdanchik
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Publication number: 20200357723Abstract: The present technology relates to a semiconductor device, an imaging device, and a manufacturing apparatus, capable of providing a semiconductor substrate maintaining and improving insulating performance. A through hole that penetrates the semiconductor substrate, an electrode at the center of the through hole, and a space around the electrode are included. The through hole also penetrates an insulating film formed on the semiconductor substrate. A barrier metal is further included around the electrode. An insulating film is further included in the semiconductor substrate and the space. The semiconductor device has a multilayer structure, and the electrode connects wirings formed in different layers to each other. The present technology can be applied to, for example, an image sensor in which a logic circuit and a sensor circuit are laminated.Type: ApplicationFiled: October 5, 2018Publication date: November 12, 2020Inventor: REIJIROH SHOHJI
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Publication number: 20200357724Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Haruki Ito, Nobuaki Hashimoto
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Publication number: 20200357725Abstract: A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Benjamin Stassen Cook, Nazila Dadvand, Sreenivasan Koduri
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Publication number: 20200357726Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.Type: ApplicationFiled: May 9, 2019Publication date: November 12, 2020Inventors: Nazila Dadvand, Sreenivasan Koduri, Benjamin Stassen Cook