Patents Issued in November 12, 2020
  • Publication number: 20200357877
    Abstract: A display device includes a plurality of node electrodes, a conductive layer above the plurality of node electrodes and including first extensions extending in a first direction and second extensions extending in a second direction intersecting the first direction, a plurality of pixel electrodes above the conductive layer, and an insulating layer covering an edge of each of the plurality of pixel electrodes, where a plurality of openings respectively corresponding to a portion of each of the plurality of pixel electrodes is defined in the insulating layer, a center of each of the plurality of openings overlaps one of intersections between the first and second extensions and the conductive layer overlaps the plurality of node electrodes.
    Type: Application
    Filed: February 27, 2020
    Publication date: November 12, 2020
    Inventors: Chaehan Hyun, Jongwon Park
  • Publication number: 20200357878
    Abstract: A display panel includes: a first substrate including an opening area, a display area, and a non-display area; a plurality of display elements arranged in the display area; a second substrate facing the first substrate with the plurality of display elements therebetween; a sealing member arranged between the first substrate and the second substrate; a first conductive line between the opening area and the display area, the first conductive line being located in the non-display area; a second conductive line located in the non-display area; and at least one insulating layer arranged between the first conductive line and the second conductive line.
    Type: Application
    Filed: March 19, 2020
    Publication date: November 12, 2020
    Inventors: Minjun JO, Jaekyung GO, Yongseung PARK, Seonggeun WON
  • Publication number: 20200357879
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Publication number: 20200357880
    Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: November 12, 2020
    Inventors: Dewei Xu, Sunil K. Singh, Siva R. Dangeti, Seung-Yeop Kook
  • Publication number: 20200357881
    Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
  • Publication number: 20200357882
    Abstract: A semiconductor device includes: a drift layer of a first conductivity type which is made of silicon carbide; a junction region formed on one main surface of the drift layer; a junction termination extended region of the drift layer, the junction termination extended region being formed outside the junction region when the one main surface is viewed in plan view, and the junction termination extended region containing an impurity of a second conductivity type opposite to the first conductivity type; and a guard ring region of the drift layer, the guard ring region being formed at a position overlapping the junction termination extended region when the one main surface is viewed in plan view, and the guard ring region containing the impurity of the second conductivity type with a concentration that is higher than that of the junction termination extended region, wherein in the junction termination extended region, the concentration of the impurity of the second conductivity type in a depth direction from the o
    Type: Application
    Filed: February 13, 2018
    Publication date: November 12, 2020
    Inventors: Akihiko SHIBUKAWA, Yusuke MAEYAMA, Shunichi NAKAMURA
  • Publication number: 20200357883
    Abstract: A power semiconductor device includes an active region having a total volume with a central volume forming at least 20% of the total volume, a peripheral volume forming at least 20% of the total volume and surrounding the central volume, and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The peripheral volume has a constant lateral distance from an edge termination region. A first doped semiconductor region is electrically connected with a first load terminal at a semiconductor body frontside. A second doped semiconductor region is electrically connected with a second load terminal at a semiconductor body backside. The first and/or second doped semiconductor region has: a central portion extending into the central volume and having a central average dopant dose; and a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose.
    Type: Application
    Filed: May 6, 2020
    Publication date: November 12, 2020
    Inventors: Manfred Pfaffenlehner, Josef-Georg Bauer, Frank Dieter Pfirsch, Thilo Scheiper, Konrad Schraml
  • Publication number: 20200357884
    Abstract: Embodiments of the invention are directed to a method that includes forming a first sacrificial nanosheet over a substrate and forming a first nanosheet stack over the first sacrificial nanosheet. A cavity is formed under the first nanosheet stack by removing at least a first portion of the first sacrificial nanosheet and leaving a second portion of the first sacrificial nanosheet. An isolation material is deposited within the cavity to form a first isolation region. A portion of the first nanosheet stack that is above the second portion of the first sacrificial nanosheet is removed to separate the first nanosheet stack into a second nanosheet stack and a third nanosheet stack. The second portion of the first sacrificial nanosheet is replaced with the isolation material to form a second isolation region. A bottom isolation region includes the first isolation region and the second isolation region.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Inventors: Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh
  • Publication number: 20200357885
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20200357886
    Abstract: Transistors having reduced parasitics and enhanced performance. In some embodiments, a transistor can include a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain. The transistor can further include a body configured to provide the conductive channel upon the application of the voltage to the gate. The body can be implemented as a second type active region that butts with the first type active region on the source side at a respective area not covered by the gate, and does not butt with the first type active region on the drain side at a respective area not covered by the gate.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 12, 2020
    Inventors: Yun SHI, Tzung-Yin LEE
  • Publication number: 20200357887
    Abstract: Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Ecrit semiconductors are presented. A dielectric layer is deposited on a high Ecrit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Ecrit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Ecrit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 12, 2020
    Inventors: Kelson D Chabak, Andrew J Green, Gregg H Jessen
  • Publication number: 20200357888
    Abstract: A nitride compound semiconductor having a low resistivity that is conventionally difficult to be manufactured is provided. Since the nitride compound semiconductor exhibits a high electron mobility, a high-performance semiconductor device may be configured. The present invention may provide, at a high productivity, a group 13 nitride semiconductor of an n-type conductivity that may be formed as a film on a substrate having a large area size and has a mobility of 70 to 140 cm2/(V·s) by a pulsed sputtering method performed in a process atmosphere at room temperature to 700° C.
    Type: Application
    Filed: June 1, 2018
    Publication date: November 12, 2020
    Inventors: Hiroshi FUJIOKA, Kohei UENO
  • Publication number: 20200357889
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Anthony K. Stamper, Steven M. Shank, Michel J. Abou-Khalil, Siva P. Adusumilli
  • Publication number: 20200357890
    Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventor: Arup Bhattacharyya
  • Publication number: 20200357891
    Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: United Microelectronics Corp.
    Inventor: Chin-Chin Tsai
  • Publication number: 20200357892
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Steven M. Shank, Anthony K. Stamper, Siva P. Adusumilli
  • Publication number: 20200357893
    Abstract: A semiconductor device is fabricated by a method including the following steps: a first step of forming a semiconductor film containing a metal oxide over an insulating layer; a second step of forming a conductive film over the semiconductor film; a third step of forming a first resist mask over the conductive film and etching the conductive film to form a first conductive layer and to expose a top surface of the semiconductor film that is not covered with the first conductive layer; and a fourth step of forming a second resist mask that covers a top surface and a side surface of the first conductive layer and part of the top surface of the semiconductor film and etching the semiconductor film to form a semiconductor layer and to expose a top surface of the insulating layer that is not covered with the semiconductor layer.
    Type: Application
    Filed: February 18, 2019
    Publication date: November 12, 2020
    Inventors: Yasutaka NAKAZAWA, Kenichi OKAZAKI, Takayuki OHIDE, Rai SATO
  • Publication number: 20200357894
    Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventors: Kangguo Cheng, Christopher J. Waskiewicz, Michael P. Belyansky, Brent Alan Anderson, Muthumanickam Sankarapandian, Puneet Suvarna, Hiroaki Niimi
  • Publication number: 20200357895
    Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Kangguo Cheng, Juntao LI, Heng Wu, Peng Xu
  • Publication number: 20200357896
    Abstract: A method for manufacturing a semiconductor device includes patterning a plurality of semiconductor fins on a semiconductor substrate, and replacing at least two of the plurality of semiconductor fins with a plurality of dummy fins including a dielectric material. A gate structure is formed on and around the plurality of semiconductor fins and the plurality of dummy fins, and a source/drain contact is formed adjacent the gate structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Kangguo Cheng, Ruilong Xie, Juntao Li, Chanro Park
  • Publication number: 20200357897
    Abstract: A semiconductor device is disclosed including, among other things, a first device region defined above a substrate, wherein the first device region is isolated from the substrate by a buried insulating layer, the first device region including a first power rail, a first signal line traversing at least a first portion of the first device region, and a first plurality of edge cells positioned in the substrate adjacent the first device region, wherein at least a first edge cell of the first plurality of edge cells includes a substrate contact connecting the first power rail to the substrate and a first signal line antenna diode connecting the first signal line to the substrate.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Stefan Block, Herbert Johannes Preuthen, Ulrich Hensel
  • Publication number: 20200357898
    Abstract: Vertical transport field effect transistors (VTFET) are disclosed along with methods of making. The VTFET is made with a novel gate last replacement metal gate (RMG) process. The invention allows uniform and high doping levels without adversely affecting the gate region in the process. The distance from the S/D regions and the junctions are the same. Fin caps protect the fins and gate protecting hard mask protect the dummy gate material during the beginning process steps. The invention enables easy connection and increased surface area at the connection points to reduce contact resistance.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Choonghyun Lee, Soon-Cheon Seo, Injo Ok, Alexander Reznicek
  • Publication number: 20200357899
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen LO, Li-Te LIN, Pinyen LIN
  • Publication number: 20200357900
    Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Wen-Cheng Lo, Sun-Jay Chang
  • Publication number: 20200357901
    Abstract: The present invention teaches a method of manufacturing a metal oxide thin film transistor (TFT) that includes the following steps: forming a shielding layer, a metal oxide semiconductor layer, a gate electrode, and a first photoresist pattern layer stacked on a substrate; forming a second photoresist layer on the metal oxide semiconductor layer and the first photoresist pattern layer; conducting ashing process to the second photoresist layer and the first photoresist pattern layer, and lifting the second photoresist layer and first photoresist pattern layer after they are ashing-processed; forming a first insulation layer on the metal oxide semiconductor layer and the gate electrode; and forming independent source electrode and drain electrode on the first insulation layer. The present invention deposits the second photoresist layer on the first photoresist pattern layer hardened by the conductorization process, so that they may be easily lifted after the ashing process.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 12, 2020
    Inventors: Qinzun LIN, Guihua HUANG
  • Publication number: 20200357902
    Abstract: A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: STMicroelectronics SA
    Inventors: Philippe GALY, Louise DE CONTI
  • Publication number: 20200357903
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate having a transistor section and a diode section, wherein both the transistor section and the diode section each have a drift region of a first conductivity-type provided inside the semiconductor substrate, and a base region of a second conductivity-type provided above the drift region inside the semiconductor substrate, inside the semiconductor substrate, a lifetime control region including lifetime killers is provided below the base region from at least a part of the transistor section to the diode section, and in the transistor section, a threshold value adjusting section for adjusting a threshold value of the transistor section is provided overlapping the lifetime control region as seen from an upper surface of the semiconductor substrate.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Inventor: Motoyoshi KUBOUCHI
  • Publication number: 20200357904
    Abstract: Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.
    Type: Application
    Filed: July 28, 2020
    Publication date: November 12, 2020
    Inventors: Daisuke OZAKI, Akinori KANETAKE, Tohru SHIRAKAWA, Yosuke SAKURAI
  • Publication number: 20200357905
    Abstract: An improved semiconductor structure includes a substrate, a buffer layer disposed on a top surface of the substrate, a channel layer disposed on a top surface of the buffer layer, a barrier layer disposed on a top surface of the channel layer, an etch-stop layer disposed on a top surface area of the barrier layer, a cap-layer disposed on a top surface area of the etch-stop layer, a source contact disposed on a first area of the barrier layer, a drain contact disposed on a second area of the barrier layer, a gate contact disposed on the cap layer between the source contact and the drain contact, and a dielectric layer disposed on areas of the etch-stop layer between the source contact and the gate contact and between the drain contact and the gate contact, respectively. The etch-stop layer is disposed on an area of the top surface of the barrier layer between the first area and the second area.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 12, 2020
    Applicant: Cambridge Electronics Inc.
    Inventor: BIN LU
  • Publication number: 20200357906
    Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
  • Publication number: 20200357907
    Abstract: We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
  • Publication number: 20200357908
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a channel layer and an active layer over a substrate; forming a doped epitaxial layer over the active layer; patterning the doped epitaxial layer, the active layer, and the channel layer to form a fin structure comprising a doped epitaxial fin portion, an active fin portion below the doped epitaxial fin portion, and a channel fin portion below the active fin portion; removing the doped epitaxial fin portion; and forming a gate electrode at least partially extending along a sidewall of the fin structure to form a Schottky barrier between the gate electrode and the fin structure after removing the doped epitaxial fin portion.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chao-Hsin WU, Li-Cheng CHANG, Cheng-Jia DAI, Shun-Cheng YANG
  • Publication number: 20200357909
    Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on th
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
  • Publication number: 20200357910
    Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Yu-Syuan LIN, Jiun-Lei YU, Ming-Cheng LIN, Chun Lin TSAI
  • Publication number: 20200357911
    Abstract: Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
  • Publication number: 20200357912
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a semiconductor substrate and forming a dielectric layer over the semiconductor substrate to surround the first gate stack and the second gate stack. The method also includes forming a protection element to cover the second gate stack. The method further includes replacing the first gate stack with a metal gate stack after the formation of the protection element.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen YANG, Tsung-Yu CHIANG
  • Publication number: 20200357913
    Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Xi-Zong Chen, Te-Chih Hsiung, Cha-Hsin Chao, Yi-Wei Chiu
  • Publication number: 20200357914
    Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Ching CHENG, Chih Chieh YEH, Cheng-Hsien WU, Hung-Li CHIANG, Jung-Piao CHIU, Tzu-Chiang CHEN, Tsung-Lin LEE, Yu-Lin YANG, I-Sheng CHEN
  • Publication number: 20200357915
    Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Yu-Lien HUANG, Meng-Chun CHANG
  • Publication number: 20200357916
    Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Sameer S. PRADHAN, Subhash M. JOSHI, Jin-Sung CHUN
  • Publication number: 20200357917
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.
    Type: Application
    Filed: May 6, 2019
    Publication date: November 12, 2020
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Andrew Christopher Graeme Wood
  • Publication number: 20200357918
    Abstract: A vertical-conduction MOSFET device, includes: a semiconductor body, having a front side and a back side and having a first conductivity; a trench-gate region; a body region, having the first conductivity; a source region, having a second conductivity; and a drain region, having the second conductivity. The source region, body region, and drain region are aligned with one another along a first direction and define a channel area, which, in a conduction state of the MOSFET device, hosts a conductive channel. The drain region borders on a portion of the semiconductor body having the first conductivity, thus forming a junction diode, which, in an inhibition state of the MOSFET device, is adapted to cause a leakage current to flow outside the channel area.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 12, 2020
    Inventors: Giuseppe CINA', Antonio Giuseppe GRIMALDI, Luigi ARCURI
  • Publication number: 20200357919
    Abstract: A power semiconductor device includes: a semiconductor layer including a main cell region, a sensor region, and an insulation region between the main cell region and the sensor region; a plurality of power semiconductor transistors disposed on the main cell region; a plurality of current sensor transistors disposed on the sensor region; and a protection resistance layer disposed on the semiconductor layer across the insulation region so that at least a portion of the plurality of power semiconductor transistors and at least a portion of the plurality of current sensor transistors are connected to each other under an abnormal operation condition.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 12, 2020
    Applicant: HYUNDAI AUTRON CO., LTD.
    Inventors: Ju-Hwan LEE, Tae-Young PARK, Seong-hwan YUN
  • Publication number: 20200357920
    Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.
    Type: Application
    Filed: March 24, 2020
    Publication date: November 12, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hyun SONG, Chang Woo SOHN, Young Chai JUNG, Sa Hwan HONG
  • Publication number: 20200357921
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok
  • Publication number: 20200357922
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20200357923
    Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a first conductor and a second conductor over the second oxide, a third oxide over the second oxide, a second insulator over the third oxide, a third conductor that is located over the second insulator and overlaps with the third oxide, a third insulator that is located over the first insulator and in contact with a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor, and a fourth insulator over the third conductor, the second insulator, the third oxide, and the third insulator. The fourth insulator is in contact with a top surface of each of the third conductor, the second insulator, and the third oxide.
    Type: Application
    Filed: November 27, 2018
    Publication date: November 12, 2020
    Inventors: Shunpei YAMAZAKI, Hiromi SAWAI, Ryo TOKUMARU, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Sho NAGAMATSU, Tomoaki MORIWAKA
  • Publication number: 20200357924
    Abstract: An oxide semiconductor thin film according to an embodiment of the present invention includes: an oxide semiconductor containing In, Zn, Ti, and Sn, an atomic ratio of (In+Sn)/(In+Zn+Ti+Sn) being not less than 0.36 and not more than 0.92, an atomic ratio of Sn/(In+Sn) being not less than 0.02 and not more than 0.46, an atomic ratio of Sn/(In+Zn+Ti+Sn) being not less than 0.01 and not more than 0.42, an atomic ratio of Ti/(In+Zn+Ti+Sn) being not less than 0.01 and not more than 0.10.
    Type: Application
    Filed: November 19, 2018
    Publication date: November 12, 2020
    Inventors: Fumito OOTAKE, Motoshi KOBAYASHI, Mitsuru UENO, Masaru WADA, Kouichi MATSUMOTO
  • Publication number: 20200357925
    Abstract: A minute transistor is provided. A semiconductor device includes a semiconductor over a substrate, a first conductor and a second conductor over the semiconductor, a first insulator over the first conductor and the second conductor, a second insulator over the semiconductor, a third insulator over the second insulator, and a third conductor over the third insulator. The third insulator is in contact with a side surface of the first insulator. The semiconductor includes a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between a top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.
    Type: Application
    Filed: June 18, 2020
    Publication date: November 12, 2020
    Inventors: Satoshi TORIUMI, Takashi HAMADA, Tetsunori MARUYAMA, Yuki IMOTO, Yuji ASANO, Ryunosuke HONDA, Shunpei YAMAZAKI
  • Publication number: 20200357926
    Abstract: A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.
    Type: Application
    Filed: February 18, 2019
    Publication date: November 12, 2020
    Inventors: Yuki HATA, Katsuaki TOCHIBAYASHI, Junpei SUGAO, Shunpei YAMAZAKI