Abstract: A semiconductor chip 10 is provided on a semiconductor circuit base 8 on one surface of an insulating substrate 4. A circuit base 26 is provided on the one surface of the insulating substrate 4 spaced to the semiconductor circuit base 8. The insulating substrate 4, the semiconductor circuit base 8, the semiconductor chip 10, and the reinforcement and balance base 26 are sealed into a resin-molded sealing body 2. The sealing body 2 has resin non-adhering portions 34.

Abstract: A semiconductor package includes a substrate formed of electrically insulating material and having a die mounting surface, a first semiconductor die embedded within the substrate and comprising a first conductive terminal that faces the die mounting surface, a second semiconductor die mounted on the die mounting surface and comprising a first conductive terminal that faces and is spaced apart from the die mounting surface, and a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together, wherein the second semiconductor die partially overlaps with the first semiconductor die.

Abstract: A substrate structure, a semiconductor package structure including the same and a method for manufacturing the same are provided. The substrate structure includes a first passivation layer, a first circuit layer and a first protection layer. The first passivation layer has a first surface and a second surface opposite to the first surface. The first circuit layer has an outer lateral surface. A first portion of the first circuit layer is disposed in the first passivation layer. The first protection layer is disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer. The outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer.

Abstract: A semiconductor device includes a device cell including a gate component configured to receive a gate control signal and a temperature sensing component adjacent to the device cell. Each of the temperature sensing component and the gate component includes polycrystalline silicon.

Abstract: A semiconductor component having at least one semiconductor component having a first electrical connector and at least one further electrical connector, a printed circuit board, and a prefabricated metal block group. The metal block group has a first metal block arranged between the semiconductor component and the printed circuit board, connected to a first electrical connector of the semiconductor component by a solder joint and connected to at least one conductor track of the printed circuit board by a further solder joint. The metal block group includes at least one further metal block interposed between the further electrical connection and the printed circuit board by a solder joint. The metal blocks of the prefabricated metal block group are arranged laterally next to one another and have their lateral outer surfaces partially or completely encased by an electrically insulating casing common to them.

Abstract: An insulating substrate provided between the semiconductor chip and a cooler in the dual-side cooled power module includes: an inner metal layer configured to face the semiconductor chip; an outer metal layer configured to face the cooler; and an insulating layer interposed between the inner metal layer and the outer metal layer, wherein at least one inner thermal diffusion inductor of a plurality of inner thermal diffusion inductors is inserted into the inner metal layer.

Abstract: Semiconductor chips may include a substrate; a protective layer on a first surface of the substrate, through electrodes extending through the substrate and the protective layer, and a Peltier structure including first through structures including first conductivity type impurities, and second through structures including second conductivity type impurities, which may extend through the substrate and the protective layer; pads on the protective layer and connected to the through electrodes, respectively, first connection wires connecting respective first ends of the first through structures to respective first ends of the second through structures, and second connection wires connecting respective second ends of the first through structures to respective second ends of one of the second through structures. The first through structures and the second through structures may be alternately connected to each other in series by the first connection wires and the second connection wires.

Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

Abstract: A conductive structure includes: a conductive pillar and at least one embedded block arranged in the conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. When the conductive pillar is heated and expanded, an extrusion effect of the conductive pillar on a structure adjacent to the conductive pillar can be reduced, thereby improving the performance of the semiconductor structure.

Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

Abstract: A semiconductor device includes a die body having a frontside and a transistor having an active area formed in the die body, the active area being bounded by an outer periphery. An interconnect structure is formed over the frontside of the die body and contains patterned electrically conductive material defining first, second, and third contacts electrically coupled to first, second, and third subregions, respectively, within the active area of the transistor. A frontside input/output (I/O) interface is formed in an outer portion of the interconnect structure. The frontside I/O interface contains first, second, and third contact pads, the first contact pad being electrically connected to the first contact, the second contact pad being electrically connected to the second contact, and the third contact pad being electrically connected the third contact, wherein the third contact pad is positioned at a location overlying the active area of the transistor.

Abstract: An amplifier module includes a module substrate and first and second power transistor dies. The first power transistor die is coupled to a mounting surface of the module substrate, and has first and second input/output (I/O) contact pads and a first ground contact pad, all of which are all exposed at a surface of the first power transistor die that faces toward the mounting surface of the module substrate. The second power transistor die also is coupled to the mounting surface, and has third and fourth I/O contact pads and a second ground contact pad. The third and fourth I/O contact pads are exposed at a surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a surface of the second power transistor die that faces toward the mounting surface.

Abstract: A manufacturing method for a chip packaging structure, comprising: arranging a metal heat dissipation layer on a substrate comprising at least one flange on its side surface; forming a sealing pin located on an upper surface of the flange, so that the metal heat dissipation layer, the flange and the sealing pin form a cavity for accommodating an encapsulant; attaching a chip structure on an upper surface of the metal heat dissipation layer using an adhesive layer; forming the encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer and the chip structure, the sealing pin extends to a periphery of the upper surface of the encapsulant; performing a mechanical or chemical treatment, to make electrode connecting structures on an upper layer of the chip structure exposed outside the first encapsulant; arranging a pin layer for electrically coupling to and covering the electrode connection structures.

Abstract: The semiconductor device includes: a heat spreader; a semiconductor element joined to the heat spreader via a first joining member; a first lead frame joined to the heat spreader via a second joining member; a second lead frame joined to the semiconductor element via a third joining member; and a mold resin. In a cross-sectional shape obtained by cutting at a plane perpendicular to a one-side surface of the heat spreader, an angle on the third joining member side out of two angles formed by a one-side surface of the semiconductor element and a straight line connecting an end point of a joining surface between the third joining member and the semiconductor element and an end point of a joining surface between the third joining member and the second lead frame, is not smaller than 90° and not larger than 135°.

Abstract: In one example, an electronic device comprises a first substrate comprising a base, an electronic component over the first substrate and comprising a top side and a bottom side, a first terminal and a second terminal on the top side, and a third terminal on the bottom side, wherein the third terminal is coupled with the first substrate. The electronic device further comprises a second substrate over the electronic component, and an encapsulant over the first substrate, contacting a lateral side of the electronic component and contacting the second substrate. A first lead is coupled with and extends over the base of the first substrate, a second lead of the second substrate is coupled to the first terminal of the electronic component, and the first lead and the second lead are exposed from a top side of the encapsulant. Other examples and related methods are also disclosed herein.

Abstract: A semiconductor device includes: first and second semiconductor elements each having two electrodes respectively disposed on two surfaces; two first terminals respectively connected to the two electrodes of the first semiconductor element and arranged side by side in one direction; two second terminals respectively connected to the two electrodes of the second semiconductor element, and arranged side by side in the one direction to be adjacent to the two first terminals; and a sealing resin portion covering the first and second semiconductor elements and the first and second terminals in a state where facing surfaces of the first and second terminals are exposed from the sealing resin portion. The facing surfaces of the two first terminals have different area ratios, the facing surfaces of the two second terminals have different area ratios, and one of the first terminals is arranged adjacent to both the two second terminals.

Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.

Abstract: In one example, an electronic device comprises a substrate comprising a first side and a second side, a first a lead on the second side, and a cavity in the second side adjacent to the first lead, an electronic component in the cavity and comprising a first terminal, a second terminal, and a third terminal, and a device encapsulant in the cavity and contacting a lateral side of the electronic component, and contacting a lateral side of the first lead opposite to the cavity. Other examples and related methods are also disclosed herein.

Abstract: Methods, apparatuses and systems provide for technology that includes a transistor assembly for a power electronics apparatus having a plurality of transistor pairs arranged in a common plane, where for each pair of transistors one transistor is flipped relative to the other transistor. The technology further includes a first lead frame arranged parallel to and electrically coupled to the first transistor in each transistor pair, a second lead frame coplanar to the first lead frame and arranged parallel to and electrically coupled to the second transistor in each transistor pair, and a plurality of output lead frames arranged coplanar to each other, where each respective output lead frame is arranged parallel to and electrically coupled to a respective one pair of the plurality of transistor pairs.

Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.

Abstract: A semiconductor device includes a semiconductor element, a lead frame, a bridge member, and a sealing resin. The semiconductor element has first and second surfaces opposite from each other, and has first and second electrodes respectively exposed on the first and second surfaces. The lead frame includes a mounting portion and a non-mounting portion divided from the mounting portion. The mounting portion has a mounting surface to which the semiconductor element is mounted and the first electrode is electrically connected, and an opposite surface opposite from the mounting surface. The bridge member electrically connects the second electrode and the non-mounting portion. The sealing resin has electric insulation, has a thermal conductivity of 2.2 W or more, and covers the semiconductor element, the lead frame, and the bridge member in a state where the opposite surface of the mounting portion is exposed from the sealing resin.

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

Abstract: A disclosed apparatus may include (1) an integrated circuit electrically coupled to a substrate, (2) a plurality of electrical contacts that are disposed on the substrate and are electrically coupled to the integrated circuit via the substrate, (3) at least one cable assembly electrically coupled to the plurality of electrical contacts, and (4) a package stiffener physically coupled to the substrate around the integrated circuit such that the at least one cable assembly is accessible to at least one electrical cable. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An electronic package and method for manufacturing the same are provided. The electronic package includes a substrate and a wetting layer. The substrate includes a plurality of conductive step structures each including a first portion and a second portion. The first portion has a first bottom surface, a first outer surface and a first inner surface. The second portion has a second bottom surface, a second outer surface and a second inner surface, wherein the second portion partially exposes the first bottom surface. The wetting layer at least covers the second bottom surface, the second outer surface and the second inner surface of the second portion of each of the conductive step structures.

Abstract: A chip card body including a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region to accommodate a chip with an antenna, wherein the coupling region is configured to inductively couple the metal plate to the antenna of the chip, a dielectric layer applied to the metal plate, an electrically conductive layer applied to a side of the dielectric layer opposite the metal plate, and at least one electrically conductive coupling between the metal plate and the electrically conductive layer, wherein the metal plate, the dielectric layer and the electrically conductive layer form a capacitor.

Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

Abstract: An apparatus includes a plurality of layers arranged on top of one another and including at least one ground layer and a signal layer; a first set of signal pads and a second set of signal pads on the signal layer; and a slot formed in the at least one ground layer between the first set of signal pads and the second set of signal pads. The apparatus can include an optical assembly housed by the plurality of layers and connected to the first set of signal pads and the second set of signal pads. The optical assembly can include a micro Intradyne Coherent Receiver (?ICR), a Coherent Driver Modulator (CDM), or a Coherent Optical Subassembly (COSA).

Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

Abstract: A reticle-stitched integrated circuit is provided. The reticle-stitched integrated circuit extends over a first die area and a second die area of an integrated circuit wafer. While individually the first die area and the second die area are within their respective reticle limits, collectively the first die area and the second die area exceed the reticle limit. A first layer of the reticle-stitched integrated circuit may have communication wires that remain exclusively in only one of the first die area and the second die area. A second layer of the reticle-stitched integrated circuit may have communication wires that overlap the first die area and the second die area, thereby allowing communication between the two die areas and enabling the reticle-stitched integrated circuit to exceed the limit of the reticle.

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

Abstract: A channel structure for signal transmission is provided. The channel structure includes a first common pad, disposed on a first layer; a second common pad, disposed on a second layer; a via, for electrically connecting the first common pad and the second common pad; a first device path pad, disposed on the second layer and located in a first direction of the second common pad; and a second device path pad disposed on the second layer and located in a second direction of the second common pad. The channel structure includes a first electrical element electrically coupled between the second common pad and the first device path pad, or includes a second electrical element electrically coupled between the second common pad and the second device path pad.

Abstract: Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating overheating and potential damage to the semiconductor device. The masking layer is resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

Abstract: A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.

Abstract: The present application discloses a fuse structure and a formation method. The fuse structure includes: a first dielectric layer, and at least two discrete first conductive plugs penetrating the first dielectric layer; a second conductive plug, the second conductive plug being electrically connected to the at least two first conductive plugs; a top metal layer, the top metal layer being electrically connected to the second conductive plug, and located on one side of the second conductive plug which is far from the first conductive plugs; and a second dielectric layer, the second dielectric layer being located on the top of the first dielectric layer, and the second conductive plug and the top metal layer being located in the second dielectric layer. The embodiments of the present application simplify the fuse structure, increasing the output efficiency of the fuse structure.

Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes an intermediate region and array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region. In the intermediate region, wall-structure regions of the first block and the second block are separated by a staircase structure. The memory device further includes a beam structure, located in the intermediate region and including at least a plurality of discrete first beam structures, each extending along the second lateral direction and connecting the wall-structure regions of the first block and the second block; and a plurality of second dielectric layers, located in the beam structure. In the first beam structures, the second dielectric layers is alternated with the first dielectric layers.

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

Abstract: An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.

Abstract: An integrated circuit module, system and method of providing power and signals is disclosed that includes a silicon chip and a package substrate having voltage connections and signal connections. The silicon chip includes a silicon substrate having a top surface, a bottom surface and circuitry formed therein, one or more front-side metal layers formed on the top surface of the silicon substrate, one or more back-side metal layers formed on the bottom surface of the silicon substrate, and one or more through silicon vias (TSVs) formed through the silicon substrate for creating a conductive pathway from the back-side of the silicon substrate to the front-side of the silicon substrate, preferably closest to the silicon substrate.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

Abstract: An electronic system in package, including at least: a support; one or more chips mechanically and electrically coupled to a front face of the support; an encapsulation material covering the front face of the support and encapsulating the chip(s); several side protection elements, comprising an opaque material and laterally surrounding the chip(s) and configured to form a barrier at least against laser attacks made through side faces of the electronic system in package that are substantially perpendicular to the front face of the support; and wherein the side protection elements are disposed in the encapsulation material or in one or more first blocks of material distinct from the support and disposed in the encapsulation material.

Abstract: A packaged radio-frequency device is disclosed, including a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. A shielded package may be implemented on the first side of the packaging substrate, the shielded package including a first circuit and a first overmold structure, the shielded package configured to provide radio-frequency shielding for at least a portion of the first circuit. A set of through-mold connections may be implemented on the second side of the packaging substrate, the set of through-mold connections defining a mounting volume on the second side of the packaging substrate. The device may include a component implemented within the mounting volume and a second overmold structure substantially encapsulating one or more of the component or the set of through-mold connections.

Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.

Abstract: A semiconductor package includes an upper conductive pattern and a redistribution layer on a first surface of a substrate, a semiconductor chip facing the first surface of the substrate, the semiconductor chip being spaced apart from the first surface of the substrate, a conductive bump bonding between the semiconductor chip and the upper conductive pattern, the conductive bump electrically connecting the semiconductor chip and the upper conductive pattern, and an upper passivation layer on the redistribution layer, a portion of the upper passivation layer facing an edge of a lower surface of the semiconductor chip.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.