Abstract: A method of fabricating a semiconductor device includes: epitaxially growing a multilayer Group-III nitride structure on a first surface of a substrate; removing portions of the multilayer structure to form a mesa arranged on the first surface; applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material; forming an electrode on a top surface of the mesa; forming a via in the insulating material that extends from the top surface of the insulating material to the first surface of the substrate; inserting conductive material into the via to form a conductive via; applying an electrically conductive redistribution structure to the upper surface and electrically connecting the conductive via to the electrode; and successively removing portions of a second surface of the substrate, to expose the insulating material and form a worked second surface including the insulating material.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a third nitride region. The first nitride region includes Alx1Ga1-x1N (0?x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second nitride region includes Alx2Ga1-x2N (x1<x2?1) or InyAlzGa(1-y-z)N (0<y?1, 0?z<1, y+z?1). The second nitride region includes a sixth partial region. The third nitride region includes Alx3Ga1-x3N (x1<x3<x2). The third nitride region includes a seventh partial region.

Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a semiconductor layer provided between the first electrode and the second electrode, having a first face and a second face, and containing silicon; a first semiconductor region of n-type; a second semiconductor region of p-type disposed the first semiconductor region and the first face; a third semiconductor region of n-type between the second semiconductor region and the first face; a gate electrode facing the second semiconductor region; and a metal silicide layer between the first electrode and the second semiconductor region and between the first electrode and the third semiconductor region, including a top surface, a first bottom surface in contact with the third semiconductor region, and containing gold or a platinum group element. The n-type impurity concentration in the third semiconductor region monotonically decreases from the first bottom surface toward the second electrode.

Abstract: A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a first and a second electrodes, a first gate electrode, a first and a second field plates. The first field plate is disposed over the second nitride-based semiconductor layer and extends from a region between the first electrode and the first gate electrode to a region directly over the first gate electrode. The second field plate is disposed over the second nitride-based semiconductor layer and extends from a region between the first electrode and the first field plate to a region directly over the first field plate. The second field plate is horizontally spaced away from the first gate electrode.

Abstract: The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.

Abstract: A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate having a source/drain feature and a gate structure formed thereon; forming an interlayer dielectric layer on the semiconductor substrate; patterning the interlayer dielectric layer to form a trench to expose the source/drain feature within the trench; forming a dielectric liner on sidewalls of the trench; filling a metal layer in the trench; recessing a portion of the metal layer in the trench, thereby forming a recess in the metal layer; and refilling a dielectric material layer in the recess.

Abstract: A semiconductor device includes a first vertically-oriented semiconductor pillar having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width, a first dielectric material abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar, and a first conductive structure having a first surface, and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in electrical contact with the top surface of the first vertically-oriented semiconductor pillar, wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the second portion of the first surface is disposed on the first dielectric material.

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in a first region, and the first source/drain epitaxial feature is asymmetric with respect to a fin. The structure further includes a second source/drain epitaxial feature disposed in the first region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, and a conductive feature disposed over the first and second source/drain epitaxial features and the first dielectric feature.

Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

Abstract: A non-volatile memory device may include a substrate, a first floating gate, a second floating gate, a third floating gate and a fourth floating gate. The substrate may include an active region. The first to fourth floating gates may be formed on the substrate. The first to fourth floating gates may be radially arranged to be partially overlapped with the active region. The first floating gate and the third floating gate may face each other in a first direction. The first floating gate and the third floating gate may have asymmetrically planar shapes. The first floating gate and the second floating gate may face each other in a second direction substantially perpendicular to the first direction. The first floating gate and the second floating gate may have asymmetrically planar shapes. The third floating gate and the fourth floating gate may face each other in the second direction. The third floating gate and the fourth floating gate may have asymmetrically planar shapes.

Abstract: The application discloses a super flash including: a first gate trench formed at the top of a source region, wherein a floating gate and a control gate are formed in the first gate trench. A second nitrogen oxide layer and a first oxide layer are formed between a first side surface of the floating gate and side and bottom surfaces of the first gate trench. A third nitrogen oxide layer and a fourth oxide layer are formed between a second side surface of the floating gate and a side surface of the control gate. The floating gate is a TiN layer; and the top of the floating gate is higher than a top surface of the control gate. The second nitrogen oxide layer and the third nitrogen oxide layer prevent the diffusion of oxygen into the floating gate. The present application also discloses a method for manufacturing a super flash.

Abstract: A semiconductor structure includes a peripheral region and an array region. A substrate is provided. An active layer is provided in the substrate corresponding to the peripheral region. A word line groove is formed in the substrate corresponding to the array region. A word line is formed in the word line groove. The word line includes a first word line conductive layer and a second word line conductive layer with one stacked on another. A top of the first word line conductive layer is a protrusion. The protrusion protrudes along a direction pointing from the first word line conductive layer to the second word line conductive layer. An isolation layer covering the substrate is formed. A first through hole and a second through hole both penetrating through the isolation layer are formed simultaneously. The first through hole exposes the active layer. The second through hole exposes the protrusion.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first silicon-germanium film which is conformally formed inside a surface of the substrate of the first region and defines a first gate trench, a first gate insulating film which extends on the first silicon-germanium film along a profile of the first gate trench and is in physical contact with the first silicon-germanium film, a first metallic gate electrode on the first gate insulating film, a source/drain region formed inside the substrate on both sides of the first metallic gate electrode, a second gate insulating film in the second region and a second metallic gate electrode on the second gate insulating film.

Abstract: A thin film transistor, a manufacturing method thereof, and a display panel are provided. The thin film transistor includes a semiconductor layer, a gate disposed corresponding to a position of the semiconductor layer, and a gate insulating layer disposed between the semiconductor layer and the gate. The gate insulating layer includes a first gate insulating layer and a second gate insulating layer. A dielectric constant of the first gate insulating layer is greater than a dielectric constant of the second gate insulating layer.

Abstract: Apparatus and methods for multi-gate radio frequency (RF) switches are disclosed herein. The RF switches use various layout design techniques to improve figure of merit (FOM). Examples of such techniques include using only two field-effect transistors (FETs) in series to maintain shorter fingers for lower metal resistance, placing a body contact on only one side of the RF switch layout, implementing metallization with reduced coupling from input to output, and/or providing air gaps to improve high frequency performance.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a nanostructure stack over the substrate. The method includes forming a gate stack over the nanostructure stack and the substrate. The method includes removing the first nanostructure forming a first gap between the substrate and the second nanostructure. The method includes forming a first spacer layer in the first gap and a gate spacer over a sidewall of the gate stack. The method includes partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack. The method includes forming a source/drain structure in the first trench and over the first spacer layer.

Abstract: A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolation pillar structure located between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. The upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.

Abstract: A semiconductor element includes an element having a gate electrode provided in a semiconductor substrate. The semiconductor substrate has an emitter electrode arranged on an upper surface and a collector electrode arranged on a lower surface. A gate pad is arranged at a different position from the emitter electrode on the upper surface. A gate resistor arranged on the upper surface has an adjustable resistance value, and is connected between the gate electrode and the gate pad.

Abstract: A Normally-off MESFET device comprising a semiconductor layer, a source contact, a drain contact and a stacked gate contact, wherein the stacked gate contact comprises a bottom metal layer, a top metal layer and an insulating layer between the bottom and top metal layers, wherein the source, drain and stacked gate contacts are in contact with the semiconductor layer, wherein the bottom metal layer and the semiconductor layer form a Schottky contact, creating a depletion region in the semiconductor layer below the bottom metal layer, and wherein the extension of the depletion region into the semiconductor layer is configured to be modulated by application of a voltage to the top metal layer.

Abstract: A solution-phase processed vertical Schottky diode comprises a stack of films on a substrate, where the stack of films includes: a first electrode film comprising a noble metal; a first semiconducting film on the first electrode film, where the first semiconducting film comprises zinc oxide doped with an electron donor metal at a first dopant concentration; a second semiconducting film on the first semiconducting film, where the second semiconducting film comprises zinc oxide doped with the electron donor metal at a second dopant concentration higher than the first dopant concentration; and a second electrode film on the second semiconducting film, where the second electrode film comprises a noble metal.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a hole injection buffer layer (HIBL) on the p-type semiconductor layer, and forming a gate electrode on the HIBL.

Abstract: Gate profile tuning techniques are disclosed herein. An exemplary gate profile tuning method includes forming a gate structure over a channel layer. The gate structure includes a dummy gate and gate spacers disposed along sidewalls of the dummy gate. The method further includes partially removing the dummy gate to form a gate opening that defines a gate profile. The gate profile is then modified by treating portions of the gate spacers (for example, by oxygen plasma treatment) and removing the treated portions of the gate spacers (for example, by oxide removal). After removing a remainder of the dummy gate to expose the channel layer, a gate stack of the gate structure is formed in the gate opening. The gate stack has a funnel-shaped profile. In some embodiments, a width of the gate stack above the channel layer is greater than a width of the gate stack below the channel layer.

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

Abstract: A semiconductor device including a structure having N gate electrode layers G and (N?1) channel formation region layers CH (where N?3) alternately juxtaposed on an insulating material layer of a base having the insulating material layer formed on a surface of a conductive substrate. Each of the structure, the channel formation region layer CH, and the gate electrode layer G has a bottom surface, a top surface, and four side surfaces. A second surface of the nth channel formation region layer is connected to a fourth surface of the nth gate electrode layer. A fourth surface of the nth channel formation region layer is connected to a second surface of the (n+1)th gate electrode layer. One of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion.

Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.

Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate and p-type body regions are disposed at a top of the semiconductor substrate. The p-type body regions are in contact with an emitter metal layer. The semiconductor substrate includes at least one first region, and a region of the semiconductor substrate outside the at least one first region is a second region. Each of p-type body regions in the at least one first region is provided with a first p-type body region contact region, and the emitter metal layer is in contact with the first p-type body region contact region and forms an ohmic contact with the first p-type body region contact region. Each of p-type body regions in the second region forms no ohmic contact with the emitter metal layer.

Abstract: Provided is a reverse-conducting IGBT chip including a first conductive type substrate; and several first conductive type short circuit regions arranged at intervals below the substrate and adjacent to a collector region. The short circuit regions are located outside a first preset range having the center of a chip as a center, in a second preset range outside the first preset range and having the center of the chip as a center, in a third preset range outside the second preset range and having the center of the chip as a center, and in a range outside the third preset range and enclosed by a chip edge.

Abstract: A power semiconductor device and method of manufacture thereof involving drift layer of a first conductivity type; base layer of a second conductivity type different than the first conductivity type; source region with first conductivity type arranged on a side of the base layer facing away from the drift layer; a first trench extending from the emitter side into the drift layer; an insulated trench gate electrode extending into the first trench; a second trench being arranged on a side of a first trench facing away from the source region; an electrically conductive layer extending into the second trench and electrically insulated from the base layer and the drift layer. A portion of the base layer extends from the emitter side at least as deep in the vertical direction towards the collector side as the at least one second trench.

Abstract: A bidirectional thyristor device (1) comprising a semiconductor body (2) extending between a first main surface (21) and a second main surface (22), is provided wherein a first main electrode (31) and a first gate electrode (41) are arranged on the first main surface and a second main electrode (32) and a second gate electrode (42) are arranged on the second main surface. The first main electrode comprises a plurality of first segments (310) that are spaced apart from one another, wherein at least some of the first segments are completely surrounded by the first gate electrode in a view onto the first main surface. The second main electrode comprises a plurality of second segments (320) that are spaced apart from one another, wherein at least some of the second segments are completely surrounded by the second gate electrode in a view onto the second main surface.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first source/drain (S/D) electrode, a second S/D electrode, a first gate electrode, a second gate electrode, a first passivation layer, a conductive layer, and a second passivation layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second S/D electrodes and the first and second gate electrodes are disposed above the second nitride-based semiconductor layer. The first passivation layer covers the first and second gate electrodes. The conductive layer is disposed over the first passivation layer and includes an electrode portion and a field plate portion. The second passivation layer is disposed on the conductive layer and penetrates the conductive layer to make contact with the first passivation layer.

Abstract: A nitride semiconductor device 1 includes an SiC substrate 2 of a hexagonal crystal system that has a first main surface 2a and a second main surface 2b at an opposite side thereof and a nitride epitaxial layer 20 that is formed on the first main surface 2a and the first main surface 2a has an off angle of greater than 1° with respect to a c-plane of the hexagonal crystal.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a single III-V group semiconductor layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The single III-V group semiconductor layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The single III-V group semiconductor layer has a high resistivity region and a current aperture enclosed by the high resistivity region, in which the high resistivity region comprises more metal oxides than the current aperture so as to achieve a resistivity higher than that of the current aperture. The third nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first gate electrode, a first S/D electrode, and a first field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion that is non-semi-conducting and surrounds the active portion to form at least two interfaces extending along a first direction and spaced apart from each other by the active portion. The first gate electrode and the first S/D electrode are disposed above the second nitride-based semiconductor layer. The first field plate is disposed above the second nitride-based semiconductor layer and extends along the second direction and across the two interfaces such that the field plate extends to the electrically isolating portion, and overlaps with the first gate electrode near the interfaces.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a gate electrode, and a doped nitride-based semiconductor layer. The doped nitride-based semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The doped nitride-based semiconductor layer has a pair of opposite ledge portions free from coverage of the gate electrode and a central portion therebetween. The second nitride-based semiconductor layer has a first portion beneath the central portion and a second portion beneath the ledge portion, and the second nitride-based semiconductor layer has a doping concentration of a dopant that selected from a highly electronegative group, in which the doping concentration from the first portion to the second portion increases.

Abstract: A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.

Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: A semiconductor device includes a transistor disposed in an active region. The transistor comprises a source/drain feature, a fin channel and a gate structure wrapping over the fin channel. The transistor also includes an insulation region disposed at an active edge. The active edge is at a boundary of the active region. The insulation region includes a trench. The trench has a tapered portion. A width of the tapered portion of the trench at a top of the fin channel is greater than a width of the tapered portion of the trench at a bottom of the gate structure.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a bottom electrode layer over a substrate and forming a gate dielectric layer over the bottom electrode layer. The method for manufacturing the semiconductor structure also includes forming an active layer over the gate dielectric layer and forming an indium-containing feature vertically overlapping the bottom electrode layer. The method for manufacturing the semiconductor structure also includes forming a source/drain contact landing on the indium-containing feature.

Abstract: An interconnect structure is disposed over a semiconductor substrate. The interconnect structure includes a plurality of interconnect layers. A first thin-film transistor (TFT) and a second TFT disposed over the semiconductor substrate. The first TFT and the second TFT each vertically extend through at least a subset of the interconnect layers. An opening is formed in the interconnect structure. The opening is disposed between the first TFT and the second TFT. A sensing film is disposed over a bottom surface and side surfaces of the opening.

Abstract: A semiconductor device and an electronic device are provided. The semiconductor device includes an insulating substrate, and a non-planar layer disposed on the insulating substrate and including a non-planar structure. The non-planar structure includes a sidewall. An active pattern is configured with at least a part located on the sidewall of the non-planar structure. The active pattern includes a channel located on the sidewall. A ratio of a size of the non-planar structure in a thickness direction of the non-planar layer to a thickness of the active pattern is less than or equal to seven.

Abstract: Disclosed is a thin film transistor including: a gate electrode disposed on a substrate; a semiconductor layer overlapping the gate electrode with a gate insulating film interposed therebetween, and a source region and a drain region which are in contact with the semiconductor layer, in which the semiconductor layer includes a crystallized oxide semiconductor, and the crystallized oxide semiconductor includes a crystal having an X-ray diffraction (XRD) main peak Miller index (hkl) value of (009).

Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.