Abstract: Disclosed is a color filter according to an example embodiment, an image sensor, and an electronic apparatus having the image sensor. The color filter includes a first dielectric layer, a second dielectric layer on the first dielectric layer, and a plurality of metal elements buried in both of the first dielectric layer and the second dielectric layer in lateral contact with each of the first dielectric layer and the second dielectric layer.

Abstract: Provided is a solid-state imaging device capable of acquiring an image with higher image quality. It includes: a substrate; a plurality of photoelectric conversion units in a two-dimensional matrix on the substrate; a lattice-shaped pixel separation unit on the substrate and surrounding the respective photoelectric conversion units; and a lattice-shaped light-shielding film on a side of a light-incident surface of the substrate that includes a plurality of openings that opens the respective plurality of photoelectric conversion units on the light-incident surface side. The light-shielding film has an overhang that overhangs inward of the respective openings at a corner between two mutually intersecting sides of a lattice of the light-shielding film. Each of light-incident surfaces of a plurality of intersections where sides of a lattice of the pixel separation unit intersect one another overlaps with at least one of the lattice of the light-shielding film or the overhang in plan view.

Abstract: An image sensor may include a sensor chip that is bonded to an application-specific integrated circuit (ASIC) chip. A bond pad for the image sensor may be formed in the ASIC chip and exposed through a trench in the sensor chip. The image sensor may include a conductive light shield at a periphery of the image sensor to shield optically black pixels. An opaque layer may be formed over the conductive light shield to mitigate reflections off the conductive light shield. An anti-reflective layer may be formed over the pixel array. The anti-reflective layer may have a different thickness over the pixel array than in the trench for the bond pad.

Abstract: Crosstalk is suppressed in a wiring layer.

Abstract: Provided are an imaging apparatus and a manufacturing method for an imaging apparatus that are advantageous for acquiring a captured image in which an influence of a rays is suppressed. An imaging apparatus includes: a sensor substrate having a photoelectric conversion element on which image-capturing light is incident; a cover substrate that covers the photoelectric conversion element and transmits the image-capturing light; and an ?-ray transmission preventive film that transmits the image-capturing light.

Abstract: A process for fabricating a light detector with one or more antireflection (AR) and/or bandpass filter coatings deposited thereon by area-selective atomic layer deposition (ALD). The AR coatings may comprise a metal oxide or a metal fluoride, such as AlF3, Al2O3, and/or HfO2, and the bandpass filter coatings may comprise solar-blind bandpass filter coatings. The AR and/or bandpass filter coatings may be deposited with different thicknesses on different portions of the light detector using an intentional and controllable patterning by a lithography-based process. As a result, the AR and/or bandpass filter coatings provide a butcher-block style response profile with each of the different portions of the light detector targeting a specific bandpass of light. The AR and/or bandpass filter coatings comprise a linear variable filter (LVF) that provides a spatially varying response by the light detector.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an H-like shape. The image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. The second isolation structure surrounds a second portion of the light-sensing region.

Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, a light transmitting member, and a plurality of pillar members disposed between and contacting the image sensor die and the light transmitting member. A height of the plurality of pillar members defines a gap height between an active region of the image sensor die and the light transmitting member. The image sensor package including a bonding material that couples the light transmitting member to the image sensor. The bonding material contacts a side of a pillar member, of the plurality of pillar members, that extends between a first end contacting the light transmitting member and a second end contacting the image sensor die.

Abstract: A pixel structure and an image sensor are provided. The pixel structure includes: a plurality of pixel units adjacent to each other and are arranged in an array. A first optical partition wall is arranged between the adjacent pixel units. The pixel structure further includes a microlens assembly. The microlens assembly is located on an upper side of all the pixel units and is opposite to all the pixel units. Each of the pixel units includes a color filter, a pixel microlens, and a photoelectric conversion layer arranged successively from top to bottom. Colors of color filters of the adjacent pixel units are different.

Abstract: Provided is a solid-state imaging device capable of forming a pixel separation groove having a suitable action in a substrate. A solid-state imaging device of the present disclosure includes: a first photoelectric conversion unit and a second photoelectric conversion unit that are provided in a first semiconductor substrate and are adjacent to each other; a first pixel separation groove provided between the first photoelectric conversion unit and the second photoelectric conversion unit not to penetrate through the first semiconductor substrate; and a second pixel separation groove provided to penetrate through the first semiconductor substrate.

Abstract: A solid-state imaging device as disclosed includes: a semiconductor substrate; a floating diffusion region; a conversion efficiency switching transistor; and a first pixel separation section. The semiconductor substrate has a first surface and a second surface that are opposed to each other. The semiconductor substrate has a photoelectric conversion section formed therein for each of the pixels. The photoelectric conversion section generates electric charge through photoelectric conversion. The electric charge corresponds to an amount of received light. The floating diffusion region is provided in the semiconductor substrate, and accumulates the electric charge generated by the photoelectric conversion section. The conversion efficiency switching transistor causes capacitance of the floating diffusion region to be variable.

Abstract: An image sensor includes a substrate including a first face and a second face, the second face being opposite the first face in a first direction; a photoelectric conversion area disposed in the substrate; an active area disposed in the substrate and on the photoelectric conversion area; an element isolation pattern extending from the first face of the substrate into the substrate and defining the active area; and a transfer gate electrode including: a first portion extending from the first face of the substrate and extending through the element isolation pattern; and a second portion disposed on the active area, wherein the first portion extends through a bottom face of the element isolation pattern, wherein a vertical level of a bottom face of the first portion is lower than a vertical level of the bottom face of the element isolation pattern.

Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.

Abstract: A photoelectric conversion apparatus includes a first member in a first semiconductor layer, a second member in a second semiconductor layer, and a third member in a third semiconductor layer. In the first semiconductor layer, a first member includes a photoelectric conversion unit and a transfer transistor configured to transfer an electric charge generated in the photoelectric conversion unit. In the second semiconductor layer, a second member includes a readout circuit configured to output a signal based on the electric charge transferred from the transfer transistor. In the third member includes a signal processing circuit configured to process the signal. The first member, the second member, and the third member are stacked, and a source region or a drain region of a transistor forming the readout circuit includes a salicide structure.

Abstract: An image sensor and method for fabricating are provided. The image sensor includes: a semiconductor substrate with multiple pixel regions formed thereon; adhesive frame formed on the semiconductor substrate, the adhesive frame including a peripheral adhesive frame arranged along the periphery of the semiconductor substrate and multiple reaction well adhesive frames disposed within the peripheral adhesive frame; a biological liquid crystal filled at least in each of the reaction well adhesive frames, the biological liquid crystal having an antigen-modified or an antibody-modified liquid crystal sensing interface; a glass coverplate disposed opposite to the semiconductor substrate; and a bonding layer, bonding the adhesive frames to the glass coverplate and loses a bonding power when heated or irradiated by UV light.

Abstract: A pixel 10 is provided with a lower metal electrode 41, an upper metal electrode 43, a capacitor insulation layer 42, contacts 44 and 45 and a contact 46. The lower metal electrode 41, upper metal electrode 43 and capacitor insulation layer 42 are formed on a semiconductor substrate 21, are clear of a region in which a photodiode 11 is formed, and are formed at a region in which a reading circuit 13 is formed. At least the contacts 44 and 45 electrically connect the lower metal electrode 41 with a metal wire 40, and at least the contact 46 electrically connects the upper metal electrode 43 with the metal wire 40.

Abstract: Sensitivity is improved.

Abstract: A light detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.

Abstract: There is provided a photoelectric conversion device including a photoelectric conversion unit, a floating diffusion, an amplification transistor, a capacitance addition transistor electrically connected to the floating diffusion. The photoelectric conversion device further includes a metal-oxide semiconductor (MOS) capacitive element and a wiring capacitive element that are electrically connected to the floating diffusion via the capacitance addition transistor.

Abstract: An image pickup unit includes a stacked device in a substantially rectangular parallelepiped shape including an external electrode, and a three-dimensional wiring board including a bonding electrode and an alignment mark on a bottom surface of a recess on a first principal surface and a projection, on a side surface, projecting in a first direction parallel to a wall surface of the recess, in which the external electrode of the stacked device that is disposed in the recess is bonded to the bonding electrode, and on the bottom surface, an area of a region in which a first region where the bonding electrode is virtually moved in the first direction and the alignment mark are superposed on each other is less than 50% of an area of the alignment mark.

Abstract: Some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. The techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. The array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. In this way, a performance of the backside illumination image sensor may be improved. Such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.

Abstract: Problems have been presented in terms of the step flatness of cured films used, inter alia, as wiring-insulating insulation films or protective films formed so as to cover metal wirings or light-emitting elements such as LEDs. The present invention overcomes problems relating to the incidence of wiring defects such as short-circuiting and defects associated with light-emitting element connection, and problems relating to the light-emission fault rate when this display device has been produced. The present invention is a display device having at least a metal wiring, a cured film, and a plurality of light-emitting elements, wherein a pair of electrode terminals are provided on one surface of each of the light-emitting elements. The pair of electrode terminals are connected to a plurality of the metal wirings extending in the cured film. The metal wirings are configured so that electrical insulation properties are maintained by the cured film.

Abstract: A light-emitting device includes a base semiconductor layer, a three-dimensional (3D) light-emitting structure, and a flat light-emitting structure formed in a flat shape, wherein the flat light-emitting structure generates light having a different wavelength than that of the 3D light-emitting structure. A strain-relieving layer relieving lattice mismatch between the base semiconductor layer and the flat light-emitting structure may be arranged on the base semiconductor layer in an area in which at least the flat light-emitting structure is formed.

Abstract: A display device includes a light-emitting element layer on a substrate, and a circuit element layer between the substrate and the light-emitting element layer. The circuit element layer includes a first metal layer including lines, and metal patterns, all in a same layer and extending in a direction and spaced apart from one another, and an upper gate line on the first metal layer. The light-emitting element layer includes first alignment electrodes and a second alignment electrode, disposed in a same layer and spaced apart from one another, light-emitting elements in gaps between the first alignment electrodes and the second alignment electrode, a first contact electrode on the light-emitting elements and in contact with first end portions of the light-emitting elements, and a first power connector, disposed in a same layer as the first contact electrode and electrically connecting the first voltage line and the metal patterns.

Abstract: A light emitting structure includes: a substrate; a first epitaxial structure disposed on the substrate; a second epitaxial structure disposed on the first epitaxial structure; and a third epitaxial structure disposed on the second epitaxial structure. Each of the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure comprises, in a sequentially stacked structure, a first semiconductor layer of a first conductivity, a carrier blocking layer, an active layer, and a second semiconductor layer of a second conductivity.

Abstract: A semiconductor light emitting device package can include a first layer having a first region and a second region surrounding the first region, a common electrode wiring on the first region of the first layer, a plurality of semiconductor light emitting devices on the common electrode wiring, a plurality of electrode wirings on upper sides of the plurality of semiconductor light emitting devices, a plurality of electrode pads on the second region of the first layer, and a second layer on the plurality of semiconductor light emitting devices, the plurality of electrode wirings, and the plurality of electrode pads. The first layer and the second layer can have an elliptical shape. The plurality of electrode pads can include a first electrode pad, a second electrode pad, a third electrode pad, and at least one or more common electrode pads.

Abstract: Discussed is an assembly substrate structure of a display device including a semiconductor light emitting device and a display device having the same. The assembly substrate structure of the display device including a semiconductor light emitting device can include an assembly substrate, a first assembly electrode and a second assembly electrode disposed spaced apart from each other on the assembly substrate, a magnetic structure disposed under the first assembly electrode and the second assembly electrode and an insulating layer disposed between the first and second assembly electrodes and the magnetic structure.

Abstract: The embodiment relates to a semiconductor light emitting device for a display pixel and a display device including the same. A semiconductor light emitting device for a display pixel according to an embodiment can include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer and an active layer disposed therebetween, a passivation layer disposed on the light emitting structure, and a second electrode layer disposed under the light emitting structure. The light emitting structure may include a rounding semiconductor layer in which an upper surface thereof is partially rounded.

Abstract: A display device includes a first pixel electrode disposed on a base layer, a first insulating layer disposed on the first pixel electrode and including an opening exposing the first pixel electrode, a first electrode and a second electrode disposed on the first insulating layer and spaced apart from each other with the opening disposed between the first electrode and the second electrode, a light emitting element disposed in the opening and including a first end portion electrically contacting the first pixel electrode and a second end portion, a second insulating layer covering the first insulating layer, the first electrode, and the second electrode and exposing the second end portion of the light emitting element, and a second pixel electrode disposed on the second insulating layer and electrically contacting the second end portion of the light emitting element.

Abstract: A display device includes an alignment electrode that includes a first electrode and a second electrode surrounding the first electrode; a first organic layer disposed on the alignment electrode and including an opening partially exposing the alignment electrode; and a light emitting element provided in the opening of the first organic layer.

Abstract: A semiconductor structure includes a recess extending into a substrate and an inductor device including a first isolation layer, a first magnetic layer over the first isolation layer, a second isolation layer over the first magnetic layer, and a conductive element surrounded by the second isolation layer, wherein at least a portion of the inductor device is disposed within the recess. A method of manufacturing a semiconductor structure includes disposing a first isolation layer on a surface of a substrate and extending into a recess formed on the surface; disposing a first magnetic layer over the first isolation layer; disposing a second isolation layer over the first magnetic layer to form a trench; disposing a conductive element in the trench; disposing a third isolation layer over the first magnetic layer, the conductive element and the second isolation layer; and disposing a second magnetic layer over the third isolation layer.

Abstract: A method for fabricating a semiconductor device includes sequentially stacking a sacrificial layer and a support layer on a substrate, forming bottom electrodes penetrating the sacrificial layer and the support layer to come into contact with the substrate, patterning the support layer to form a support pattern that connects the bottom electrodes to each other, removing the sacrificial layer to expose surfaces of the bottom electrodes, depositing a conductive layer on the exposed surfaces of the bottom electrodes and a surface of the support pattern, and etching the conductive layer. The etching the conductive layer includes selectively removing the conductive layer on the support pattern to expose the surface of the support pattern. The depositing the conductive layer and the etching the conductive layer are alternately performed in a same chamber.

Abstract: The semiconductor device is provided. The semiconductor device comprises a substrate; a plurality of lower electrodes on the substrate and arranged in a honeycomb structure; and a supporter connecting the plurality of lower electrodes to each other, wherein the supporter has a plurality of supporter holes defined therein, wherein each of the plurality of supporter holes exposes at least a portion of each of the plurality of lower electrodes, wherein the supporter includes: a plurality of first extensions extending in a first direction; and a plurality of second extensions extending in a second direction so as to intersect the plurality of first extensions, wherein each of the plurality of first extensions has first and second sidewalls, wherein each of the plurality of second extensions has third and fourth sidewalls, wherein each of the first to fourth sidewalls includes a convex portion and a concave portion.

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

Abstract: A method of manufacturing a semiconductor device includes: forming a lower layer of a repeating layer in which a first conductivity column and a second conductivity column are alternately arranged in a repeating direction by replacing a lower epitaxial layer for the first conductivity column with a region for the second conductivity column; and forming an upper layer of the repeating layer by replacing an upper epitaxial layer for the first conductivity column with a region for the second conductivity column. The second conductivity column includes a central portion and an end portion between the central portion and a boundary surface of the lower layer and the upper layer. A width of the end portion in the repeating direction is smaller than that of the central portion.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: A semiconductor device includes a first epitaxial (epi) layer that forms a first super-junction (SJ) layer of the semiconductor device and a second epi layer disposed on the first SJ layer that forms a device layer of the semiconductor device. The first epi layer includes oppositely doped SJ pillars that extend along a first direction within the SJ layer. The device layer includes device structures of a striped metal-oxide-semiconductor field-effect transistor (MOSFET) device cell that extends along a second direction within the device layer. The angle between the first direction and the second direction is substantially between forty-five degrees and ninety degrees, inclusive.

Abstract: A super junction MOSFET device, including: a substrate having a first conductive type; a buffer layer having the first conductive type and disposed on the substrate; a super junction structure disposed on the buffer layer and including multiple first conductive type pillars and multiple second conductive type pillars alternately arranged in a transverse direction, several second conductive type pillars being partially and/or wholly displaced to provide two or more different transverse dimensions for the first conductive type pillars; a body region having the second conductive type and disposed on a top of the second conductive type pillar; a source structure located within the body region and including a source region having the first conductive type and an ohmic contact region having the second conductive type which contacts with the source region; and a gate structure in contact with the first conductive type pillar and the source structure.

Abstract: Embodiments relates to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where an isolation trench is formed in the substrate; forming a first isolation layer in the isolation trench, where the first isolation layer fills the isolation trench, and a crack extending to an upper surface of the first isolation layer along a vertical direction is formed in the first isolation layer; removing part of the first isolation layer by etching back to form an isolation filling groove in communication with a top opening of the crack; and forming a second isolation layer in the isolation filling groove to plug the top opening of the crack, where the first isolation layer and the second isolation layer jointly constitute an isolation structure.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a front side of a substrate. The method also includes forming a gate structure surrounding the nanostructures. The method also includes forming a source/drain structure beside the gate structure. The method also includes forming a trench though the substrate from a back side of the substrate. The method also includes forming a first silicide layer in contact with the source/drain structure. The method also includes forming a second silicide layer over the first silicide layer and the sidewalls of the trench. The method also includes depositing a first conductive material over the second silicide layer. The method also includes etching back the first conductive material. The method also includes etching back the second silicide layer. The method also includes depositing a second conductive material in the trench.

Abstract: A semiconductor device includes an active pattern with a first impurity having a first conductivity, first and second nanosheets on the active pattern, a gate electrode on the active pattern and surrounding each of the first and second nanosheets, a lower source/drain region on the active pattern, an uppermost surface of the lower source/drain region being lower than a lower surface of the second nanosheet, and the lower source/drain region being doped with a second impurity having the first conductivity, an upper source/drain region on the lower source/drain region, the upper source/drain region being doped with a third impurity having a second conductivity different from the first conductivity, and a gate insulation layer between the gate electrode and the lower and upper source/drain regions, the gate insulation layer being in contact with each of the lower and upper source/drain regions.

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate, a pair of nanosheets on the fin-type active region, a gate line surrounding the pair of nanosheets, the gate line including a sub-gate portion between the pair of nanosheets, a source/drain region contacting the pair of nanosheets, and a gate dielectric film between the gate line and the pair of nanosheets and between the gate line and the source/drain region, wherein the source/drain region includes a first blocking layer between the pair of nanosheets, the first blocking layer including an edge barrier enhancing portion facing the sub-gate portion, and a second blocking layer, wherein the first blocking layer includes a portion that intermittently extends in the vertical direction.

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode on the p-type semiconductor layer, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode. Preferably, the buffer layer further includes a bottom portion having a first carbon concentration and a top portion having a second carbon concentration, in which the second carbon concentration is less than the first carbon concentration and a thickness of the bottom portion is less than a thickness of the top portion.

Abstract: A layer structure including a two-dimensional (2D) channel layer, a method of manufacturing a two-dimensional (2D) channel layer, an electronic device including the layer structure, and an electronic apparatus including the layer structure are disclosed. The layer structure may include a first substrate, a second substrate surrounded by the first substrate, and a 2D channel layer on the second substrate. An interfacial energy of the second substrate may be less than an interfacial energy of the first substrate. The method of manufacturing a 2D channel layer may include forming a second substrate to be surrounded by a first substrate, forming a precursor layer for forming a 2D channel on any one of the first and second substrates, and transforming the precursor layer into a liquid precursor layer. The interfacial energy of the second substrate may be less than the interfacial energy of the first substrate.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an active pillar, where the active pillar includes: a channel region, as well as a first doped region and a second doped region located at two sides of the channel region, the channel region, the first doped region, and the second doped region having a same doping type, where a counter-doped region is arranged in the channel region, the counter-doped region is close to the first doped region, and a doping type of the counter-doped region is different from a doping type of the channel region; and a gate, where the gate surrounds a part of the channel region, and in a plane in which an axis of the active pillar is located, projection of the gate partially overlaps with projection of the counter-doped region.

Abstract: A gallium nitride device and a method for manufacturing a high electron mobility transistor are provided. The gallium nitride device includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a cap layer disposed on the barrier layer, a gate disposed on the cap layer, a source, a drain, and ohmic sidewall dams. The source and the drain are formed in the cap layer and the barrier layer. Each of the source and the drain has a trench portion, and a contact below the trench portion and protruding into the channel layer. The ohmic sidewall dams are disposed on a sidewall of the trench portion of each of the source and the drain.