Abstract: A package structure is provided. The package structure includes a substrate, a conductive pad, and a conductive wire. The conductive pad is disposed over the substrate. The conductive wire includes an end portion connected to the conductive pad, wherein a grain arrangement of the end portion is distinct from a grain arrangement of the conductive pad.

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

Abstract: The present application discloses a drive chip and a display panel. The drive chip includes a first area and a second area. The drive chip includes a substrate and drive pins. The density of the pins located in the first area is lower than the density of the pins located in the second area. The pins located in the second area includes first drive pins and second drive pins. The distance between the substrate and a face of the first drive pins away from the substrate is greater than the distance between the substrate and a face of the second drive pins away from the substrate. The occurrence of poor electric conduction is avoided.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.

Abstract: A high-performance hybrid bonded interconnect structure and a method for producing a high-performance hybrid bonded interconnect structure is discloses. The interconnect structure may comprise a first plurality of die stacks bonded to a carrier. A protective layer may be provided over at least a portion of the first plurality of die stacks and the second plurality of die stacks. A bridging layer comprising a conductive interconnect may provide electrical communication between the plurality of die stacks.

Abstract: A semiconductor device includes a substrate and a conductive pad coupled to the substrate. A first solder mask is coupled to the substrate and to a portion of the conductive pad so the first solder mask covers the portion of the conductive pad and extends above the conductive pad. A second solder mask is coupled to a portion of the first solder mask and extends above the first solder mask.

Abstract: In some embodiments, a semiconductor device assembly can include a first semiconductor die, a second semiconductor die, and an interconnection structure therebetween. The interconnection structure can directly electrically couple the first and the second semiconductor dies. The interconnection structure can include an inner metallic pillar, an outer metallic shell, a continuous metallic bridging layer, and a dielectric liner. The outer metallic shell can surround and be spaced from the inner metallic pillar, the continuous metallic bridging layer can be over and connected with the inner metallic pillar and the outer metallic shell, and the dielectric liner can be between the inner metallic pillar and the outer metallic shell. In some embodiments, the second semiconductor die can be excluded and the interconnection structure can solely be coupled to the first semiconductor die.

Abstract: A substrate bonding method includes: providing a first and a second substrate; forming, on the first substrate, a first metal micro-bump array including first metal pillar(s) formed on the first substrate and first metal nanowires formed thereon and spaced apart from each other; forming, on the second substrate, a second metal micro-bump array including second metal pillar(s) formed on the second substrate and second metal nanowires formed thereon and spaced apart from each other; pressing the first substrate onto the second substrate, such that the first and second metal micro-bump arrays are positioned and staggered with each other, forming a physically interwoven interlocking structure between the first and second metal nanowires; applying a filling material between the first and second substrates; curing the filling material to form a bonding cavity; and then performing confined heating reflux on the first and second metal micro-bump arrays in the bonding cavity.

Abstract: An electronic device according to the present disclosure includes a semiconductor substrate, a chip, and a bump. The chip has a thermal expansion coefficient different from that of the semiconductor substrate. The bump connects the connection pads provided on the opposing principal surfaces of the semiconductor substrate and the chip. The bump has a porous metal layer and a metal film. The metal film is provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on the side surfaces of the porous metal layer.

Abstract: In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

Abstract: A semiconductor device may include a lower structure including a first substrate, a first pad on the first substrate, and a first insulating layer enclosing the first pad, and an upper structure including a second substrate, a second pad on the second substrate, and a second insulating layer enclosing the second pad. Each of the first and second pads may include a first portion and a second portion on the first portion. The second portion may include the same metallic material as the first portion. The second portion of the first pad may be in contact with the second portion of the second pad, and the first insulating layer may be in contact with the second insulating layer.

Abstract: A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

Abstract: A heat radiation structure includes a vapor chamber provided along a surface of a die, a mesh interposed between the die and the vapor chamber, and a liquid metal impregnated in the mesh. In the mesh, a peripheral portion has a higher material density per unit volume than a central portion. In the mesh, the central portion may be formed of a single layer, and the peripheral portion is formed of two layers. The mesh may be a resin material.

Abstract: A semiconductor device includes a semiconductor substrate and a metal layer disposed on a surface of the semiconductor substrate. The metal layer includes a first metal layer and a second metal layer. The second metal layer covers a surface of the first metal layer and has a higher solder wettability than the first metal layer. The second metal layer is exposed on a main surface of the metal layer. The first metal layer is exposed on a side surface of the metal layer. The metal layer has a protruding portion on the main surface. The protruding portion extends to make one round along an outer peripheral edge of the main surface.

Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

Abstract: According to one embodiment, a semiconductor chip includes a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metallic layer. The semiconductor layer includes a first portion, a second portion, and a third portion that is located between the first portion and the second portion. The semiconductor layer is provided on a first side of the first electrode in a first direction. The second electrode is over the first portion in the first direction. The third electrode is over the second portion in the first direction. The metallic layer is provided on a second side of the first electrode and is under the third portion in the first direction.

Abstract: A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.

Abstract: A semiconductor device according to an embodiment includes a metal frame separated from a semiconductor chip, and a metal connector connected to the semiconductor chip via a first bonding material on an electrode of the semiconductor chip, and connected to the metal frame via a second bonding material on a disposition surface of the metal frame. The metal connector includes: a first part connected to the first bonding material and serving as a first end; a second part connected to the first part and rising toward the metal frame; a third part connected to the second part and serving as a second end; and a notch that opens on a second-end-side surface formed on the third part, adjacent to a connecting surface connected to the second bonding material, and opposed to a tilted surface of the metal frame adjacent to and tilted with respect to the disposition surface.

Abstract: A method of dispensing an underfill material on a semiconductor device package. A substrate having a semiconductor chip electrically connected thereto and offset from the substrate by solder joints is provided. The semiconductor chip has a footprint defined by a length and width of the semiconductor chip. Standoff heights between the substrate and the semiconductor chip are calculated and used to determine a volume of underfill material needed to substantially fill a space between the substrate and the semiconductor chip. The determined volume of underfill material is dispensed on the substrate such that the space between the substrate and the semiconductor chip is substantially filled by the underfill material. The method may allow for improved dispensing an underfill material to substantially fill the space between the substrate and semiconductor chip when variations in standoff height are present.

Abstract: A wire bonding apparatus includes a bonding stage, a capillary, a clamp provided with the capillary rotatably installed thereon, and a bonding arm. The clamp includes a housing having an internal space, a first member fixedly installed at an upper end of the internal space of the housing and provided with a first gear unit on a lower surface thereof, a second member fixedly installed at a lower end of the internal space of the housing to be spaced apart from the first member, and provided with a second gear unit on an upper surface thereof, a third member, the third member being provided with a third gear unit corresponding to the first gear unit and a fourth gear unit corresponding to the second gear unit, . The capillary is fixedly installed on the third member and rotates in conjunction with the third member.

Abstract: A method includes directly bonding a first wafer to a second wafer, wherein the bonding electrically connects a first interconnect structure of the first wafer to a second interconnect structure of the second wafer; directly bonding first semiconductor devices to the second wafer, wherein the bonding electrically connects the first semiconductor devices to the second interconnect structure; encapsulating the first semiconductor devices with a first encapsulant; and forming solder bumps over the first semiconductor devices.

Abstract: A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.

Abstract: A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

Abstract: A semiconductor device includes a plurality of top semiconductor dies. Each of the plurality of top semiconductor dies can be bonded to a bottom semiconductor die. The semiconductor device includes a redistribution structure disposed opposite the plurality of top semiconductor dies from the plurality of bottom semiconductor dies and comprising a plurality of interconnect structures. A top semiconductor die can connect to another top semiconductor die via a first subset of the plurality of interconnect structures.

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

Abstract: Systems and techniques that facilitate high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices are provided. In various embodiments, a device can comprise a superconducting qubit wafer that can be coupled, by one or more first bump-bonds, to a parametric Josephson wafer. In various aspects, the device can further comprise a first underfill that surrounds the one or more first bump-bonds. In various instances, the first underfill can protect the parametric Josephson wafer from mechanical and/or chemical degradation associated with subsequent fabrication, processing, and/or handling of the superconducting qubit wafer.

Abstract: Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.

Abstract: An AI module includes a first semiconductor chip. The first semiconductor chip includes a plurality of operation blocks each of which performs a predetermined operation and a plurality of memory blocks each including memory. The plurality of operation blocks and the plurality of memory blocks are arranged in a checkered pattern or in a striped pattern in plan view.

Abstract: A semiconductor package and method of fabricating the same are provided. The semiconductor package includes a first semiconductor chip including first and second surfaces opposite to each other; connection terminals on the first surface of the first semiconductor chip; a first dielectric layer on the second surface of the first semiconductor chip; a second semiconductor chip on the first dielectric layer and including a third surface opposite to the second surface and a fourth surface opposite to the third surface; a second dielectric layer on the third surface of the second semiconductor chip and in contact with the first dielectric layer; a third semiconductor chip on the fourth surface of the second semiconductor chip; and a first adhesive layer between the second semiconductor chip and the third semiconductor chip, the first dielectric layer and the second dielectric layer including no wirings.

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, and having widths narrower than a width of the first semiconductor chip, and a molded layer on an upper surface of the first semiconductor chip. The first semiconductor chip includes first front-surface pads, a first back-surface insulating layer divided into a first region and a second region, first back-surface pads in the first region, dummy pads in the second region, the dummy pads respectively having an upper surface on which a metal oxide film is disposed, and a first through-electrode electrically connecting the first front-surface pads and the first back-surface pads to each other. The plurality of second semiconductor chips respectively includes second front-surface pads, second back-surface pads, and a second through-electrode electrically connecting the second front-surface pads and the second back-surface pads to each other.

Abstract: Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

Abstract: A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

Abstract: A semiconductor module according to the present disclosure includes a circuit board having a first surface and a second surface, a first semiconductor device mounted on the first surface of the circuit board, a second semiconductor device mounted on the second surface of the circuit board, a first heat dissipation substrate placed on the top of the first semiconductor device, and a second heat dissipation substrate placed on the top of the second semiconductor device. The first heat dissipation substrate is coupled to a second surface of the first semiconductor device and the second heat dissipation substrate is coupled to a second surface of the second semiconductor device.

Abstract: A semiconductor device includes semiconductor elements. Each semiconductor element, including first, second and third electrodes, is controlled to turn on and off current flow between the first electrode and the second electrode by drive signals inputted to the third electrode. The first electrodes of the semiconductor elements are electrically connected mutually, and the second electrodes of the semiconductor elements are electrically connected mutually. The semiconductor device further includes a control terminal receiving the drive signals, a first wiring section connected to the control terminal, a second wiring section, and third wiring sections, and further a first connecting member electrically connecting the first and the second wiring sections, a second connecting member electrically connecting the second wiring section and each third wiring section, and third connecting members connecting the third wiring sections and the third electrodes of the semiconductor elements.

Abstract: Techniques and mechanisms for a micro-LED (“uLED”) structure to facilitate efficient communication of an optical signal. In an embodiment, a columnar “nanopost” uLED structure comprises contiguous bodies of respective semiconductor materials, including a first body of a doped semiconductor material. The first body forms a pyramidal structure, wherein one or more others of the contiguous bodies are arranged on the first body in a vertically stacked configuration. More particularly, a second body of an undoped semiconductor material is to provide a quantum well of the uLED structure, wherein the second body does not cover or otherwise extend along vertical sidewall structures of the first body. In another embodiment, the pyramidal structure, in combination with the vertically stacked arrangement of semiconductor bodies, facilitates efficient communication of narrowly columnated optical signal by mitigating optical signal communication via vertical sides of the uLED structure.

Abstract: An embodiment of present invention discloses a light-emitting device which includes a first light-emitting area, a second light-emitting area, and a third light-emitting area. The first light-emitting area emits a red light and includes a first light-emitting unit. The second light-emitting area emits a blue light and includes a second light-emitting unit. The third light-emitting area emits a green light and includes a third light-emitting unit. The first light-emitting area is larger than the second light-emitting area and larger than the third light-emitting area. Each of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit has a width of less than 100 ?m and a length of less than 100 ?m.

Abstract: Provided is a display panel including a substrate, a drive array layer, a light-shielding layer and multiple light-emitting components. The drive array layer is located on a side of the substrate and includes multiple first grooves. The light-shielding layer is located on a side of the drive array layer facing away from the substrate, the light-shielding layer includes multiple first openings, the multiple first openings penetrate through the light-shielding layer, and an orthographic projection of a first groove on the substrate at least partially surrounds an orthographic projection of a respective first opening of the multiple first openings on the substrate. An orthographic projection of a light-emitting component on the substrate at least partially overlaps with an orthographic projection of a respective first opening of the multiple first openings on the substrate. At least part of the light-shielding layer is located within the multiple first grooves.

Abstract: Provided are a light emitting device, a method for manufacturing same, and a display device including the light emitting device.

Abstract: A semiconductor package includes a first redistribution structure having a first redistribution layer; a first semiconductor chip on the first redistribution structure, and having first lower pads, first upper pads, and first through-electrodes; a second semiconductor chip on the first semiconductor chip, and having second lower pads, second upper pads, and second through-electrodes; a vertical connection conductor on the first redistribution structure, and connected to the first redistribution layer; a molded portion on the first redistribution structure, and surrounding the first second semiconductor chips; a second redistribution structure on the second semiconductor chip and the vertical connection conductor, the second redistribution structure having a second redistribution layer connected to the second upper pads and the vertical connection conductor; and a third semiconductor chip on the second redistribution structure, and having contact pads connected to the second redistribution layer.

Abstract: A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged arou

Abstract: A package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. The first die and a second die are disposed on the package substrate. The first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. The second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.

Abstract: A miniaturized semiconductor package device using trenches for increased component density includes a redistribution layer, an electronic device, a molding layer, and conductive terminals. The redistribution layer includes a first surface, a second surface opposite to the first surface, a trench on the first surface, and a circuit layer. The electronic device is disposed in the trench and electrically connected to the circuit layer. The molding layer is formed on the first surface and covers the electronic device. The conductive terminals are disposed on the second surface of the redistribution layer and form electrical connections to the circuit layer.

Abstract: A module is described. The module includes two dies which are stacked over a top insulating layer of a PCB. When both dies are be connected to the PCB through a copper pillar, the top die has a taller interconnect and the bottom die has a shorter interconnect. To further reduce a height of the module, the bottom die and/or the top die may be placed into a cavity of the PCB and a bulk silicon layer of the top die may be grinded away.

Abstract: The present application provides a substrate encapsulating method, a display panel, and a display device. The substrate encapsulating method includes providing a first underlay, and fabricating a switching device on the first underlay to form a switching substrate; providing a second underlay, and fabricating a light-emitting diode on the second underlay to form a light-emitting substrate; applying a frame glue to an edge of the switching substrate or an edge of the light-emitting substrate; and bonding the switching substrate and the light-emitting substrate with the frame glue to seal the light-emitting diode between the switching substrate and the light-emitting substrate.

Abstract: A display device is provided and includes: a plurality of display modules disposed on the first bearing surface, each of the display modules including a plurality of display units; a plurality of first functional elements located on the first bearing surface, and each of the first functional elements disposed between any two of the display units; and a plurality of second functional elements located on the second bearing surface; wherein a function of each of the second functional elements is the same as a function of each of the first functional elements, and processing capability of each of the second functional elements is different from processing capability of each of the first functional elements.

Abstract: The invention provides a transparent display, which comprises a plurality of horizontal circuit layers, wherein each horizontal circuit layer extends along a horizontal direction, a plurality of vertical conductive plugs connect the horizontal circuit layers with each other, a control integrated circuit located on one of the horizontal circuit layers, and at least one light-emitting element located on another horizontal circuit layer, wherein the control integrated circuit overlaps with the at least one light-emitting element in a vertical direction.

Abstract: An optical device includes: an optical element that is rectangular as seen in a top view, and that has a light-receiving portion at a top surface thereof; a wiring substrate on which the optical element is mounted; wires electrically connecting the optical element and the wiring substrate at from one to three sides of the rectangular optical element; a resin portion formed at a periphery of the optical element, and covering a portion of the top surface of the optical element including the wires; and an opening portion that is concave, that is provided in the resin portion, and that is formed by a molding die such that at least the light-receiving portion and the top surface at a periphery of the light-receiving portion are exposed, wherein the resin portion that structures a bottom surface at the opening portion is flush with the top surface.