Abstract: A display device including: electrodes on a base layer; an insulating layer on the electrodes and including a first protruding pattern and a second protruding pattern; light emitting elements on the insulating layer, a light emitting element from among the light emitting elements including a first end and a second end, wherein the light emitting elements include a first light emitting element, the first end of the first light emitting element being adjacent to the first protruding pattern, and the second end of the first light emitting element being adjacent to the second protruding pattern; a first connecting electrode electrically connected to the first end of the first light emitting element and including a first base portion and first protruding portions connected to the first base portion; and a second connecting electrode electrically connected to the second end of the first light emitting element.

Abstract: A display device having a display region includes a substrate, a plurality of organic light emitting parts disposed on the substrate in the display region, an organic layer disposed on at least one of the plurality of organic light emitting parts, a circuit layer disposed on the substrate, and a first layer disposed between the organic layer and the circuit layer. At least a portion of the organic layer has a curved profile.

Abstract: A semiconductor module includes: first and second switching devices coupled in series; a casing housing the first and second switching devices, and having first to fourth edges respectively on first to forth edge sides thereof; positive and negative terminals provided on the first edge side of the casing; an output terminal provided on the second edge side of the casing; a first control terminal and a first sense terminal for the first switching device, and a second control terminal and a second sense terminal for the second switching device, all provided on the third edge side of the casing; first and second conductive patterns respectively coupled to the positive terminal and the output terminal, and on which the first and second switching device are respectively arranged; and a third conductive pattern coupled to the negative terminal and the second switching device, on a side corresponding to the fourth edge side.

Abstract: A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patterns overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

Abstract: To reduce the chip size of a chip-type electronic component including a capacitor and an inductor. A chip-type electronic component includes a capacitor constituted by a lower electrode pattern, an upper electrode pattern, and an insulating layer, an insulating layer covering the capacitor, and an inductor pattern disposed on the insulating layer. The inductor pattern has a section overlapping the capacitor, whereby an auxiliary capacitor is added. The inductor pattern is thus made to partly overlap the capacitor, so that a larger inductance can be obtained with a small chip size. In addition, characteristics can also be improved by auxiliary capacitance.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a logic cell. The logic cell includes a first transistor and a second transistor. The first transistor includes a first gate structure extending in a first direction and overlapping a first semiconductor fin. The second transistor includes a second gate structure extending in the first direction and overlapping the first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins extend in a second direction that is perpendicular to the first direction. The first and second transistors share a source/drain region, and one end of the first gate structure is formed between the first and second semiconductor fins.

Abstract: A semiconductor device includes a semiconductor body including an upper surface, input and output terminals disposed on the upper surface of the semiconductor body, first and second p-n junction devices that are monolithically integrated in the semiconductor body, and a signal line protection circuit connected between the input and output terminals and comprising a low-pass filter and a voltage clamping device, wherein each of the low-pass filter and the voltage clamping device include the first and second p-n junction devices.

Abstract: In a semiconductor integrated circuit device, first and second interconnects extending in the X direction are formed in a metal interconnect layer. The first and second interconnects are placed on the opposite sides of each resistor element in the X direction and connected to the resistor element. The first interconnect is connected to PAD, and a third interconnect is connected to VSS. In an ESD protection diode, an anode and a cathode are formed alternately in the Y direction. The resistor element and the first and second interconnects overlap the cathode of the ESD protection diode, and the third interconnect overlaps the anode of the ESD protection diode, in planar view.

Abstract: A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: An integrated circuit (IC), including a first row of cells including a first set of one or more complementary metal oxide semiconductor (CMOS) signal processing cells including a first diffusion region; a second row of cells including a second set of one or more CMOS signal processing cells including a second diffusion region; and a first body tie electrically coupling a first voltage rail to the first and second diffusion regions.

Abstract: A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits of the front end can include N-polar III-N transistors that are all formed from the same epitaxial material structure and monolithically integrated onto a single chip. Due to the different performance requirements of the various transistors in the different circuits, parameters such as gate length, gate-to-channel separation, and surface-to-channel separation in the access regions of the devices can be varied to meet the desired performance requirements.

Abstract: A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

Abstract: A microelectronic device includes a first transistor having a first drain and a first source, a first doped zone constituting one from among the first drain and the first source, a second doped zone constituting the other from among the first drain and the first source, a second transistor comprising a second drain and a second source, a third doped zone constituting the second source or the second drain, a fourth doped zone constituting the other from among the second drain and the second source, a dielectric layer having an upper face in contact with the four doped zones and a rear gate in contact with a lower face of the dielectric layer. The second doped zone and the fourth doped zone form a common electrode.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, an array layer, an inorganic insulation layer, a conductive electrode, a passivation layer, and a pixel electrode disposed in sequence. The array layer includes a source electrode and a drain electrode. A first via hole is defined in the array substrate. The first via hole penetrates the passivation layer and the inorganic insulation layer and exposes the drain electrode. The pixel electrode is connected to the drain electrode in the first via hole.

Abstract: An electronic device and a display panel are provided. The display panel has a display region and a bending region positioned at one side of the display region. The display panel includes a first transparent substrate, a first inorganic layer, a second inorganic layer, and a blocking layer positioned at one side of the first transparent substrate. The second inorganic layer has a first via in the bending region of the display panel. This alleviates the mura near the bending region due to the exposure of the first transparent substrate and thus alleviates the mura issue occurred on the conventional display panel close to the bending region.

Abstract: An array substrate includes a first substrate and a planarization layer disposed on a side of the first substrate. The planarization layer is provided with a first through hole. A cross-sectional area of the first through hole gradually decreases in a direction from the planarization layer toward the first substrate. An angle between a sidewall of the first through hole and a bottom surface of the first through hole is 50° to 90°.

Abstract: An object of the present invention is to provide a technology using which, in a thin film transistor using oxide semiconductor, the resistance of a channel region of the oxide semiconductor is made high, and at the same time the resistances of a source region and a drain region of the oxide semiconductor are made low. There is provided a semiconductor device including: a thin film transistor including oxide semiconductor, the oxide semiconductor including a channel region, a drain region, and a source region; a gate insulating film formed on the channel region; an aluminum oxide film formed on the gate insulating film; and a gate electrode formed on the aluminum oxide film, wherein the aluminum oxide film has a region that covers neither the drain region nor the source region in a plane view.

Abstract: The present application provides an array substrate and a display panel. The array substrate includes a substrate, a first gate electrode, a first insulating layer, a first electrode, a second gate electrode, a first conductive channel, and a second electrode. The present application reduces a leakage current of the array substrate by using an orthographic projection of the first gate electrode on the substrate to overlap an orthographic projection of the first conductive channel on the substrate.

Abstract: The embodiments of the application disclose a display panel and a method of manufacturing same. In the display panel, an active layer includes a first part, a second part, a conductor part, and a channel part. The conductor part is disposed between the first part and the second part and is connected to the channel part. A first metal layer includes a gate electrode, which overlaps the channel part. A second metal layer includes a source electrode and a drain electrode, the source electrode is connected to the first part, and the drain electrode is connected to the second part.

Abstract: The present application discloses an array substrate and a display panel. The array substrate comprises a flexible substrate, a thin-film transistor layer, a planarization layer, and a pixel electrode layer, wherein the thin-film transistor layer comprises driving circuit units and metal wires, a groove is defined between adjacent driving circuit units, and a plurality of protrusions are formed at positions where the groove overlaps the metal wires. The array substrate according to the present application improves stability of the array substrate.

Abstract: A pixel array, a display panel, and a display device are provided. The pixel array includes a first pixel electrode, a first data line, and a second data line. The first pixel electrode includes a first side and a second side opposite to the first side. The first data line is electrically connected to the first pixel electrode. The first data line is adjacent to the first side of the first pixel electrode and extends to the second side. The second data line is adjacent to the first data line. At least a portion of the second data line is disposed between the second side and the first data line. The first data line and the second data line are respectively configured to transmit signals with opposite polarities.

Abstract: A display panel and a display device are provided. The display panel includes a driving backplate and a plurality of display substrates. At least one first opening is defined in a first base and a first bonding terminals of the display substrates, the first opening penetrates the first base and the first bonding terminals, a bridging terminal is disposed in the first opening, the bridging terminal is electrically connected to a lateral surface of the first bonding terminals, so that a problem of poor connection between a display screen and a motherboard existing in current bezel-free splicing display technology is relieved.

Abstract: An array substrate and a display terminal are provided. The display panel includes the plurality of stacked metal sub-layers and the first passivation sub-layer and the second passivation sub-layer stacked. The first passivation sub-layer is disposed between the metal layer and the second passivation layer. Material of the first passivation sub-layer includes silicon nitride. The first passivation sub-layer covers the untidy area at the ends of the molybdenum-titanium alloy thin layer to avoid from detachment of the passivation layer, and meanwhile to solve the issues of simplifying the manufacturing process of the display panel, and to avoid from oxidation of the bonding pads.

Abstract: A display panel and a method for manufacturing the same are provided. The display panel includes a first bonding area and a second bonding area connected to the first bonding area. The display panel further includes a substrate and a bonding wiring layer. A thickness of a part of the substrate in the second bonding area is less than a thickness of a part of the substrate in the first bonding area. The bonding wiring layer is disposed on surfaces of the parts of the substrate in the first bonding area and the second bonding area. A side surface of the bonding wiring layer away from the first bonding area and a side surface of the substrate away from the first bonding area are located on a same plane.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a middle display region, and first and second peripheral display regions arranged at two opposite sides of the middle display region respectively. Each pixel unit includes at least two sub-pixels in different colors and having a rectangular shape including long and short sides. In the middle display region and at least one of the first and second peripheral display regions, the sub-pixels in each pixel unit are sequentially arranged along a short side extension direction, extension directions of the first and second peripheral display regions are perpendicular to the short side extension direction in the middle display region, and the short side extension direction in at least one of the first and second peripheral display regions is perpendicular to the short side extension direction in the middle display region.

Abstract: To provide a semiconductor device that occupies a small area. The semiconductor device includes a first conductive layer, first to fifth insulating layers, and a second conductive layer that are stacked in this order and further includes a semiconductor layer, a third conductive layer, and a sixth insulating layer. The semiconductor layer is in contact with the top surface of the first conductive layer, the side surfaces of the first to fifth insulating layers, and the second conductive layer. The sixth insulating layer is over the semiconductor layer. The third conductive layer is over the sixth insulating layer and overlaps with the semiconductor layer with the sixth insulating layer between the third conductive layer and the semiconductor layer. The first insulating layer includes a region having a higher hydrogen content than the second insulating layer. The fifth insulating layer includes a region having a higher hydrogen content than the fourth insulating layer.

Abstract: A display panel and a method for fabricating the same are disclosed. The display panel includes a base substrate, a micro-light emitting device layer and a thin film transistor array layer. The micro-light emitting device layer is disposed on one side of the base substrate, a light output side faces to the base substrate, and the thin film transistor array layer is formed on the side of the micro-light emitting device layer facing away from the light output side. LED chips do not need to be bound and connected to the thin film transistor array layer through a conductive adhesive bonding process or a metal bonding process during mass transfer, so that the stability and yield are improved.

Abstract: The present application provides a display panel, a display device, and a manufacturing method of the display panel. The display panel includes a substrate, a first terminal, a conductive line, and a first connecting member. The first terminal is arranged on a first surface of the substrate. The conductive line is at least partially arranged on a side surface of the substrate and is spaced apart from the first terminal. The first connecting member is connected between the conductive line and the first terminal to make the conductive line electrically connected to the first terminal, and therefore improve electrical connection between the conductive line and the first terminal.

Abstract: The present application sets forth an array substrate and a display terminal. The array substrate includes an underlay, a light shielding layer disposed on the underlay, an active layer disposed on the light shielding layer, and a connection element disposed on the active layer. The light shielding layer includes light shielding portions spaced from one another. The active layer includes active portions spaced from one another. The active portions correspond to the light shielding portions. Furthermore, adjacent two active portions are electrically connected through a bridge element. A toughness of the bridge element is greater than a toughness of the active portion.

Abstract: A display panel, a fabrication method of the display panel, and a display apparatus are provided in the present disclosure. The display panel includes a substrate; a drive substrate on the substrate, where the drive substrate includes a first film layer; and the first film layer includes a first opening; and a light-emitting element on the drive substrate, where the light-emitting element is disposed corresponding to the first opening. The drive substrate further includes an auxiliary film layer; and the auxiliary film layer includes a thickened part, a thinned part, or a hollow part overlapped with the first opening.

Abstract: A display device may include a source electrode disposed on a substrate; a drain electrode disposed on the substrate; an insulating layer disposed on the source electrode and the drain electrode, the insulating layer including an opening overlapping the drain electrode; and a first electrode disposed on the insulating layer and electrically contacting the drain electrode in the opening of the insulating layer, wherein an angle between a side surface of the opening of the insulating layer and a plane parallel to the substrate is in a range of about 70 degrees to about 85 degrees.

Abstract: A display device and a manufacturing method thereof are provided. The display device includes a substrate, a switching thin film transistor, and a driving thin film transistor. The switching thin film transistor includes a first gate, a first active layer, a first source, and a first drain disposed on the substrate, wherein the first source and the first drain are disposed on a side of the first active layer away from the substrate. The driving thin film transistor includes a second source, a second drain, a second active layer, and a second gate disposed on the substrate, wherein the second active layer is positioned on a side of the second source and the second drain away from the substrate.

Abstract: An embodiment of the present application discloses a display panel manufacturing method and a display panel including a driver transistor, a storage capacitor, a switch transistor, and a sensing transistor vertically stacked. At leas two transistors are vertically stacked to solve a technical issue that a pixel in a conventional display panel employs a pixel circuit design of transistors and capacitors arranged along a direction parallel to the display panel to cause a lowered pixel density of the display panel to result in a lowered resolution of a display panel product.

Abstract: A display device includes a semiconductor pattern. A first capacitor electrode under the semiconductor pattern. A second capacitor electrode on the semiconductor pattern, the second capacitor electrode including a portion forming a gate electrode. A first electrode and a second electrode at a same layer on the second capacitor electrode. At least one light emitting element between the first electrode and the second electrode. A first pixel electrode on the first electrode and connected to a first end of the at least one light emitting element. A second pixel electrode on the second electrode and connected to a second end of the at least one light emitting element. The first electrode is connected to the first capacitor electrode and the semiconductor pattern. The semiconductor pattern and the gate electrode form a transistor. A first capacitor is formed by the first and second capacitor electrodes.

Abstract: An array substrate and a manufacturing method thereof are provided. A metal film layer is formed on an active layer of the array substrate. The metal film layer protects the active layer from being damaged by an etchant liquid or dry etching process during patterning processing of a source electrode/a drain electrode. Afterwards, a portion of the metal film layer that corresponds to a channel of the active layer the channel is subjected to oxidizing processing to form an oxide layer to help keep the functional property of the active layer. In the entire manufacturing process of the array substrate, the active layer will not be subject to damage in subsequent processing and stability of the device can be maintained.

Abstract: A method for fabricating an array substrate, the array substrate, a display panel, and a thin film transistor are provided. The thin film transistor includes a gate electrode, an active layer, a source electrode, a drain electrode, and an interlayer insulating layer. The active layer is disposed corresponding to the gate electrode. The source electrode and the drain electrode are disposed at both sides of the active layer and electrically connected to the active layer. The interlayer insulating layer is disposed between the active layer and the source electrode, and between the active layer and the drain electrode. The interlayer insulating layer is provided with step-shaped contact holes. The source electrode and the drain electrode are filled in the contact holes and electrically connected to the active layer.

Abstract: A solid-state imaging device according to an embodiment of the present disclosure includes a stacked photoelectric converter for each of pixels. The stacked photoelectric converter has a plurality of photoelectric conversion elements stacked therein. The plurality of photoelectric conversion elements each has different wavelength selectivity. This solid-state imaging device further includes a plurality of data output lines from which pixel signals based on electric charges outputted from the photoelectric conversion elements are outputted. A plurality of data output lines is provided for each predetermined unit pixel column. The plurality of the data output lines is equal in number to an integer multiple of the photoelectric conversion elements stacked in the stacked photoelectric converter.

Abstract: To prevent the occurrence of a defect in an infrared-light attenuation filter and prevent a reduction in image quality. An imaging device includes a photoelectric converter, an on-chip lens, a color filter, the infrared-light attenuation filter, and a protective film. The photoelectric converter performs photoelectric conversion depending on incident light. The on-chip lens collects the incident light into the photoelectric converter. Infrared light and visible light of a specified wavelength from among the collected incident light are transmitted through the color filter. The infrared-light attenuation filter attenuates the infrared light from among the collected incident light, and visible light from among the collected incident light is transmitted through the infrared-light attenuation filter. The protective film is arranged adjacent to the infrared-light attenuation filter and protects the infrared-light attenuation filter.

Abstract: The invention relates to a light transit time pixel comprising —at least one modulation gate (GA, GB) which has a photoactive region (FAB) and a storage region (MA, MB), said storage region (MA, MB) having a locally increased n-type doping below the modulation gate (GA, GB) and delimiting the photoactive region (FAB) of the modulation gate (GA, GB), —at least one transfer gate (TXA, TXB) which adjoins the storage region (MA, MB) of the modulation gate (GA, GB), —at least one reading diode (DA, DB) which follows the transfer gate (TXA, TXB), —at least one drain gate (DG) which adjoins one side of the light-sensitive region (FAB) of the modulation gate (GA, GB), and —at least one drain diode (DD) which follows the drain gate (DG).

Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.

Abstract: The stacked image sensor includes a first semiconductor substrate and including a photoelectric conversion region and a floating diffusion area, a first insulating layer under the first semiconductor substrate and including a gate of a transfer transistor, a second semiconductor substrate under the first insulating layer and including first impurities of a first conductivity type, and a second insulating layer under the second semiconductor substrate and including a metal pad of a floating diffusion node and a gate of a source follower transistor, wherein the floating diffusion area and the metal pad of the floating diffusion node are electrically connected through a deep contact that is in the first insulating layer and the second semiconductor substrate. The second semiconductor substrate further includes a well region. At least a portion of deep contact may be in the well region. The well region may surround the deep contact.

Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a thin film transistor layer including a first thin film transistor and an infrared detection element disposed on a first side of the thin film transistor layer. The infrared detection element includes a first electrode, a light-absorbing layer, and a second electrode sequentially stacked, wherein the infrared detection element is electrically connected to the first thin film transistor, and wherein a material of the light-absorbing layer is microcrystalline silicon. A thickness and band gap of the microcrystalline silicon simultaneously fulfill a purpose of infrared detection.

Abstract: An image sensor may include; a semiconductor substrate including a first surface and a second surface, and further including a photoelectric conversion region, a buried gate structure disposed in a buried gate trench extending into the semiconductor substrate from the first surface of the semiconductor substrate, a floating diffusion region disposed on one side of the buried gate structure in the semiconductor substrate, a contact pad disposed on the first surface of the semiconductor substrate above the floating diffusion region and including polysilicon, an intermediate layer disposed on the contact pad and including a metal silicide, and a contact disposed on the intermediate layer and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate.

Abstract: A semiconductor package includes: a package substrate; a semiconductor chip disposed on the package substrate; a transparent substrate disposed on the semiconductor chip; and an adhesive layer that is disposed between the semiconductor chip and the transparent substrate. The adhesive layer is configured to block light. The transparent substrate includes: a first lower side that faces the semiconductor chip, a second lower side that faces the semiconductor chip and that is disposed above the first lower side, and a first inner side wall that connects the first lower side and the second lower side, and the adhesive layer is in contact with the second lower side and the first inner side wall.

Abstract: In a solid-state imaging device, a material forming an underfill part is prevented from flowing toward a side of a pixel region, shortening of a distance between an end portion of an opening of a substrate and the pixel region is enabled, and miniaturization is promoted. The device includes: an imaging element having a pixel region including a large number of pixels on one plate surface of a semiconductor substrate; a substrate provided on the surface side with respect to the imaging element and having an opening for passing light to be received by the pixel region; and an underfill part including a cured fluid and covering a connection part that electrically connects the imaging element and the substrate, in which the substrate has a groove for guiding the fluid forming the underfill part in a direction away from the surface of the imaging element.

Abstract: A device for multi-spectral photo-detection in the infrared includes a photo-detection stage and a filtering stage superimposed on top of one another. The photo-detection stage includes a read circuit, an active layer incorporating a matrix of photodiodes, and a support substrate, superimposed together in that order. The filtering stage includes filtering areas of a first type, each formed of an interference filter capable of transmitting the wavelengths of a first spectral band and of blocking the wavelengths of a second spectral band, and filtering areas of a second type, capable of transmitting at least part of the wavelengths of the second spectral band. The device further includes an adhesive layer, located between the photo-detection stage and the filtering stage, on the support substrate side, and an anti-reflective coating, located between the adhesive layer and the support substrate.