Abstract: Apparatus, systems, articles of manufacture, and methods for volume adjustment are disclosed herein. An example method includes collecting data corresponding to a volume of an audio signal as the audio signal is output through a device, when an average volume of the audio signal does not satisfy a volume threshold for a specified timespan, determining a difference between the average volume and a desired volume, and applying a gain to the audio signal to adjust the volume of the audio signal to the desired volume, the gain determined based on the difference between the average volume and the desired volume.

Abstract: Volume leveler controller and controlling method are disclosed. In one embodiment, A volume leveler controller includes an audio content classifier for identifying the content type of an audio signal in real time; and an adjusting unit for adjusting a volume leveler in a continuous manner based on the content type as identified. The adjusting unit may configured to positively correlate the dynamic gain of the volume leveler with informative content types of the audio signal, and negatively correlate the dynamic gain of the volume leveler with interfering content types of the audio signal.

Abstract: A micro-mechanical resonator die includes: micro-mechanical resonator die layers; a cavity formed in at least one of the micro-mechanical resonator die layers; and a micro-mechanical resonator suspended in the cavity. The micro-mechanical resonator includes: a base; a first resonator portion extending from the base along a first plane; and a second resonator portion extending from the base along a second plane. The first resonator portion is configured to operate in an out-of-plane flexural mode that displaces at least part of the first resonator portion out of the first plane. The second resonator portion is configured to operate in an out-of-plane flexural mode that displaces at least part of the second resonator portion out of the second plane and out-of-phase relative to the first resonator portion.

Abstract: Provided are a band-pass filter circuit and a multiplexer. The band-pass filter circuit includes an electromagnetic LC filter circuit and acoustic resonance units. At least one of the acoustic resonance units each includes at least one first acoustic resonator and at least one second acoustic resonator. The first acoustic resonator is connected in series between the band-pass filter circuit and the electromagnetic LC filter circuit. Each of the at least one second acoustic resonator is connected to a terminal of the at least one first acoustic resonator, where the first terminal of the band-pass filter circuit serves as an input terminal or output terminal of the band-pass filter circuit. One or more of the acoustic resonance units are connected on an input side of the electromagnetic LC filter circuit; and the remaining of the acoustic resonance units are connected on an output side of the electromagnetic LC filter circuit.

Abstract: A noise filter includes: a ground-side power supply line detecting circuit that is connected to each of a power supply line and a power supply line and detects a power supply line connected to an electrode from among the power supply line and the power supply line; and a control circuit that determines whether the power supply line connected to the electrode is the power supply line or the power supply line on the basis of a detection result by the ground-side power supply line detecting circuit, controls a relay to short-circuit between a Y capacitor and an electrical device ground when determining that the power supply line connected to the electrode is the power supply line, and controls a relay to short-circuit between a Y capacitor and the electrical device ground when determining that the power supply line connected to the electrode is the power supply line.

Abstract: Disclosed herein is a common mode filter that includes a winding core part and first and second wires wound in a same direction around the winding core part. The first and second wires constitute a first winding block on one endmost side in an axial direction of the winding core part, a second winding block on other endmost side in the axial direction of the winding core part, and a third winding block positioned between the first and second winding blocks. The second winding block is a winding block at an odd-numbered position counted from the first winding block. The first and second wires cross each other in an area between the first and third winding blocks and in an area between the second and third winding blocks.

Abstract: A microelectromechanical resonator device is provided having two-dimensional resonant rods. The resonator device has a piezoelectric layer formed with a plurality of alternating rods and trenches. A bottom electrode is in contact with a bottom surface of the piezoelectric layer. A top electrode metal grating of conductive strips is aligned in contact with corresponding rods of the piezoelectric layer.

Abstract: A piezoelectric resonator device according to one or more embodiments may be provided, in which a crystal resonator plate includes a cutout part between a vibrating part and an external frame part, and a metal film formed on a first main surface of a first sealing member is electrically connected to an external electrode terminal formed on a second main surface, which does not face an internal space, of a second sealing member via a first internal wiring formed on an inner wall surface of the external frame part.

Abstract: Resonator devices are disclosed. An acoustic resonator device includes a piezoelectric plate having front and back surfaces, an acoustic Bragg reflector on the back surface, and an interdigital transducer (IDT) on the front surface. The acoustic Bragg reflector reflects a primary shear acoustic mode excited by the IDT in the piezoelectric plate over a frequency range including a resonance frequency and an anti-resonance frequency of the acoustic resonator device.

Abstract: A surface acoustic wave filter package comprising a tapered interdigital transducer structure.

Abstract: A surface acoustic wave resonator and a manufacturing method thereof are provided. The surface acoustic wave resonator includes a piezoelectric substrate, an interdigital transducer located on a surface of the piezoelectric substrate, and a suppression layer for suppressing a transverse mode arranged on at least one of the piezoelectric substrate and the interdigital transducer.

Abstract: A vibrator element includes a vibrator section that has a first principal surface, a second principal surface, a first side surface, and a second side surface, a support section that is disposed at a distance from the vibrator section and has a first support side surface facing the first side surface of vibrator section and a second support side surface extending in a direction that intersects with the direction in which the first support side surface extends, and a linkage section that has a first linkage surface coupled to the first side surface and the first support side surface and a second linkage surface coupled to the second side surface and the second support side surface, and the first linkage surface has a configuration in which at least one of a first section coupled to the first side surface and a second section coupled to the first support side surface has a curved surface.

Abstract: A bulk acoustic wave (BAW) device with resonance-tuned layer stack is disclosed. The BAW device includes two acoustic resonators with top electrodes in different regions on a top side of a piezoelectric layer. The BAW device includes an acoustic mirror on a bottom side of the piezoelectric layer and a bottom electrode between the acoustic mirror and the piezoelectric layer. The piezoelectric layer includes a recess in a second region on the bottom side of the piezoelectric layer. The bottom electrode is disposed in the recess on the bottom side of the piezoelectric layer. A distance between a first top electrode in a first region and the bottom electrode may be greater than a distance between a second top electrode in the second region and the bottom electrode.

Abstract: A vibrator includes a vibrator section, a support section, a linkage section, a first excitation electrode that is provided at a first principal surface, a second excitation electrode that is provided at a second principal surface and induces along with the first excitation electrode thickness-shear vibration that vibrates along a direction X, a first support electrode that is provided at the support section and electrically coupled to the first excitation electrode, a second support electrode that is provided at the support section and electrically coupled to the second excitation electrode, a first draw-out wiring line that is drawn from the first excitation electrode along a direction Z and electrically couples the first excitation electrode to the first support electrode, and a second draw-out wiring that is drawn from the second excitation electrode along the direction Z and electrically couples the second excitation electrode to the second support electrode.

Abstract: An apparatus for filtering is disclosed that implements twin double-mode surface-acoustic-wave filters with opposite polarities and a geometric offset. The apparatus includes a first double-mode surface-acoustic-wave structure comprising an electrode structure having a first quantity of fingers and a first pitch. The first double-mode surface-acoustic-wave structure has a first polarity. The apparatus also includes a second double-mode surface-acoustic-wave structure coupled to the first double-mode surface-acoustic-wave structure with a second polarity that is opposite the first polarity. The second double-mode surface-acoustic-wave structure comprises an electrode structure having a second quantity of fingers and a second pitch. The second quantity of fingers is equal to the first quantity of fingers. The second pitch differs from the first pitch by a pitch offset.

Abstract: A resonator may include two or more electrodes and one or more piezoelectric materials, where the two or more electrodes and the one or more piezoelectric materials are distributed in a direction. Further, at least one of the two or more electrodes may have a constant thickness along the direction and may include two or more regions having different densities, where the two or more regions are distributed in a plane normal to the direction and the two or more regions have the constant thickness along the direction.

Abstract: An acoustic wave device includes a first resonator, a first functional electrode provided on one of first and second main surfaces and a first dielectric film on the one of the first and second main surfaces, a second resonator sharing the piezoelectric layer with the first resonator and including a second functional electrode on one of the first and second main surfaces, a second dielectric film on the first main surface and a third dielectric film on the second main surface. The piezoelectric layer includes first and second resonator portions in which the first and second resonator are respectively provided. When thicknesses of the first resonator portion, the second resonator portion, the first dielectric film, the second dielectric film, and the third dielectric film are represented by tp1, tp2, ts1, ts2, and ts3, respectively, ts1/tp1<(ts2+ts3)/tp2 is satisfied.

Abstract: A radio frequency module includes a module substrate, a plurality of passive components disposed on a main surface of the module substrate, and a filter component disposed over the plurality of passive components, wherein the filter component includes series arm resonators that constitute an acoustic wave filter, the series arm resonator is connected between the series arm resonators, and a region of the filter component formed with the series arm resonator does not overlap the plurality of passive components and at least a part of the other region of the filter component overlaps at least a part of each of the plurality of passive components in a plan view of the module substrate.

Abstract: A multi-layer piezoelectric substrate silicon package comprises a bottom filter including a cap wafer of the bottom filter, and a device wafer of the bottom filter, the cap wafer of the bottom filter and the device wafer of the bottom filter each having a first through silicon via configured to provide an electrical path from a first bottom terminal of the device wafer of the bottom filter to a first top terminal of the cap wafer of the bottom filter.

Abstract: A method and an apparatus for coupling two nonlinear resonators via a nonlinear element to generate phononic frequency combs.

Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

Abstract: Techniques are described herein for phase modulation and interpolation that support high phase modulation resolution with high linearity. Embodiments receive a digital signal that uses a sequence of K-bit digital codes to encode a sequence of instantaneous phases for phase-modulating a local oscillator signal. A fractional divider divides a reference clock into N divided clock signals at equally spaced phase intervals and selects a pair of such signals based on first designated bits of the digital code. A fractional divider-calibrated delay line generates M delayed clock signals at equally spaced phase intervals between the selected pair of divided clock signals, and selects a pair of the delayed clock signals based on second designated bits of the digital code. A digital controlled edge interpolator generates a delayed local oscillator output signal by interpolating between the selected pair of delayed clock signals based on third designated bits of the digital code.

Abstract: The first stage of the differential interface circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first transistor and the second transistor are coupled to input terminals, respectively. The third transistor and the fourth transistor are coupled in parallel with the first transistor and the second transistor, respectively. The gate of the third transistor is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.

Abstract: A nitride semiconductor module includes a nitride semiconductor device, forming a transistor, and a control circuit. The nitride semiconductor device includes a control electrode arranged on a passivation layer between gate and drain electrodes. The control circuit generates first and second control voltages. The first control voltage, which shifts between a first voltage level and a lower second voltage level, controls a voltage applied between the gate and source electrodes. The second control voltage, which shifts between a third voltage and a lower fourth voltage level, is applied between the control and source electrodes. The control circuit generates the first and second control voltages during a turn-off operation of the transistor so that a shifting completion time of the second control voltage from the third to fourth voltage level is earlier than that of the first control voltage from the first to second voltage level.

Abstract: A controller adapted to operate a driver circuit of Bipolar Junction Transistors (BJT) such that within each ON-OFF switching cycle of the BJT, the output of the driver circuit is in the floating state for longer than it is in either the ON or OFF state. In the floating state the driver circuit is not drawing power and so power efficiency is improved. The circuit may include a bypass connection between the base and collector terminals of the BJT. The resistance of the bypass connection is selected to decay charge in the drift region whilst the transistor is ON to reduce the switching time of the BJT.

Abstract: A power limiting circuit is provided to control operation power of a power device during operation. The power limiting circuit includes a detection circuit and a control circuit. The detection circuit is coupled to the power device. The detection circuit is configured to detect a cross voltage between an input terminal and an output terminal of the power device and generate at least one detection signal associated with the detected cross voltage. The control circuit is coupled to the detection circuit and the power device. The control circuit is configured to generate a control signal based on the at least one detection signal. The control signal is provided to enable or disable the power device to control the operation power of the power device.

Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

Abstract: Methods and devices to control PCM switches are disclosed. The described devices include PCM switch drivers and logic and control circuits, all integrated with the PCM and the associated heater on the same chip. Various architectures for the driver are also presented, including architectures implement feedback mechanism to mitigate variations from process, temperature, and supply voltage.

Abstract: A switch circuit includes: first through third common terminals; a first selection terminal that can be connected to the first through third common terminals; second and third selection terminals that can be connected to the first and third common terminals via a first node and can be connected to the first and second common terminals via a second node; first through third switches connected between the first through third common terminals and the first selection terminal; fourth through fifth switches connected between the first and third common terminals and the first node; sixth and seventh switches connected between the first and second common terminals and the second node; eighth and ninth switches connected between the second and third selection terminals and the first node; and tenth and eleventh switches connected between the second and third selection terminals and the second node.

Abstract: A gate driving circuit (10X) is configured to be capable of driving a driving target transistor (QH) having a gate and a first terminal, and includes: an application terminal to which a negative voltage (VEE1) is applied; a driving transistor (MOS1) that has a control terminal fed with a control signal (MC1) and that is connected between the gate of the driving target transistor and the application terminal; and a bias switcher (101B) configured to feed the first terminal of the driving target transistor with either a ground potential (GND1) or the negative voltage selectively according to the logic level of the control signal at a timing delayed from the timing at which the control signal switches its logic level.

Abstract: A multi-stage driver circuit has a transmission line coupled to an output of the multi-stage driver circuit. The transmission line has inductive elements and programmable capacitive elements selected to shape the transmitted data signal. The programmable capacitive elements have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit.

Abstract: Apparatus and methods for multi-gate radio frequency (RF) switches are disclosed herein. The RF switches use various layout design techniques to improve figure of merit (FOM). Examples of such techniques include using only two field-effect transistors (FETs) in series to maintain shorter fingers for lower metal resistance, placing a body contact on only one side of the RF switch layout, implementing metallization with reduced coupling from input to output, and/or providing air gaps to improve high frequency performance.

Abstract: Systems and techniques that facilitate mitigating stray-coupling via multi junction qubits are provided. In various embodiments, a device can comprise a first qubit having a plurality of Josephson junctions respectively between a plurality of capacitor pads. In various aspects, the device can further comprise a plurality of second qubits respectively coupled to different ones of the plurality of capacitor pads, such that no two of the plurality of second qubits can be coupled to a same one of the plurality of capacitor pads.

Abstract: A superconducting quantum chip includes a coupler and a controller. The coupler is configured to couple a first superconducting bit circuit and a second superconducting bit circuit. A frequency response curve of the coupler includes at least one phase inversion point, and the phase inversion point includes a resonance point or a pole of the frequency response curve. The controller is configured to adjust the frequency response curve of the coupler, so that an odd quantity of phase inversion points is included between a bit frequency of the first superconducting bit circuit and a bit frequency of the second superconducting bit circuit. The controller further adjusts a frequency of the phase inversion point, so that an equivalent interaction of cross-resonance effect of the first superconducting bit circuit and the second superconducting bit circuit is zero.

Abstract: One aspect disclosed features an apparatus comprising: an input buffer configured to receive an input voltage pulse as an input, and to output, responsive to a leading edge of the input voltage pulse, a logic high voltage pulse at a first output of the input buffer and a logic low voltage pulse at a second output of the input buffer; an array of L active pull-up devices electrically coupled between a positive supply rail and an output node, each active pull-up device driven by the logic high voltage pulse as modulated by a corresponding bit of a series of N first L-bit binary words; and an array of L active pull-down devices electrically coupled between a negative supply rail and the output node, each active pull-down device driven by the logic low voltage pulse as modulated by a corresponding bit of a series of M second L-bit binary words.

Abstract: Embodiments provide an impedance calibration circuit, including: a calibration circuit configured to receive a first calibration clock signal, to perform impedance calibration on a basis of the first calibration clock signal, and to output a first stop signal when the calibration is completed; a first detection circuit configured to detect calibration time of the impedance calibration circuit, and to output a second stop signal when the calibration time reaches a preset value; and a calibration control circuit configured to receive the first stop signal and the second stop signal and to output the first calibration clock signal. When the first stop signal or the second stop signal is received, the calibration control circuit stops outputting the first calibration clock signal.

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.

Abstract: Rapid-data-transfer sensor arrays include a controller and a plurality of sensor integrated circuits (ICs) connected in series and configured to periodically take measurements and provide measurement data to the controller as serial data. A sensor IC includes a transducer, a shift register, a serial-data-in (SDI) pin, a serial-data-out (SDO) pin, a clock pin, and a bi-directional start/done (ST/DN) pin. The sensor IC includes a power regulation circuit configured to selectively supply power for a sleep mode and an active mode for recording data and an internal shift register. When finished with the measurement, the sensor IC is configured to provide measurement data to the shift register for transfer to the controller. The controller is configured to initiate serial transfer of data from each of the shift registers of the first plurality of sensor ICs to the controller. Examples include a 2D array.

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR/AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.

Abstract: In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.

Abstract: An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension.

Abstract: In some examples, a circuit includes a phase frequency detector (PFD) having a first input, a second input, and an output. The circuit also includes a control circuit having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit having an input and an output, the modulation circuit input coupled to the output of the control circuit. The circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit and the output of the oscillator coupled to the second input of the PFD.

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Abstract: A capacitor weighted segmentation buffer includes a push-pull buffer circuit and a plurality of capacitors. The capacitors include a first capacitor having a first terminal coupled to a control terminal of the first transistor and a second terminal arranged to receive a first input signal; a second capacitor having a first terminal coupled to a control terminal of the second transistor and a second terminal arranged to receive the first input signal; a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal arranged to receive a second input signal; and a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the second input signal.

Abstract: Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.