With Significant Flow Manipulation Or Condition, Other Than Merely Specifying The Components Or Their Sequence Or Both Patents (Class 117/102)
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Patent number: 8980002Abstract: Methods are disclosed for growing group III-nitride semiconductor compounds with advanced buffer layer technique. In an embodiment, a method includes providing a suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. The method includes forming an AlN buffer layer by flowing an ammonia gas into a growth zone of the processing chamber, flowing an aluminum halide containing precursor to the growth zone and at the same time flowing additional hydrogen halide or halogen gas into the growth zone of the processing chamber. The additional hydrogen halide or halogen gas that is flowed into the growth zone during buffer layer deposition suppresses homogeneous AlN particle formation. The hydrogen halide or halogen gas may continue flowing for a time period while the flow of the aluminum halide containing precursor is turned off.Type: GrantFiled: May 10, 2012Date of Patent: March 17, 2015Assignee: Applied Materials, Inc.Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
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Publication number: 20150059641Abstract: The present disclosure generally relates to systems and methods for growing group III-V nitride crystals. In particular the systems and methods include diffusing constituent species of the crystals through a porous body composed of the constituent species, where the species freely nucleate to grow large nitride crystals.Type: ApplicationFiled: September 4, 2014Publication date: March 5, 2015Inventors: Jason Schmitt, Peng Lu, Jeremy Jones
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Publication number: 20150064098Abstract: The present invention provides a process for producing a two-dimensional nanomaterial by chemical vapour deposition (CVD), the process comprising contacting a substrate in a reaction chamber with a first flow which contains hydrogen and a second flow which contains a precursor for said material, wherein the contacting takes place under conditions such that the precursor reacts in the chamber to form said material on a surface of the substrate, wherein the ratio of the flow rate of the first flow to the flow rate of the second flow is at least 5:1. Two-dimensional nanomaterials obtainable by said process are also provided, as well as devices comprising said nanomaterials.Type: ApplicationFiled: March 28, 2013Publication date: March 5, 2015Applicant: Isis Innovation LimitedInventors: Nicole Grobert, Adrian Timothy Murdock, Antal Adolf Koós
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Publication number: 20150050482Abstract: Method for synthesizing large single-crystal graphene films by suppressing evaporative substrate loss in chemical vapor deposition, and graphene films synthesized thereby. The substrate may be configured as a tube prior to exposure to an organic compound at high temperature. Low flow rate of the gaseous carbon source may be employed, and this flow rate may be increased after an initial nucleation period.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Inventors: Rodney S. Ruoff, Shanshan Chen
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Patent number: 8945302Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.Type: GrantFiled: March 4, 2012Date of Patent: February 3, 2015Assignee: Mosaic Crystals Ltd.Inventor: Moshe Einav
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Patent number: 8945304Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.Type: GrantFiled: August 13, 2008Date of Patent: February 3, 2015Assignee: The Board of Regents of the Nevada System of Higher Education on behalf of the University of Nevada, Las Vegas University of NevadaInventors: Biswajit Das, Myung B. Lee
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Patent number: 8936681Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.Type: GrantFiled: October 18, 2011Date of Patent: January 20, 2015Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Yang Wei, Shou-Shan Fan
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Publication number: 20150013595Abstract: A silicon carbide growth method for growing a silicon carbide crystal on a substrate in a hot wall reaction chamber heated to a temperature between 1600° C. and 2000° C. Process gases enter the reaction chamber utilizing at least a primary gas flow, a secondary gas flow, and a shower gas flow. The shower gas flow is fed substantially perpendicularly to the primary and secondary gas flows and is directed towards the substrate. The primary and secondary gas flows are oriented substantially parallel to the surface of the substrate. A silicon precursor gas is entered by the primary gas flow. A hydrocarbon precursor gas is entered in at least one of the primary gas flow, the secondary gas flow, or the shower gas flow. Hydrogen is entered primarily in the secondary flow and the shower head flow. A CVD reactor chamber for use in processing the method.Type: ApplicationFiled: January 29, 2013Publication date: January 15, 2015Inventors: Erik Janzén, Olof Kordina
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Publication number: 20150013594Abstract: A vapor phase growth apparatus of an embodiment includes: a reaction chamber; a first gas supply path configured to supply a first process gas including organic metal and a carrier gas into the reaction chamber; a second gas supply path configured to supply a second process gas including ammonia into the reaction chamber; a first carrier gas supply path configured to supply a first carrier gas of a hydrogen or inert gas into the first gas supply path while being connected to the first gas supply path and including a first mass flow controller; and a second carrier gas supply path configured to supply a second carrier gas of a hydrogen or inert gas different from the first carrier gas into the first gas supply path while being connected to the first gas supply path and including a second mass flow controller.Type: ApplicationFiled: July 2, 2014Publication date: January 15, 2015Applicant: NuFlare Technology, Inc.Inventors: Takumi YAMADA, Yuusuke SATO
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Publication number: 20150007766Abstract: A vapor phase growth apparatus of an embodiment includes: a reaction chamber; a gas supply path connected to an organic metal supply source at a first connection, the gas supply path being connected to a carrier gas supply source, the gas supply path supplies a process gas including organic metal and a carrier gas into the reaction chamber; a gas discharge path connected to the organic metal supply source at a second connection, the gas discharge path discharges the process gas to the outside of the apparatus; a first mass flow controller and a first adjustment device provided at the gas supply path; a second adjustment device provided at the gas discharge path; and a shortcut path connecting the gas supply path to the gas discharge path. One of the first and the second adjustment device is a back pressure regulator, and the other is a mass flow controller.Type: ApplicationFiled: July 2, 2014Publication date: January 8, 2015Applicant: NuFlare Technology, Inc.Inventors: Takumi YAMADA, Yuusuke SATO
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Publication number: 20140318442Abstract: An epitaxial reactor enabling simultaneous deposition of thin films on a multiplicity of wafers is disclosed. During deposition, a number of wafers are contained within a wafer sleeve comprising a number of wafer carrier plates spaced closely apart. Process gases flow preferentially into the interior volume of the wafer sleeve, which is heated by one or more lamp modules. To improve uniformity, the direction of process gas flow may be varied in a cross-flow configuration and the wafers may be mounted at a small angle to the plane of the wafer carrier plates, wherein the wafers are configured in pairs along the direction of gas flow and wherein along the direction of gas flow the angular mounting of the wafers provides a smaller gap between opposed wafer surfaces on said parallel wafer carrier plates in the center of said wafer sleeve than at the periphery of said wafer sleeve.Type: ApplicationFiled: March 17, 2014Publication date: October 30, 2014Applicant: Crystal Solar IncorporatedInventors: Visweswaren Sivaramakrishnan, Jean Vatus, Andrzej Kaszuba, Vicente Lim, Ashish Asthana
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Publication number: 20140318443Abstract: A silicon wafer used in manufacturing crystalline GaN for light emitting diodes (LEDs) includes a silicon substrate, a buffer layer of aluminum nitride (AlN) and an upper layer of GaN, the silicon wafer has a diameter of at least 200 millimeters and an Si(111)1×1 surface. The AlN buffer layer overlies the Si(111) surface. The GaN upper layer is disposed above the buffer layer, Across the entire wafer substantially no aluminum atoms of the AlN are present in a bottom most plane of atoms of the AlN, and across the entire wafer substantially only nitrogen atoms of the AlN are present in the bottom most plane of atoms of the AlN. A method of making the AlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber.Type: ApplicationFiled: July 7, 2014Publication date: October 30, 2014Applicant: MANUTIUS IP INC.Inventors: William E. FENWICK, Jeff RAMER
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Publication number: 20140283736Abstract: A vapor phase growth apparatus of an embodiment includes a reaction chamber, a first gas supply channel that supplies a Si source gas to the reaction chamber, a second gas supply channel that supplies a C source gas to the reaction chamber, a third gas supply channel that supplies an n-type impurity source gas to the reaction chamber, a fourth gas supply channel that supplies a p-type impurity source gas to the reaction chamber, and a control unit that controls the amounts of the n-type impurity and p-type impurity source gases at a predetermined ratio, and introduces the n-type impurity and p-type impurity source gases into the reaction chamber. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al, Ga, or In and N, and/or a combination of B and P.Type: ApplicationFiled: March 12, 2014Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Johji Nishio, Tatsuo Shimizu, Chiharu Ota, Takashi Shinohe
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Patent number: 8760584Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.Type: GrantFiled: May 14, 2013Date of Patent: June 24, 2014Assignee: MSTAR Semiconductor, Inc.Inventor: Po-Jen Yang
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Patent number: 8748785Abstract: A microwave plasma apparatus for processing a material includes a plasma chamber, a microwave radiation source, and a waveguide guiding microwave radiation from the microwave radiation source to the plasma chamber. A process gas flows through the plasma chamber and the microwave radiation couples to the process gas to produce a plasma jet. A process material is introduced to the plasma chamber, becomes entrained in the plasma jet, and is thereby transformed to a stream of product material droplets or particles. The product material droplets or particles are substantially more uniform in size, velocity, temperature, and melt state than are droplets or particles produced by prior devices.Type: GrantFiled: January 17, 2008Date of Patent: June 10, 2014Assignees: Amastan LLC, University of ConnecticutInventors: Eric Jordan, Baki M. Cetegen, Kamal Hadidi, Paul Woskov
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8715413Abstract: The invention provides a method for manufacturing a Group III nitride semiconductor crystal. The method includes the steps of preparing a seed crystal and performing a convex surface-growing step to grow the group III nitride semiconductor crystal. The growth surface of the group III nitride semiconductor crystal is constituted only by a plurality of surfaces not vertical to a growth direction and the group III nitride semiconductor crystal grows while forming a convex shape as a whole by the growth surface constituted of the plurality of surfaces. The invention also provides a method for manufacturing a group III nitride semiconductor substrate.Type: GrantFiled: June 16, 2010Date of Patent: May 6, 2014Assignee: Hitachi Cable, Ltd.Inventor: Yuichi Oshima
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Patent number: 8663389Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.Type: GrantFiled: May 21, 2011Date of Patent: March 4, 2014Inventor: Andrew Peter Clarke
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Patent number: 8652255Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.Type: GrantFiled: October 9, 2008Date of Patent: February 18, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
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Patent number: 8636844Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.Type: GrantFiled: July 6, 2012Date of Patent: January 28, 2014Assignee: Translucent, Inc.Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
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Patent number: 8617312Abstract: A method of forming (and system for forming) layers, such as calcium, barium, strontium, and/or magnesium, tantalates and/or niobates, and optionally titanates, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.Type: GrantFiled: September 14, 2006Date of Patent: December 31, 2013Assignee: Micron Technology, Inc.Inventors: Brian A. Vaartstra, Stefan Uhlenbrock
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Patent number: 8608849Abstract: A method for making zinc oxide nano-structure, the method includes the following steps. Firstly, providing a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, providing a growing substrate and forming a metal layer thereon. Thirdly, depositing a catalyst layer on the metal layer. Fourthly, placing the growing substrate into the reacting room together with a quantity of zinc source material. Fifthly, introducing a oxygen-containing gas into the reacting room. Lastly, heating the reacting room to a temperature range of 500˜1100° C.Type: GrantFiled: September 29, 2008Date of Patent: December 17, 2013Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
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Publication number: 20130327266Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: SoitecInventors: Chantal ARENA, Christiaan WERKHOVEN
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Patent number: 8603243Abstract: A method of: supplying sources of carbon and silicon into a chemical vapor deposition chamber; collecting exhaust gases from the chamber; performing mass spectrometry on the exhaust gases; and correlating a partial pressure of a carbon species in the exhaust gases to a carbon:silicon ratio in the chamber.Type: GrantFiled: July 31, 2008Date of Patent: December 10, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, Charles R. Eddy, Jr., David Kurt Gaskill
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Patent number: 8591654Abstract: A device for manufacturing a SiC single crystal includes: a raw material gas introduction pipe; a raw material gas heat chamber having a raw material gas supply passage for heating the gas in the passage; a reaction chamber having a second sidewall, an inner surface of which contacts an outer surface of a first sidewall of the heat chamber, and having a bottom, on which a SiC single crystal substrate is arranged; and a discharge pipe in a hollow center of the raw material gas heat chamber. The supply passage is disposed between an outer surface of the discharge pipe and an inner surface of the first sidewall. The discharge pipe discharges a residual gas, which is not used for crystal growth of the SiC single crystal.Type: GrantFiled: October 28, 2008Date of Patent: November 26, 2013Assignee: DENSO CORPORATIONInventors: Yasuo Kitou, Jun Kojima
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Patent number: 8568530Abstract: Precursors suitable for chemical vapor deposition, especially ALD, of hafnium oxide or zirconium oxide, have the general formula: (R1Cp)2MR2 wherein Cp represents a cyclopentadienyl ligand, R1 is H or a substituting alkyl group, alkoxy group or amido group of the Cp ligand, R2 is an alkyl group, an alkoxy group or an amido group and M is hafnium or zirconium.Type: GrantFiled: June 8, 2006Date of Patent: October 29, 2013Assignee: Sigma-Aldrich Co. LLCInventors: Peter Nicholas Heys, Paul Williams, Fuquan Song
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Patent number: 8545628Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.Type: GrantFiled: November 16, 2007Date of Patent: October 1, 2013Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 8529697Abstract: A process for growing a crystal of a nitride semiconductor in which after the step of mounting a substrate (12) in a reaction tube (11), the step of feeding a first material gas containing a Group 3 element onto the substrate in the reaction tube and the step of feeding a second material gas containing elemental nitrogen onto the substrate in the reaction tube are carried out alternately to deposit a nitride semiconductor crystal directly on the substrate. The number of moles of the elemental nitrogen contained in the second material gas has a ratio of 200 or more to the number of moles of the Group 3 element in the first material gas.Type: GrantFiled: August 31, 2005Date of Patent: September 10, 2013Assignees: Honda Motor Co., Ltd.Inventors: Hideki Hashimoto, Akihiko Horiuchi, Hideo Kawanishi
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Publication number: 20130199441Abstract: The present invention provides improved gas injectors for use with CVD (chemical vapour deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates.Type: ApplicationFiled: March 14, 2013Publication date: August 8, 2013Applicant: SOITECInventor: SOITEC
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Patent number: 8470090Abstract: Affords large-diametric-span AlN crystals, applicable to various types of semiconductor devices, with superior crystallinity, a method of growing the AlN crystals, and AlN crystal substrates. The AlN crystal growth method is a method in which an AlN crystal (4) is grown by vapor-phase epitaxy onto a seed crystal substrate (2) placed inside a crystal-growth compartment (24) within a crystal-growth vessel (12) provided within a reaction chamber, and is characterized in that during growth of the crystal, carbon-containing gas is supplied to the inside of the crystal-growth compartment (24).Type: GrantFiled: July 10, 2006Date of Patent: June 25, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Naho Mizuhara, Michimasa Miyanaga, Tomohiro Kawase, Shinsuke Fujiwara
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Patent number: 8455372Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.Type: GrantFiled: June 20, 2012Date of Patent: June 4, 2013Assignee: Fudan UniversityInventors: Qingqing Sun, Runchen Fang, Wen Yang, Pengfei Wang, Wei Zhang
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Patent number: 8449675Abstract: A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an n++ or p++ doped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n+ or p+ to the level n++ or p++, and an epitaxial layer is then deposited on this layer.Type: GrantFiled: July 28, 2008Date of Patent: May 28, 2013Assignee: Siltronic AGInventors: Rupert Krautbauer, Gerhard Huettl, Andrej Lenz, Erwin-Peter Mayer, Rainer Winkler
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Patent number: 8415546Abstract: Disclosed is a fabrication method of a metal nanoplate using metal, metal halide or a mixture thereof as a precursor. The single crystalline metal nanoplate is fabricated on a single crystalline substrate by performing heat treatment on a precursor including metal, metal halide or a mixture thereof and placed at a front portion of a reactor and the single crystalline substrate placed at a rear portion of the reactor under an inert gas flowing condition. A noble metal nanoplate of several micrometers in size can be fabricated using a vapor-phase transport process without any catalyst. The fabricated nanoplate is a single crystalline metal nanoplate having high crystallinity, high purity and not having a two-dimensional defect. Morphology and orientation of the metal nanoplate with respect to the substrate can be controlled by controlling a surface direction of the single crystalline substrate. The metal nanoplate of several micrometer size is mass-producible.Type: GrantFiled: September 22, 2009Date of Patent: April 9, 2013Assignee: Korea Advanced Institute of Science and TechnologyInventors: Bongsoo Kim, Youngdong Yoo
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Patent number: 8394197Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.Type: GrantFiled: July 11, 2008Date of Patent: March 12, 2013Assignee: Sub-One Technology, Inc.Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
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Publication number: 20130047918Abstract: Deposition systems include a reaction chamber, a substrate support structure disposed within the chamber for supporting a substrate within the reaction chamber, and a gas input system for injecting one or more precursor gases into the reaction chamber. The gas input system includes at least one precursor gas furnace disposed at least partially within the reaction chamber. Methods of depositing materials include separately flowing a first precursor gas and a second precursor gas into a reaction chamber, flowing the first precursor gas through at least one precursor gas flow path extending through at least one precursor gas furnace disposed within the reaction chamber, and, after heating the first precursor gas within the at least one precursor gas furnace, mixing the first and second precursor gases within the reaction chamber over a substrate.Type: ApplicationFiled: August 22, 2012Publication date: February 28, 2013Applicant: SOITECInventors: Ronald Thomas Bertram, JR., Michael Landis
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Patent number: 8382897Abstract: Methods for gas delivery to a process chamber are provided herein. In some embodiments, a method may include flowing a process gas through one or more gas conduits, each gas conduit having an inlet and an outlet for facilitating the flow of gas through the gas conduits and into a gas inlet funnel having a second volume, wherein each gas conduit has a first volume less than the second volume, and wherein each gas conduit has a cross-section that increases from a first cross-section proximate the inlet to a second cross-section proximate the outlet but excluding any intersection points between the gas inlet funnel and the gas conduit, and wherein the second cross-section is non-circular; and delivering the process gas to the substrate via the gas inlet funnel.Type: GrantFiled: April 25, 2012Date of Patent: February 26, 2013Assignee: Applied Materials, Inc.Inventors: Kedarnath Sangam, Anh N. Nguyen
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Publication number: 20130032084Abstract: A system for depositing thin single crystal silicon wafers by epitaxial deposition in a silicon precursor depletion mode with cross-flow deposition may include: a substrate carrier with low total heat capacity, high emissivity and small volume; a lamp module with rapid heat-up, efficient heat production, and spatial control over heating; and a manifold designed for cross-flow processing. Furthermore, the substrate carrier may include heat reflectors to control heat loss from the edges of the carrier and/or heat chokes to thermally isolate the carrier from the manifolds, allowing independent temperature control of the manifolds. The carrier and substrates may be configured for deposition on both sides of the substrates—the substrates having release layers on both sides and the carriers being configured to have equal process gas flow over both surfaces of the substrate. High volume may be addressed by a deposition system comprising multiple mini-batch reactors.Type: ApplicationFiled: May 29, 2012Publication date: February 7, 2013Applicant: Crytal Solar, IncorporatedInventors: Visweswaren Sivaramakrishnan, Tirunelveli S. Ravi, Quoc Vinh Truong, Jean R. Vatus, Visweswaren Sivaramakrishnan
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Patent number: 8361227Abstract: In a crystal growth method, an enclosed growth crucible is provided inside of a growth chamber. The growth crucible has polycrystalline source material and a seed crystal disposed in spaced relation therein. The interior of the growth crucible is heated whereupon a temperature gradient forms between the source material and the seed crystal. The temperature gradient is sufficient to cause the source material to sublimate and be transported to the seed crystal where it precipitates on the seed crystal. A gas mixture is caused to flow into the growth crucible and between the polycrystalline source material and an interior surface of the growth crucible. The gas mixture reacts with an unwanted element in the body of the growth crucible to form a gaseous byproduct which then flows through the body of the growth crucible to the exterior of the growth crucible.Type: GrantFiled: September 11, 2007Date of Patent: January 29, 2013Assignee: II-VI IncorporatedInventors: Ilya Zwieback, Thomas E. Anderson, Avinash K. Gupta
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Publication number: 20130014694Abstract: A method of growing a semiconductor epitaxial thin film and a method of fabricating a semiconductor light emitting device using the same are provided. The method of growing a semiconductor epitaxial thin film, includes: disposing a plurality of wafers loaded in a wafer holder in a reaction chamber; and jetting a reactive gas including a chlorine organic metal compound to the wafers through a gas supply unit provided to extend in a direction in which the wafers are loaded, to grow a semiconductor epitaxial thin film on a surface of each of the wafers.Type: ApplicationFiled: July 12, 2012Publication date: January 17, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Sun MAENG, Bum Joon KIM, Hyun Seok RYU, Jung Hyun LEE, Ki Sung KIM
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Patent number: 8349076Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.Type: GrantFiled: October 11, 2006Date of Patent: January 8, 2013Assignee: Samsung Corning Precision Materials Co., Ltd.Inventors: In-Jae Song, Jai-yong Han
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Patent number: 8337798Abstract: A crystal producing apparatus includes a crystal forming unit and a crystal growing unit. The crystal forming unit forms a first gallium nitride (GaN) crystal by supplying nitride gas into melt mixture containing metal sodium (Na) and metal gallium (Ga). The first GaN crystal is sliced and polished to form GaN wafers. The crystal growing unit grows a second GaN crystal on a substrate formed by using a GaN wafer, by the hydride vapor phase epitaxy method, thus producing a bulked GaN crystal.Type: GrantFiled: October 1, 2007Date of Patent: December 25, 2012Assignee: Ricoh Company, Ltd.Inventors: Seiji Sarayama, Hirokazu Iwata
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Patent number: 8334015Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.Type: GrantFiled: January 14, 2008Date of Patent: December 18, 2012Assignee: Intermolecular, Inc.Inventors: Tony P. Chiang, Sunil Shanker, Chi-I Lang
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Patent number: 8323407Abstract: The invention relates to a method and system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The method includes reacting an amount of a gaseous Group III precursor having one or more gaseous gallium precursors as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber; and supplying sufficient energy to the gaseous gallium precursor(s) prior to their reacting so that substantially all such precursors are in their monomer forms. The system includes sources of the reactants, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their component monomers.Type: GrantFiled: November 3, 2011Date of Patent: December 4, 2012Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 8293592Abstract: A semiconductor device manufacturing method including: (a) loading into a chamber a substrate having at least an exposed silicon surface and an exposed surface of silicon oxide film or silicon nitride film on a substrate surface; (b) simultaneously supplying at least a first process gas containing silicon and a second process gas for etching into the chamber when the substrate inside the chamber is heated to a predetermined temperature; and (c) supplying into the chamber a third process gas having an etchability higher than the second process gas etchability. Steps (b) and (c) are performed at least once to selectively grow an epitaxial film on the exposed silicon surface of the substrate surface. A temperature of the substrate is maintained at the predetermined temperature from (b) to (c), and the temperature of the substrate is temporarily elevated above the predetermined temperature and then returned to the predetermined temperature in (c).Type: GrantFiled: March 25, 2009Date of Patent: October 23, 2012Assignee: Hitachi Kokusai Electric Inc.Inventor: Junichi Tanabe
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Patent number: 8282733Abstract: The manufacturing method of a semiconductor apparatus has a step for carrying in the substrate into the processing chamber; a step for heating the processing chamber and the substrate to the predetermined temperature; and a gas supply and exhaust step for supplying and exhausting desired gas into and from the processing chamber, wherein the gas supply and exhaust step repeats by the predetermined times a first supply step for supplying silicon-type gas and hydrogen gas into the processing chamber; a first exhaust step for exhausting at least said silicon-type gas from the processing chamber; a second supply step for supplying chlorine gas and hydrogen gas into the processing chamber; and a second exhaust step for exhausting at least the chlorine gas from the processing chamber.Type: GrantFiled: April 1, 2008Date of Patent: October 9, 2012Assignee: Hitachi Kokusai Electric Inc.Inventor: Katsuhiko Yamamoto
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Publication number: 20120248463Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.Type: ApplicationFiled: June 15, 2012Publication date: October 4, 2012Applicant: SS SC IP, LLCInventor: Jie ZHANG
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Publication number: 20120247386Abstract: A method and apparatus for forming heterojunction stressor layers is described. A germanium precursor and a metal precursor are provided to a chamber, and an epitaxial layer of germanium-metal alloy formed on the substrate. The metal precursor is typically a metal halide, which may be provided by subliming a solid metal halide or by contacting a pure metal with a halogen gas. The precursors may be provided through a showerhead or through a side entry point, and an exhaust system coupled to the chamber may be separately heated to manage condensation of exhaust components.Type: ApplicationFiled: July 28, 2011Publication date: October 4, 2012Applicant: APPLIED MATERIALS, INC.Inventors: Errol Antonio C. Sanchez, David K. Carlson
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Publication number: 20120240845Abstract: Disclosed is a novel method wherein an aluminum nitride single crystal having good crystallinity is efficiently and easily manufactured. The method for produsing an aluminum nitride single crystal wherein nitrogen gas is circulated in the presence of a raw material gas generation source, which generates an aluminum gas or an aluminum oxide gas, and a carbon body, and then the aluminum nitride single crystal is grown under a heating condition; characterized in that, at least a part of the carbon body does not directly contact with the raw material gas generation source, at least a part of the raw material gas generation source does not directly contact with the carbon body, the raw material gas generation source and the carbon body are positioned to make a space in which a clearance between the raw material gas generation source, which does not contact with the carbon body, and the carbon body, which does not contact with the raw material gas generation source, is 0.Type: ApplicationFiled: November 29, 2010Publication date: September 27, 2012Applicants: Tohoku University, Tokuyama CorporationInventors: Hiroyuki Fukuyama, Masanobu Azuma, Kazuya Takada, Takeshi Hattori
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Patent number: 8236103Abstract: A method for producing a Group III nitride semiconductor crystal includes a first step of supplying a Group III raw material and a Group V raw material at a V/III ratio of 0 to 1,000 to form and grow a Group III nitride semiconductor on a heated substrate and a second step of vapor-phase-growing a Group III nitride semiconductor crystal on the substrate using a Group III raw material and a nitrogen raw material.Type: GrantFiled: February 14, 2003Date of Patent: August 7, 2012Assignee: Showa Denko K.K.Inventors: Hisayuki Miki, Tetsuo Sakurai, Mineo Okuyama
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Patent number: 8231728Abstract: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam of a first group V element to form a first compound semiconductor layer; a second step of stopping the irradiation of the molecular beam of the group III element and the molecular beam of the first group V element to halt growth until an amount of the first group V element supplied is reduced to 1/10 or less of a supply of the first group V element in the first step; and a third step of irradiating a molecular beam of at least one of the group III elements and a molecular beam of a second group V element to form a second compound semiconductor layer, which is different from the first compound semiconductor, on the first compound semiconductor layer.Type: GrantFiled: April 28, 2004Date of Patent: July 31, 2012Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Misao Takakusaki, Susumu Kanai