With Significant Flow Manipulation Or Condition, Other Than Merely Specifying The Components Or Their Sequence Or Both Patents (Class 117/102)
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Patent number: 8221548Abstract: A process for producing a diamond thin-film includes forming a diamond crystal thin-film on a substrate and firing the diamond crystal thin-film at a sufficient temperature under high pressure under which a diamond is stable. A diamond single-crystal substrate having a diamond single-crystal thin-film formed thereon is placed in an ultra-high-pressure and high-temperature firing furnace to anneal the diamond single-crystal thin-film under the conditions of 1200° C. and 6 GPa.Type: GrantFiled: January 31, 2008Date of Patent: July 17, 2012Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
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Patent number: 8216367Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.Type: GrantFiled: May 23, 2006Date of Patent: July 10, 2012Assignee: Showa Denko K.K.Inventor: Takashi Udagawa
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Patent number: 8216365Abstract: Objects of the invention are to further enhance crystallinity and crystallinity uniformity of a semiconductor crystal produced through the flux method, and to effectively enhance the production yield of the semiconductor crystal. The c-axis of a seed crystal including a GaN single-crystal layer is aligned in a horizontal direction (y-axis direction), one a-axis of the seed crystal is aligned in the vertical direction, and one m-axis is aligned in the x-axis direction. Thus, three contact points at which a supporting tool contacts the seed crystal are present on m-plane. The supporting tool has two supporting members, which extend in the vertical direction. One supporting member has an end part, which is inclined at 30° with respect to the horizontal plane ?. The reasons for supporting a seed crystal at m-plane thereof are that m-plane exhibits a crystal growth rate, which is lower than that of a-plane, and that desired crystal growth on c-plane is not inhibited.Type: GrantFiled: February 29, 2008Date of Patent: July 10, 2012Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Shiro Yamazaki, Takayuki Sato, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
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Patent number: 8197597Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.Type: GrantFiled: November 15, 2007Date of Patent: June 12, 2012Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Publication number: 20120138952Abstract: A composition, reactor apparatus, method, and control system for growing epitaxial layers of group III-nitride alloys. Super-atmospheric pressure is used as a process parameter to control the epitaxial layer growth where the identity of alloy layers differ within a heterostructure stack of two or more layers.Type: ApplicationFiled: August 12, 2010Publication date: June 7, 2012Applicant: GEORGIA STATE UNIVERSITY RESEARCH FOUNDATION, INC.Inventor: Nikolaus Dietz
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Patent number: 8192543Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.Type: GrantFiled: July 1, 2008Date of Patent: June 5, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
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Patent number: 8142566Abstract: A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the ratio of maximum value to minimum value (maximum value/minimum value) of the dislocation density measured by a cathode luminescence method is 10 or less, and/or (c) the lifetime measured by a time-resolved photoluminescence method is 95 ps or more.Type: GrantFiled: August 5, 2005Date of Patent: March 27, 2012Assignee: Mitsubishi Chemical CorporationInventors: Kazumasa Kiyomi, Hirobumi Nagaoka, Hirotaka Oota, Isao Fujimura
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Patent number: 8143147Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.Type: GrantFiled: February 10, 2011Date of Patent: March 27, 2012Assignee: Intermolecular, Inc.Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
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Publication number: 20110300058Abstract: The present invention relates to a method for manufacturing graphene by vapour phase epitaxy on a substrate comprising a surface of SiC, characterized in that the process of sublimation of silicon from the substrate is controlled by a flow of an inert gas or a gas other than an inert gas through the epitaxial reactor. The invention also relates to graphene obtained by this method.Type: ApplicationFiled: June 7, 2011Publication date: December 8, 2011Applicant: INSTYTUT TECHNOLOGII MATERIALOW ELEKTRONICZNYCHInventor: Wlodzimierz Strupinski
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Patent number: 8007588Abstract: A vapor phase epitaxial growth method using a vapor phase epitaxy apparatus having a chamber, a support structure holding thereon a substrate in the chamber, a first flow path supplying a reactant gas for film formation on the substrate and a second flow path for exhaust of the gas, said method includes rotating the substrate, supplying the reactant gas and a carrier gas to thereby perform vapor-phase epitaxial growth of a semiconductor film on the substrate, and during the vapor-phase epitaxial growth of the semiconductor film on the substrate, controlling process parameters to make said semiconductor film uniform in thickness, said process parameters including flow rates and concentrations of the reactant gas and the carrier gas, a degree of vacuum within said chamber, a temperature of the substrate, and a rotation speed of said substrate.Type: GrantFiled: March 20, 2007Date of Patent: August 30, 2011Assignee: NuFlare Technology, Inc.Inventors: Hideki Ito, Satoshi Inada, Yoshikazu Moriyama
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Publication number: 20110174212Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, an apparatus for processing a substrate includes a process chamber having a substrate support disposed therein to support a processing surface of a substrate at a desired position within the process chamber; a first inlet port to provide a first process gas over the processing surface of the substrate in a first direction; a second inlet port to provide a second process gas over the processing surface of the substrate in a second direction different from the first direction, wherein an azimuthal angle measured between the first direction and the second direction with respect to a central axis of the substrate support is up to about 145 degrees; and an exhaust port disposed opposite the first inlet port to exhaust the first and second process gases from the process chamber.Type: ApplicationFiled: September 22, 2010Publication date: July 21, 2011Applicant: APPLIED MATERIALS, INC.Inventors: BALASUBRAMANIAN RAMACHANDRAN, ERROL ANTONIO C. SANCHEZ, NYI O. MYO, KEVIN JOSEPH BAUTISTA, HARPREET SINGH JUNEJA, ZUOMING ZHU
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Publication number: 20110067625Abstract: A crystal growth method for forming a semiconductor film, the method includes: while revolving one or more substrates about a rotation axis, passing raw material gas and carrier gas from the rotation axis side in a direction substantially parallel to a major surface of the substrate. The center of the substrate is located on a side nearer to the rotation axis than a position at which growth rate of the semiconductor film formed by thermal decomposition of the raw material gas is maximized.Type: ApplicationFiled: November 29, 2010Publication date: March 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaaki Onomura, Yoshiyuki Harada
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Patent number: 7896965Abstract: A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite base having a substrate and a growth surface. A non-closed mask material layer is grown onto the growth surface in such a way that the mask material layer has a plurality of statistically distributed windows having varying forms and/or opening areas, a mask material being chosen in such a way that a semiconductor material of the semiconductor layer that is to be grown in a later method step essentially cannot grow on said mask material or can grow in a substantially worse manner in comparison with the growth surface. Subsequently, semiconductor layers are deposited essentially simultaneously onto regions of the growth surface that lie within the windows. A further method step is singulation of the chip composite base with applied material to form semiconductor chips.Type: GrantFiled: July 22, 2004Date of Patent: March 1, 2011Assignee: OSRAM Opto Semiconductors GmbHInventor: Volker Härle
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Patent number: 7857907Abstract: The present invention relates to a method for forming a layered structure with silicon nanocrystals. In one embodiment, the method comprises the steps of: (i) forming a first conductive layer on a substrate, (ii) forming a silicon-rich dielectric layer on the first conductive layer, and (iii) laser-annealing at least the silicon-rich dielectric layer to induce silicon-rich aggregation to form a plurality of silicon nanocrystals in the silicon-rich dielectric layer. The silicon-rich dielectric layer is one of a silicon-rich oxide film having a refractive index in the range of about 1.4 to 2.3, or a silicon-rich nitride film having a refractive index in the range of about 1.7 to 2.3. The layered structure with silicon nanocrystals in a silicon-rich dielectric layer is usable in a solar cell, a photodetector, a touch panel, a non-volatile memory device as storage node, and a liquid crystal display.Type: GrantFiled: January 25, 2007Date of Patent: December 28, 2010Assignee: AU Optronics CorporationInventors: An-Thung Cho, Chih-Wei Chao, Chia-Tien Peng, Wan-Yi Liu, Ming-Wei Sun
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Patent number: 7824492Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporisable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporised, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2, with sufficiently short reaction times.Type: GrantFiled: October 2, 2003Date of Patent: November 2, 2010Assignee: ASM International N.V.Inventors: Eva Tois, Suvi Haukka, Marko Tuominen
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Publication number: 20100272141Abstract: There is provided a nitride semiconductor freestanding substrate, with a dislocation density set to be 4×106/cm2 or less in a surface of the nitride semiconductor freestanding substrate, having an in-surface variation of directions of crystal axes along the substrate surface at each point on the substrate surface, with this variation of the directions of the crystal axes along the substrate surface set to be in a range of ±0.2° or less.Type: ApplicationFiled: October 1, 2009Publication date: October 28, 2010Applicant: HITACHI CABLE, LTD.Inventor: Hajime FUJIKURA
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Patent number: 7820244Abstract: In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.Type: GrantFiled: October 31, 2006Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hun Seo, Jin-Gi Hong, Yun-Ho Choi, Hyun-Chul Kwun, Eun-Taeck Lee, Jin-Ho Kim
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Patent number: 7815735Abstract: The invention refers to a method and apparatus for CVD coating and to a coated body. To improve the mechanical properties of the structure and surface of the body and to make the method and apparatus as simple and cost-effective as possible, it is suggested in the method, in which a layer is deposited on a substrate in a carbon-containing gas atmosphere: that the process parameters be varied during the coating period in such a way that during the coating period a first operating mode and a second operating mode are repeatedly alternated, wherein in the first operating mode a higher carbon over-saturation of the gas atmosphere occurs near the substrate, and in the second operating mode a lower carbon over-saturation of the gas atmosphere occurs near the substrate. In this way, a body can be produced with a substrate and at least one layer deposited on the surface of the substrate, wherein the layer consists of nano-crystalline diamond.Type: GrantFiled: March 22, 2004Date of Patent: October 19, 2010Assignee: Cemecon AGInventors: Dirk Breidt, Oliver Lemmer, Martin Frank
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Publication number: 20100242835Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods and equipment are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the precursor is provided at a mass flow of at least 50 g Group III element/hour for a time of at least 48 hours to facilitate high volume manufacture of the semiconductor material. Advantageously, the mass flow of the gaseous Group III precursor is controlled to deliver the desired amount.Type: ApplicationFiled: June 8, 2007Publication date: September 30, 2010Inventors: Chantal Arena, Christiaan J. Werkhoven, Thomas Andrew Steidl, Charles Michael Birtcher, Robert Daniel Clark
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Publication number: 20100233426Abstract: The present invention provides a method for fabricating a single crystalline noble metal nanowire using noble metal oxide, noble metal material or noble metal halide as a precursor and a single crystalline noble metal nanowire, and more particularly a method for fabricating a single crystalline noble metal nanowire on a single crystalline substrate by heat treating a precursor located at a front portion of a furnace and a substrate located at a rear portion of the furnace in an inert flow atmosphere and a single crystalline noble metal nanowire fabricated by the fabrication method. The present invention fabricates a single crystalline noble metal nanowire by non-catalytic vapor phase transport method, the process is simple and reproducible, the fabricated nanowire is a defect free and impurity free, high quality and high purity noble metal nanowire of complete single crystal state.Type: ApplicationFiled: June 27, 2008Publication date: September 16, 2010Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Bongsoo Kim, Yeongdong Yoo
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Patent number: 7771533Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporisable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporised, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2 with sufficiently short reaction times.Type: GrantFiled: December 4, 2000Date of Patent: August 10, 2010Assignee: ASM International N.V.Inventors: Eva Tois, Suvi Haukka, Marko Tuominen
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Patent number: 7771534Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporizable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporized, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2, with sufficiently short reaction times.Type: GrantFiled: December 22, 2006Date of Patent: August 10, 2010Assignee: ASM International N.V.Inventors: Eva Tois, Suvi Haukka, Marko Tuominen
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Patent number: 7709377Abstract: A thin film including multi components and a method of forming the thin film are provided, wherein a method according to an embodiment of the present invention, a substrate is loaded into a reaction chamber. A unit material layer is formed on the substrate. The unit material layer may be formed of a mosaic atomic layer composed of two kinds of precursors containing components constituting the thin film. The inside of the reaction chamber is purged, and the MAL is chemically changed. The method of forming the thin film of the present invention requires fewer steps than a conventional method while retaining the advantages of the conventional method, thereby allowing a superior thin film yield in the present invention than previously obtainable.Type: GrantFiled: July 8, 2005Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Dae-sig Kim, Yo-sep Min, Young-jin Cho
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Patent number: 7674335Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.Type: GrantFiled: March 9, 2006Date of Patent: March 9, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
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Patent number: 7655090Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.Type: GrantFiled: September 14, 2007Date of Patent: February 2, 2010Assignee: The Regents of the University of CaliforniaInventors: Hugues Marchand, Brendan Jude Moran
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Publication number: 20100006023Abstract: Nitride semiconductor films, such as for use in solid state light emitting devices and electronic devices, are fabricated in an environment of relatively high nitrogen potential such that nitrogen vacancies in the growing film are reduced. A reactor design, and method for its use, provide high nitrogen precursor partial pressure, precracking of the precursor using a catalytic metal surface, prepyrolyzing the precursor, using catalytically-cracked molecular nitrogen as a nitrogen precursor, and/or exposing the surface to an ambient which is extremely rich in active nitrogen species. Improved efficiency for light emitting devices, particularly in the blue and green wavelengths and improve transport properties in nitride electronic devices, i.e., improved performance from nitride-based devices such as InGaAlN laser diodes, transistors, and light emitting diodes is thereby provided.Type: ApplicationFiled: July 11, 2008Publication date: January 14, 2010Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: David P. Bour, Peter Kiesel, Christopher L. Chua, Noble M. Johnson, Zhihong Yang, John E. Northrup
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Patent number: 7608539Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.Type: GrantFiled: June 18, 2007Date of Patent: October 27, 2009Assignee: Sundew Technologies, LLCInventor: Ofer Sneh
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Publication number: 20090205563Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.Type: ApplicationFiled: November 16, 2007Publication date: August 20, 2009Applicant: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 7556688Abstract: A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth to achieve n-, i-, or p-type conductivity. In order to have growth cycles of sufficient duration, preferably an extended Ga source is used in which a portion of the Ga source is maintained at a relatively high temperature while most of the Ga source is maintained at a temperature close to, and just above, the melting temperature of Ga. To grow large boules of AlGaN, preferably multiple Al sources are used, the Al sources being sequentially activated to avoid Al source depletion and excessive degradation.Type: GrantFiled: May 20, 2005Date of Patent: July 7, 2009Assignee: Freiberger Compound Materials GmbHInventors: Yuri V. Melnik, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A. Dmitriev
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Patent number: 7553370Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.Type: GrantFiled: December 19, 2005Date of Patent: June 30, 2009Assignee: Sony CorporationInventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
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Publication number: 20090107394Abstract: A device for manufacturing a SiC single crystal includes: a raw material gas introduction pipe; a raw material gas heat chamber having a raw material gas supply passage for heating the gas in the passage; a reaction chamber having a second sidewall, an inner surface of which contacts an outer surface of a first sidewall of the heat chamber, and having a bottom, on which a SiC single crystal substrate is arranged; and a discharge pipe in a hollow center of the raw material gas heat chamber. The supply passage is disposed between an outer surface of the discharge pipe and an inner surface of the first sidewall. The discharge pipe discharges a residual gas, which is not used for crystal growth of the SiC single crystal.Type: ApplicationFiled: October 28, 2008Publication date: April 30, 2009Applicant: DENSO CORPORATIONInventors: Yasuo Kitou, Jun Kojima
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Patent number: 7488386Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.Type: GrantFiled: June 13, 2006Date of Patent: February 10, 2009Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 7481880Abstract: A method of crystallizing amorphous silicon includes forming an amorphous silicon layer on a substrate, placing a mask over the substrate including the amorphous silicon layer, and applying a laser beam onto the amorphous silicon layer through the mask to form a first crystallized region, the laser beam having an energy intensity high enough to completely melt the amorphous silicon layer, wherein the mask comprises a base substrate, a phase shift layer on the base substrate, having a plurality of first stripes having a first width separated by slits, and a blocking layer overlapping the phase shift layer, having a plurality of second stripes having a second width narrower than the first width, the second stripes being parallel to the first stripes.Type: GrantFiled: January 25, 2006Date of Patent: January 27, 2009Assignee: LG Display Co., Ltd.Inventor: Kwang-Jo Hwang
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Patent number: 7473316Abstract: What is described here is a process for the initial growth of nitrogenous semiconductor crystal materials in the form AXBYCZNVMW wherein A, B, C is an element of group II or III, N is nitrogen, M represents an element of group V or VI, and X, Y, Z, W denote the molar fraction of each element of this compound, using a, which are deposited on sapphire, SiC or Si, using various ramp functions permitting a continuous variation of the growth parameters during the initial growth.Type: GrantFiled: July 24, 2000Date of Patent: January 6, 2009Assignee: Aixtron AGInventors: Bernd Schottker, Michael Heuken, Holger Jürgensen, Gerd Strauch, Bernd Wachtendorf
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Patent number: 7465353Abstract: It is to provide a method for growing an epitaxial crystal in which the doping conditions are set when an epitaxial crystal having a desired carrier concentration is grown. A method for growing an epitaxial crystal while a dopant is added to a compound semiconductor substrate, comprises: obtaining a relation between an off angle and a doping efficiency with regards to the same type of compound semiconductor substrate in advance; and setting a doping condition for carrying out an epitaxial growth on the compound semiconductor substrate based on the obtained relation and a value of the off angle of the subtrate.Type: GrantFiled: June 6, 2005Date of Patent: December 16, 2008Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Manabu Kawabe, Ryuichi Hirano
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Publication number: 20080276860Abstract: A method and apparatus for hydride vapor phase epitaxial (HVPE) deposition is disclosed. In the HVPE process, a hydride gas flows over a metal source to react with the metal source, which then reacts at the surface of a substrate to deposit a metal nitride layer. The metal source comprises gallium, aluminum, and/or indium. The hydride gas is evenly provided over the metal source to increase efficiency of hydride-metal source reaction. An exhaust positioned diametrically across the chamber from the metal source creates a cross flow of the hydride-metal source product and nitrogen precursor across the chamber tangential to the substrate. A purge gas flowing perpendicular to the cross flow directs the hydride-metal source product and nitrogen precursor to remain as close to the substrate as possible.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: BRIAN H. BURROWS, Jacob Grayson, Nyi O. Myo, Ronald Stevens, Kenric T. Choi, Sumedh Acharya, Sandeep Nijhawan, Lori D. Washington
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Patent number: 7438760Abstract: Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.Type: GrantFiled: January 30, 2006Date of Patent: October 21, 2008Assignee: ASM America, Inc.Inventors: Matthias Bauer, Keith Doran Weeks, Pierre Tomasini, Nyles Cody
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Patent number: 7416605Abstract: An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.Type: GrantFiled: January 8, 2007Date of Patent: August 26, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Stefan Zollner, Veeraraghavan Dhandapani, Paul A. Grudowski, Gregory S. Spencer
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Patent number: 7416604Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.Type: GrantFiled: June 23, 2006Date of Patent: August 26, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
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Patent number: 7393412Abstract: A method for manufacturing a compound semiconductor epitaxial substrate with few concave defects is provided. The method for manufacturing a compound semiconductor epitaxial substrate comprises a step of epitaxially growing an InGaAs layer on an InP single crystal substrate or on an epitaxial layer lattice-matched to the InP single crystal substrate under conditions of ratio of V/: 10-100, growth temperature: 630° C.-700° C., and growth rate: 0.6 ?m/h-2 ?m/h.Type: GrantFiled: November 8, 2004Date of Patent: July 1, 2008Assignee: Sumitomo Chemical Company, LimitedInventors: Kenji Kohiro, Tomoyuki Takada
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Patent number: 7374617Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.Type: GrantFiled: April 25, 2002Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Publication number: 20080081015Abstract: A crystal producing apparatus includes a crystal forming unit and a crystal growing unit. The crystal forming unit forms a first gallium nitride (GaN) crystal by supplying nitride gas into melt mixture containing metal sodium (Na) and metal gallium (Ga). The first GaN crystal is sliced and polished to form GaN wafers. The crystal growing unit grows a second GaN crystal on a substrate formed by using a GaN wafer, by the hydride vapor phase epitaxy method, thus producing a bulked GaN crystal.Type: ApplicationFiled: October 1, 2007Publication date: April 3, 2008Inventors: Seiji Sarayama, Hirokazu Iwata
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Publication number: 20080038178Abstract: In the batch production of high purity polycrystalline silicon, in which a U-shaped silicon carrier body is fastened in an open deposition reactor, the deposition reactor is hermetically sealed, the U-shaped carrier body is heated electrical current, a silicon-containing reaction gas and hydrogen are introduced into the reactor through a supply line so that silicon from the reaction gas is deposited on the carrier body, the diameter of the carrier body increases and a waste gas formed is removed from the deposition reactor through a discharge line, and, after a desired diameter of the polysilicon rod is reached, deposition is terminated, the carrier body is cooled to room temperature, the reactor is opened, the carrier body is removed from the reactor and a second U-shaped silicon carrier body made of silicon is fastened in the deposition reactor, an inert gas is fed through the supply and discharge lines into the open reactor from at least the time when the reactor is opened to extract the first carrier bodyType: ApplicationFiled: August 6, 2007Publication date: February 14, 2008Applicant: WACKER CHEMIE AGInventors: Thomas Altmann, Hans-Peter Sendlinger, Ivo Crossmann
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Patent number: 7250083Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.Type: GrantFiled: March 7, 2003Date of Patent: July 31, 2007Assignee: Sundew Technologies, LLCInventor: Ofer Sneh
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Patent number: 7235130Abstract: An apparatus for producing diamond in a deposition chamber including a heat-sinking holder for holding a diamond and for making thermal contact with a side surface of the diamond adjacent to an edge of a growth surface of the diamond, a noncontact temperature measurement device positioned to measure temperature of the diamond across the growth surface of the diamond and a main process controller for receiving a temperature measurement from the noncontact temperature measurement device and controlling temperature of the growth surface such that all temperature gradients across the growth surface are less than 20° C.Type: GrantFiled: January 27, 2005Date of Patent: June 26, 2007Assignees: Carnegie Institution of Washington, The UAB Research FoundationInventors: Russell J. Hemley, Ho-kwang Mao, Chih-shiue Yan, Yogesh K. Vohra
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Patent number: 7229498Abstract: Nanostructures (18) and methods for production thereof by phase separation during metal organic vapor-phase epitaxy (MOVPE). An embodiment of one of the methods may comprise providing a growth surface in a reaction chamber and introducing a first mixture of precursor materials into the reaction chamber to form a buffer layer (12) thereon. A second mixture of precursor materials may be provided into the reaction chamber to form an active region (14) on the buffer layer (12), wherein the nanostructure (18) is embedded in a matrix (16) in the active region (14). Additional steps are also disclosed for preparing the nanostructure (18) product for various applications.Type: GrantFiled: October 29, 2002Date of Patent: June 12, 2007Assignee: Midwest Research InstituteInventors: Andrew G. Norman, Jerry M. Olson
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Patent number: 7217322Abstract: A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.Type: GrantFiled: September 2, 2004Date of Patent: May 15, 2007Assignee: Texas Instruments IncorporatedInventors: Jeffrey A. Babcock, Scott Balster, Alfred Haeusler, Angelo Pinto, Manfred Schiekofer, Philipp Steinmann, Badih El-Kareh
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Patent number: 7211144Abstract: A method of forming a tungsten nucleation layer using a sequential deposition process. The tungsten nucleation layer is formed by reacting pulses of a tungsten-containing precursor and a reducing gas in a process chamber to deposit tungsten on the substrate. Thereafter, reaction by-products generated from the tungsten deposition are removed from the process chamber. After the reaction by-products are removed from the process chamber, a flow of the reducing gas is provided to the process chamber to react with residual tungsten-containing precursor remaining therein. Such a deposition process forms tungsten nucleation layers having good step coverage. The sequential deposition process of reacting pulses of the tungsten-containing precursor and the reducing gas, removing reaction by-products, and than providing a flow of the reducing gas to the process chamber may be repeated until a desired thickness for the tungsten nucleation layer is formed.Type: GrantFiled: July 12, 2002Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Xinliang Lu, Ping Jian, Jong Hyun Yoo, Ken Kaung Lai, Alfred W. Mak, Robert L. Jackson, Ming Xi
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Patent number: 7153361Abstract: An opto-electronic device array is made from a multilayer epitaxial film by the following steps. The multilayer epitaxial film is separated into a plurality of segments. The segments are transferred to a first substrate to be arranged in an array substantially. Active regions are respectively confined in the segments so that the active regions form the array.Type: GrantFiled: December 23, 2003Date of Patent: December 26, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Hideto Furuyama
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Patent number: 7150789Abstract: An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.Type: GrantFiled: July 29, 2002Date of Patent: December 19, 2006Assignee: Micron Technology, Inc.Inventors: Paul J. Castovillo, Cem Basceri, Garo J. Derderian, Gurtej S. Sandhu