Using An Energy Beam Or Field, A Particle Beam Or Field, Or A Plasma (e.g., Mbe) Patents (Class 117/108)
  • Patent number: 6758900
    Abstract: A micro three-dimensional structure capable of producing a micro three-dimensional structure (micrometer-to nanometer-order outer shape) having a complicated structure, a production method therefor and production device therefor are provided. In the production method for the micro three-dimensional structure, performed are the step of irradiating a focused ion beam (4) to a sample (1) while supplying a material gas (3) to form a first-layer deposit (5), the step of releasing secondary electrons (6) from the first-layer deposit (5) hit by ions to allow the secondary electrons (6) to form a terrace (7) on the first-layer deposit (5), a step of deflecting the focused ion beam (4) in a desired direction of the terrace (7) based on a set amount from a focal position controlling apparatus, a step of forming a second-layer deposit (8) in a deflected position on the terrace (7) based on the deflection amount, and a step of repeating the above steps to form a set micro three-dimensional structure.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: July 6, 2004
    Assignee: NEC Corporation
    Inventor: Shinji Matsui
  • Patent number: 6743292
    Abstract: A thin film structure is provided including a silicon substrate with a layer of silicon dioxide on a surface thereof, and a layer of cubic oxide material deposited upon the layer of silicon dioxide by ion-beam-assisted-deposition, said layer of cubic oxide material characterized as biaxially oriented. Preferably, the cubic oxide material is yttria-stabilized zirconia. Additional thin layers of biaxially oriented ruthenium oxide or lanthanum strontium cobalt oxide are deposited upon the layer of yttria-stabilized zirconia. An intermediate layer of cerium oxide is employed between the yttria-stabilized zirconia layer and the lanthanum strontium cobalt oxide layer. Also, a layer of barium strontium titanium oxide can be upon the layer of biaxially oriented ruthenium oxide or lanthanum strontium cobalt oxide.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 1, 2004
    Assignee: The Regents of the University of California
    Inventors: Quanxi Jia, Paul N. Arendt
  • Patent number: 6720260
    Abstract: Ion-induced, UV-induced, and electron-induced sequential chemical vapor deposition (CVD) processes are disclosed where an ion flux, a flux of ultra-violet radiation, or an electron flux, respectively, is used to induce the chemical reaction in the process. The process for depositing a thin film on a substrate includes introducing a flow of a first reactant gas in vapor phase into a process chamber where the gas forms an adsorbed saturated layer on the substrate and exposing the substrate to a flux of ions, a flux of ultra-violet radiation, or a flux of electrons for inducing a chemical reaction of the adsorbed layer of the first reactant gas to form the thin film. A second reactant gas can be used to form a compound thin film. The ion-induced, UV-induced, and electron-induced sequential CVD process of the present invention can be repeated to form a thin film of the desired thickness.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 13, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: James A. Fair, Nerissa Taylor
  • Patent number: 6709989
    Abstract: A method of fabricating a semiconductor structure including the steps of: providing a silicon substrate having a surface; forming by atomic layer deposition a monocrystalline seed layer on the surface of the silicon substrate; and forming by atomic layer deposition one or more layers of a monocrystalline high dielectric constant oxide on the seed layer, where providing a substrate includes providing a substrate having formed thereon a silicon oxide, and wherein forming by atomic layer deposition a seed layer further includes depositing a layer of a metal oxide onto a surface of the silicon oxide, flushing the layer of metal oxide with an inert gas, and reacting the metal oxide and the silicon oxide to form a monocrystalline silicate.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 23, 2004
    Assignee: Motorola, Inc.
    Inventors: Jamal Ramdani, Ravindranath Droopad, Zhiyi Yu
  • Patent number: 6656573
    Abstract: Self-assembled nanowires are provided, comprising nanowires of a first crystalline composition formed on a substrate of a second crystalline composition. The two crystalline materials are characterized by an asymmetric lattice mismatch, in which in the interfacial plane between the two materials, the first material has a close lattice match (in any direction) with the second material and has a large lattice mismatch in all other major crystallographic directions with the second material. This allows the unrestricted growth of the epitaxial crystal in the first direction, but limits the width in the other.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: December 2, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yong Chen, R. Stanley Williams, Douglas A. A. Ohlberg
  • Patent number: 6638838
    Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: October 28, 2003
    Assignee: Motorola, Inc.
    Inventors: Kurt Eisenbeiser, Barbara M. Foley, Jeffrey M. Finder, Danny L. Thompson
  • Patent number: 6627268
    Abstract: Ion-induced, UV-induced, and electron-induced sequential chemical vapor deposition (CVD) processes are disclosed where an ion flux, a flux of ultra-violet radiation, or an electron flux, respectively, is used to induce the chemical reaction in the process. The process for depositing a thin film on a substrate includes introducing a flow of a first reactant gas in vapor phase into a process chamber where the gas forms an adsorbed saturated layer on the substrate and exposing the substrate to a flux of ions, a flux of ultra-violet radiation, or a flux of electrons for inducing a chemical reaction of the adsorbed layer of the first reactant gas to form the thin film. A second reactant gas can be used to form a compound thin film. The ion-induced, UV-induced, and electron-induced sequential CVD process of the present invention can be repeated to form a thin film of the desired thickness.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: September 30, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: James A. Fair, Wilbert van den Hoek, Nerissa Taylor
  • Patent number: 6623559
    Abstract: A method for producing compound semiconductor quantum particles from at least a metallic element selected from Groups IIA, IIB, IIIA, IVA, and VA of the Periodic Table and at least a non-oxygen reactant element selected from the group consisting of P, As, S, Se, and Te. The method includes: (a) operating a heating and atomizing means to provide a stream of super-heated fine-sized fluid droplets of a selected metallic element into a reaction chamber; (b) directing a stream of a reactant element-containing fluid medium into the chamber to impinge upon and react with the super-heated metal fluid droplets to form substantially nanometer-sized phosphide, arsenide, sulfide, selenide, and/or telluride compound particles; and (c) cooling and/or passivating the compound particles to form the desired compound semiconductor quantum particles. These quantum particles are particularly useful for photo luminescence and biological labeling applications.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: September 23, 2003
    Assignee: Nanotek Instruments, Inc.
    Inventor: Wen-Chiang Huang
  • Patent number: 6605151
    Abstract: Thin oxide films are deposited on substrates by metal-organic molecular beam epitaxy (MOMBE) and can be incorporated into a variety of composite materials. The composites/films are characterized by a combination of transmission electron microscopy, Auger spectrometry and atomic force microscopy. Analyzes indicate that the films directly deposited on substrates are stoichiometric and phase-pure. Carbon contamination of the films resulting from precursor decomposition was not observed.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: August 12, 2003
    Assignee: Northwestern University
    Inventors: Bruce W. Wessels, Brent H. Hoerman, Feng Niu
  • Patent number: 6602558
    Abstract: A non-linear optical silica thin film (22) whose main material is SiO2—GeO2 is formed by irradiating positive or negative polar particles and polarization orientation is carried out in the silica thin film. For example, by repeating, while forming the silica thin film (22), forming the thin film in a state of irradiating positive particles, forming the thin film in a neutral state, such as irradiation of neutral particles or non-irradiation of particles, forming the thin film in a state of irradiating negative particles, and forming the thin film in a neutral state, a plurality of regions (22-1, 22-2, and 22-3) in different states of polarization orientation are formed in a direction of film thickness of the silica thin film (22). Distribution of charges arises in the silica thin film (22) being formed by irradiation of polar particles and polarization orientation is automatically carried out in the silica thin film (22).
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: August 5, 2003
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Osamu Komeda, Hiroshi Hasegawa
  • Patent number: 6599361
    Abstract: A method is described for selectively depositing a GaN epitaxial layer on a substrate. The substrate is first patterned with a seed layer, preferably of AlN, and then the GaN epitxial layer is grown on the resulting patterned substrate by molecular beam epitaxy (MBE) such that growth occurs selectively over the seed layer.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: July 29, 2003
    Assignee: National Research Council of Canada
    Inventors: Haipeng Tang, James B. Webb, Jennifer A. Bardwell
  • Publication number: 20030131788
    Abstract: A p-type InGaAlN layer, an InGaAlN active layer, and an n-type InGaAlN layer each having a composition represented by (AlxGa1-x)yIn1-yN (0≦x≦1, 0≦y≦1) are formed on a sapphire substrate. In the as-grown state, Mg is bonded to hydrogen atoms in the p-type InGaAlN layer. Then, the back surface of the sapphire substrate is irradiated with a laser beam in a nitrogen atmosphere. The resistance of the p-type InGaAlN layer is reduced by removing hydrogen therefrom with irradiation with a weak laser beam. During the irradiation with the laser beam, the diffusion of a dopant in a multilayer portion is suppressed such that a dopant profile retains sharpness. It is also possible to separate the sapphire substrate from the multilayer portion by subsequently using an intense laser beam for irradiation.
    Type: Application
    Filed: November 13, 2002
    Publication date: July 17, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tetsuzo Ueda
  • Patent number: 6592831
    Abstract: A method and apparatus for vaporizing and cracking chemical elements for use in a deposition process. The apparatus includes a vaporization cell integrally connected with a thermal cracker cell. The vaporization cell has an inlet section in communication with a valve section defining a heating chamber capable of holding a liquid or solid chemical material to be vaporized. A heat source is positioned in the heating chamber and is capable of providing sufficient thermal energy to evaporate or sublimate the chemical material. The thermal cracker cell is communicatively connected to an outlet of the vaporization cell, and includes an elongated tapered tube with a heating element associated therewith. The heating element is capable of providing sufficient thermal energy to dissociate molecular clusters of vaporized chemical material. This provides monomeric or dimeric chemical elements for use in a deposition process such as during semiconductor device fabrication.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: July 15, 2003
    Assignee: Technology Transfer Office, The University of Utah
    Inventors: Ruey-Jen Hwu, Laurence P. Sadwick, Paul P. Lee
  • Patent number: 6579359
    Abstract: A method is disclosed for fabricating monocrystal material with the bandgap width exceeding 1.8 eV. The method comprises the steps of processing a monocrystal semiconductor wafer to develop a porous layer through electrolytic treatment of the wafer at direct current under UV-illumination, and epitaxially growing a monocrystal layer on said porous layer. Growth on porous layer produces semiconductor material with reduced stress and better characteristics than with the same material grown on non-porous layers and substrates. Also, semiconductor device structure comprising at least one layer of porous group III material is included.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: June 17, 2003
    Assignee: Technologies and Devices International, Inc.
    Inventors: Marina Mynbaeva, Denis Tsvetkov, Vladimir Dmitriev, Alexander Lebedev, Nataliya Savkina, Alexander Syrkin, Stephen Saddow, Karim Mynbaev
  • Patent number: 6569240
    Abstract: After an underlying layer, made of a single crystal metal material, has been formed on a semiconductor layer, part or all of the underlying layer is changed into a metal oxide layer by supplying oxygen thereto from above the underlying layer. Then, a ferroelectric or high-dielectric-constant film is further formed on the metal oxide layer. Since the film made of a metal material is formed on the semiconductor layer, a silicon dioxide film or the like is not formed easily. Thus, a dielectric film, which includes an underlying layer with a high dielectric constant and has a large capacitance per unit area, can be obtained. Various defects such as interface states in the semiconductor layer can also be reduced advantageously if these process steps are performed after a thermal oxide film has been formed on the semiconductor layer.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: May 27, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Nishikawa, Kenji Iijima
  • Patent number: 6569534
    Abstract: An optical material including a crystalline silicon and FexSi2 in the form of dots, islands, or a film is provided. The FexSi2 has a symmetrical monoclinic crystalline structure belonging to the P21/c space group and is synthesized at the surface or in the interior of the crystalline silicon. The monoclinic structure corresponds to a deformed structure of &bgr;-FeSi2 generated by heteroepitaxial stress between the {110} plane of the FexSi2 and the {111} plane of the crystalline silicon. The value of x is 0.85≦x≦1.1. An optical element using the optical material is also provided.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: May 27, 2003
    Assignee: Mitsubishi Materials Corporation
    Inventors: Kenji Yamaguchi, Kazuki Mizushima
  • Patent number: 6562124
    Abstract: A novel method for growing semiconductor material including GaN is disclosed. The method involves placing a first substance into a growth reactor, supplying a second gaseous substance into the grouth reactor, and applying electrical field to the second gaseous substance to produce the cry stalline compound material.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: May 13, 2003
    Assignee: Technologies and Devices International, Inc.
    Inventors: Vladimir Ivantzov, Vitaliy Sukhoveev, Vladimir Dmitriev
  • Patent number: 6527858
    Abstract: A p-type ZnO single crystal having a low resistance; and a method for producing the same providing a substrate (2) in a vacuum chamber (1), supplying to the substrate (2) atomic gases of Zn, O, and N (p-type dopant) and Ga (n-type dopant) in a manner wherein the feeds of N and Ga are controlled in such a manner that the ratio of N:Ga in a crystal is 2:1, and thereby growing a p-type ZnO single crystal containing N and Ga.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: March 4, 2003
    Assignee: Rohm Co. Ltd.
    Inventors: Hiroshi Yoshida, Tetsuya Yamamoto
  • Patent number: 6524662
    Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using of electric fields and plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer while applying an electric field to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, an electric field generating means in the chamber wherein the electric field generating means applies electric field to the substrate, and a heater at the substrate support wherein the heater supplies the substrate with heat.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: February 25, 2003
    Assignees: LG. Philips LDC Co., LTD
    Inventors: Jin Jang, Soo-Young Yoon, Jae-Young Oh, Woo-Sung Shon, Seong-Jin Park
  • Patent number: 6524651
    Abstract: A stable oxidized structure and an improved method of making such a structure, including an improved method of making an interfacial template for growing a crystalline metal oxide structure, are disclosed. The improved method comprises the steps of providing a substrate with a clean surface and depositing a metal on the surface at a high temperature under a vacuum to form a metal-substrate compound layer on the surface with a thickness of less than one monolayer. The compound layer is then oxidized by exposing the compound layer to essentially oxygen at a low partial pressure and low temperature. The method may further comprise the step of annealing the surface while under a vacuum to further stabilize the oxidized film structure. A crystalline metal oxide structure may be subsequently epitaxially grown by using the oxidized film structure as an interfacial template and depositing on the interfacial template at least one layer of a crystalline metal oxide.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: February 25, 2003
    Assignee: Battelle Memorial Institute
    Inventors: Shupan Gan, Yong Liang
  • Patent number: 6524643
    Abstract: The invention provides a method for preparing a layered structure comprising a lower thin film composed of an oxide superconductor and an upper thin film composed of a material different from the oxide superconductor on a substrate. The lower thin film is deposited by a molecular beam deposition process and the upper thin film is deposited by a process having a deposition rate faster than that of the molecular beam deposition process.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: February 25, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Publication number: 20030033976
    Abstract: Methods of growing silicon carbide are provided in which an electric arc is used to sublime a silicon carbide source material. In these embodiments, a silicon carbide seed crystal is introduced into a sublimation system, along with first and second electrodes that are separated by a gap. A power supply is coupled to at least one of the electrodes and used to create an electric arc across the gap between the two electrodes. This electric arc is used to sublime at least a portion of a silicon carbide source material. The vaporized silicon carbide material may then be encouraged to condense onto a seed material to produce monocrystalline or polycrystalline silicon carbide. In embodiments of the present invention, at least one of the electrodes is comprised of silicon carbide and serves as the silicon carbide source material.
    Type: Application
    Filed: August 16, 2001
    Publication date: February 20, 2003
    Inventor: Thomas G. Coleman
  • Patent number: 6508880
    Abstract: A low defect (e.g., dislocation and micropipe) density silicon carbide (SiC) is provided as well as an apparatus and method for growing the same. The SiC crystal, grown using sublimation techniques, is preferably divided into two stages of growth. During the first stage of growth, the crystal grows in a normal direction while simultaneously expanding laterally. Although dislocations and other material defects may propagate within the axially grown material, defect propagation and generation in the laterally grown material are substantially reduced, if not altogether eliminated. After the crystal has expanded to the desired diameter, the second stage of growth begins in which lateral growth is suppressed and normal growth is enhanced. A substantially reduced defect density is maintained within the axially grown material that is based on the laterally grown first stage material.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: January 21, 2003
    Assignee: The Fox Group, Inc.
    Inventors: Yury Alexandrovich Vodakov, Mark Grigorievich Ramm, Evgeny Nikolaevich Mokhov, Alexandr Dmitrievich Roenkov, Yury Nikolaevich Makarov, Sergei Yurievich Karpov, Mark Spiridonovich Ramm, Heikki I. Helava
  • Patent number: 6503610
    Abstract: Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Publication number: 20020170491
    Abstract: Methods for producing silicon carbide crystals, seed crystal holders and seed crystal for use in producing silicon carbide crystals and silicon carbide crystals are provided. Silicon carbide crystals are produced by forcing nucleation sites of a silicon carbide seed crystal to a predefined pattern and growing silicon carbide utilizing physical vapor transport (PVT) so as to provide selective preferential growth of silicon carbide corresponding to the predefined pattern. Seed holders and seed crystals are provided for such methods. Silicon carbide crystals having regions of higher and lower defect density are also provided.
    Type: Application
    Filed: May 21, 2001
    Publication date: November 21, 2002
    Inventor: Stephan Mueller
  • Patent number: 6475277
    Abstract: A vapor phase growth apparatus 1 for growing a group III-V nitride semiconductor (GaN) comprises a reaction ampoule 3 having a container 11 disposed therein for containing a group III element and an inlet 7 for introducing nitrogen; excitation means 15 for plasma-exciting nitrogen introduced from the inlet 7; and heating means 13 for heating a seed crystal 10 disposed within the reaction ampoule 3 and the container 11; wherein, upon growing the group III-V nitride semiconductor on the seed crystal 10, nitrogen is introduced from the inlet 7, and no gas is let out from within the reaction ampoule 3.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: November 5, 2002
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Masami Tatsumi
  • Patent number: 6475278
    Abstract: A molecular beam source comprising a crucible having an opening, and a heater mounted to the crucible for evaporating by heating a molecular beam generating material accommodated in the crucible to emit a molecular beam from the opening, wherein the crucible has an accommodating section for accommodating the molecular beam generating material, a bent portion provided between the opening and the accommodating section so that the molecular beam generating material accommodated in the accommodating section does not face the opening directly, and a narrowed portion between the bent portion and the opening.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: November 5, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takaya Nakabayashi, Shuji Makino
  • Publication number: 20020152953
    Abstract: A method of making a spinel-structured metal oxide on a substrate by molecular beam epitaxy, comprising the step of supplying activated oxygen, a first metal atom flux, and at least one other metal atom flux to the surface of the substrate, wherein the metal atom fluxes are individually controlled at the substrate so as to grow the spinel-structured metal oxide on the substrate and the metal oxide is substantially in a thermodynamically stable state during the growth of the metal oxide. A particular embodiment of the present invention encompasses a method of making a spinel-structured binary ferrite, including Co ferrite, without the need of a post-growth anneal to obtain the desired equilibrium state.
    Type: Application
    Filed: April 23, 2001
    Publication date: October 24, 2002
    Inventor: Scott A. Chambers
  • Publication number: 20020153349
    Abstract: A plasma processing method includes exhausting interior of a vacuum chamber while supplying gas into the vacuum chamber, and while controlling the interior of the vacuum chamber to a pressure, applying a high-frequency power of 100 kHz to 100 MHz to a coil provided in a vicinity of a dielectric window provided so as to face a substrate placed on a substrate electrode in the vacuum chamber, and thus generating plasma in the vacuum chamber to process the substrate or a film on the substrate by the generated plasma while particles which tend to move straight from a surface of the substrate or from a surface of the film on the substrate toward a wall surface of the dielectric window inside the vacuum chamber are kept interrupted by a metal plate.
    Type: Application
    Filed: April 3, 2002
    Publication date: October 24, 2002
    Inventors: Tomohiro Okumura, Takayuki Kai, Yoichiro Yashiro
  • Patent number: 6454855
    Abstract: The method is characterized in that layers of sufficient quality for epitaxy are placed on workpieces, at a considerably increased deposition rate. To this end, instead of a UHV-CVD or ECR-CVD method, for example, a PECVD method is used by means of a DC plasma discharge.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: September 24, 2002
    Assignee: Unaxis Trading AG
    Inventors: Hans Von Känel, Carsten Rosenblad, Jurgen Ramm
  • Patent number: 6447606
    Abstract: A method for producing a single-crystalline film made of a single crystal of lithium potassium niobate-lithium potassium tantalate solid solution or a single crystal of lithium potassium niobate, including the steps of preparing a target made of a material for the single-crystalline film, preparing a foundation made of a single crystal of lithium potassium niobate-lithium potassium tantalate solid solution or a single crystal of lithium potassium niobate, irradiating the target to gasify molecules constituting the target by dissociation and evaporation thereof, and epitaxially growing the single-crystalline film on the foundation.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: September 10, 2002
    Assignee: NGK Insulators, Ltd.
    Inventors: Minoru Imaeda, Takashi Yoshino
  • Patent number: 6428621
    Abstract: A low defect (e.g., dislocation and micropipe) density silicon carbide (SiC) is provided as well as an apparatus and method for growing the same. The SiC crystal, growing using sublimation techniques, is preferably divided into two stages of growth. During the first stage of growth, the crystal grows in a normal direction while simultaneously expanding laterally. Although dislocation and other material defects may propagate within the axially grown material, defect propagation and generation in the laterally grown material are substantially reduced, if not altogether eliminated. After the crystal has expanded to the desired diameter, the second stage of growth begins in which lateral growth is suppressed and normal growth is enhanced. A substantially reduced defect density is maintained within the axially grown material that is based on the laterally grown first stage material.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: August 6, 2002
    Assignee: The Fox Group, Inc.
    Inventors: Yury Alexandrovich Vodakov, Mark Grigorievich Ramm, Evgeny Nikolaevich Mokhov, Alexandr Dmitrievich Roenkov, Yury Nikolaevich Makarov, Sergei Yurievich Karpov, Mark Spiridonovich Ramm, Heikki I. Helava
  • Patent number: 6406539
    Abstract: A process for producing a silicon carbide single crystal and a production apparatus therefor which enable, under stable conditions, continuous production of a silicon carbide single crystal which has a reduced density and dispersion of crystal defects in a growth direction, no lattice distortion, a large diameter, and constant quality. A melted or vaporized silicon material is introduced from the outside of a reaction system into a carbon material heated to a temperature equal to or higher than a temperature at which the silicon material vaporizes; and a reaction gas containing silicon gas and silicon carbide gas generated by a reaction between the carbon material and the silicon material is caused to reach a silicon carbide seed crystal substrate 5 which is held at a temperature lower than that of the carbon material, so that a silicon carbide single crystal grows on the silicon carbide seed crystal substrate.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: June 18, 2002
    Assignee: Showa Denko K.K,
    Inventors: Masashi Shigeto, Kotaro Yano, Nobuyuki Nagato
  • Patent number: 6379472
    Abstract: The present invention comprises growing gallium nitride films in the presence of bismuth using MBE at temperatures of about 1000 K or less. The present invention further comprises the gallium nitride films fabricated using the inventive fabrication method. The inventive films may be doped with magnesium or other dopants. The gallium nitride films were grown on sapphire substrates using a hollow anode Constricted Glow Discharge nitrogen plasma source. When bismuth was used as a surfactant, two-dimensional gallium nitride crystal sizes ranging between 10 &mgr;m and 20 &mgr;m were observed. This is 20 to 40 times larger than crystal sizes observed when GaN films were grown under similar circumstances but without bismuth. It is thought that the observed increase in crystal size is due bismuth inducing an increased surface diffusion coefficient for gallium. The calculated value of 4.7×10−7 cm2/sec. reveals a virtual substrate temperature of 1258 K which is 260 degrees higher than the actual one.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: April 30, 2002
    Assignee: The Regents of the University of California
    Inventors: Christian K. Kisielowski, Michael Rubin
  • Patent number: 6372041
    Abstract: A method and apparatus for homoepitaxial growth of freestanding, single bulk crystal Gallium Nitride (GaN) are provided, wherein a step of nucleating GaN in a reactor results in a GaN nucleation layer having a thickness of a few monolayers. The nucleation layer is stabilized, and a single bulk crystal GaN is grown from gas phase reactants on the GaN nucleation layer. The reactor is formed from ultra low oxygen stainless steel.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: April 16, 2002
    Assignee: GAN Semiconductor Inc.
    Inventors: Hak Dong Cho, Sang Kyu Kang
  • Patent number: 6368983
    Abstract: The invention provides a method of fabricating a wafer including growing a single crystal layer comprising a III-V compound in a first chamber at a temperature above 350° C. A temperature of a surface of the single crystal layer is reduced to below about 350° C. in the first chamber. An indium arsenide layer is deposited on the single crystal layer, to form an intermediate structure, in the first chamber at a temperature below 350° C. and above 100° C. The intermediate structure is transferred to a second chamber. A surface of the intermediate structure is heated to a temperature above about 600° C. to remove substantially all of the indium arsenide layer and impurities collected in the indium arsenide layer during the transfer to the second chamber. Another material is deposited on the single crystal layer in the second chamber.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: April 9, 2002
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Peter S. Lyman, John J. Mosca
  • Patent number: 6368406
    Abstract: A method of making intermetallic nanoparticles comprising subjecting a starting material to laser energy so as to form a vapor and condensing the vapor so as to form intermetallic nanoparticles. The starting material can be a mixture of pure elements or an alloy of two or more elements. The nanoparticles can be provided with a narrow size distribution with an average particle size of 2 to 100 nm, preferably 2 to 50 nm and more preferably 2 to 9 nm. The nanoparticles can be formed in a vacuum chamber wherein a temperature gradient is provided. The atmosphere in the chamber can be an inert atmosphere such as argon or a reactive atmosphere such as isobutene or oxygen. An electric field can be used to form filaments of the nanoparticles.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: April 9, 2002
    Assignee: Chrysalis Technologies Incorporated
    Inventors: Seetharama C. Deevi, Yezdi B. Pithawalla, M. S. El Shall
  • Patent number: 6358822
    Abstract: A method of manufacturing a compound semiconductor is provided which can produce a mixed crystal layer with high nitrogen content without lowering the crystallinity when a III-V compound semiconductor layer including nitrogen and at least another V group element is grown by molecular beam epitaxy.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: March 19, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshitaka Tomomura
  • Publication number: 20020023581
    Abstract: A low dislocation density silicon carbide (SiC) is provided as well as an apparatus and method for growing the same. The SiC crystal, grown using sublimation techniques, is preferably divided into two stages of growth. During the first stage of growth, the crystal grows in a normal direction while simultaneously expanding laterally. Although dislocations and other material defects may propagate within the axially grown material, defect propagation and generation in the laterally grown material are substantially reduced, if not altogether eliminated. After the crystal has expanded to the desired diameter, the second stage of growth begins in which lateral growth is suppressed and normal growth is enhanced. A substantially reduced defect density is maintained within the axially grown material that is based on the laterally grown first stage material.
    Type: Application
    Filed: February 14, 2001
    Publication date: February 28, 2002
    Inventors: Yury Alexandrovich Vodakov, Mark Grigorievich Ramm, Evgency Nikolaovich Mokhov, Alexandr Dimitrievich Roenkov, Yury Nikolaevich Makarov, Sergei Yurievich Karpov, Mark Spiridonovich Ramm, Heikki I. Helava
  • Publication number: 20020020341
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 21, 2002
    Applicant: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan Jude Moran
  • Patent number: 6344084
    Abstract: A combinatorial molecular layer epitaxy apparatus is provided which includes a common chamber (22) having pressure therein controllable; one or more conveyable substrate heating units (36) having a substrate holder (48) for holding one or more substrates in the common chamber; and one or more process conducting chambers (24, 26, 28) having pressure therein controllable and provided to correspond to the substrate heating units.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: February 5, 2002
    Assignee: Japan Science and Technology Corporation
    Inventors: Hideomi Koinuma, Masashi Kawasaki
  • Publication number: 20010052573
    Abstract: A target mark member having a mark pattern with a plurality of marks and a controlled width of the marks provides accuracy and efficiency in electron beam shape measurement and focus of the electron beam. The target mark member for adjusting a focus of an electron beam and measuring a shape of said electron beam in an electron beam processing apparatus includes a metal mark portion having a predetermined mark pattern, said metal mark portion comprising an epitaxial metal material; and a substrate that supports said metal mark portion.
    Type: Application
    Filed: June 14, 2001
    Publication date: December 20, 2001
    Applicant: ADVANTEST CORPORATION
    Inventor: Masaki Takakuwa
  • Patent number: 6306212
    Abstract: An insulator layer for single crystal gallium arsenide substrates in which the insulator layer is compliantly matched with the substrate and the insulator layer is free of defects causing surface roughness and crystalline defect problems which, otherwise, could impair device performance. To accomplish this, the insulator layer is formed on a gallium arsenide substrate as an integral composite or variegated structure including (a) a uniform homogenous film of Group IIa metal atoms attached directly onto a gallium arsenide substrate surface in the form of a monolayer, and (b) a single crystal epitaxial film of a Group IIa metal fluoride deposited on the monolayer.
    Type: Grant
    Filed: August 2, 2000
    Date of Patent: October 23, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francisco Santiago, Tak Kin Chu, Michael F. Stumborg, Kevin A. Boulais
  • Publication number: 20010023660
    Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.
    Type: Application
    Filed: June 4, 2001
    Publication date: September 27, 2001
    Applicant: MOTOROLA, INC.
    Inventors: Zhiyi Yu, Ravindranath Droopad, Corey Daniel Overgaard, Jamal Ramdani, Jay A. Curless, Jerald A. Hallmark, William J. Ooms, Jun Wang
  • Patent number: 6270568
    Abstract: A method for fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12); forming an interface including a seed layer (18) adjacent to the surface (12) of the silicon substrate (10), forming a buffer layer (20) utilizing molecular oxygen; and forming one or more layers of a high dielectric constant oxide (22) on the buffer layer (20) utilizing activated oxygen.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: August 7, 2001
    Assignee: Motorola, Inc.
    Inventors: Ravindranath Droopad, Zhiyi Yu, Jamal Ramdani
  • Publication number: 20010007242
    Abstract: A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein, and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer through the mask openings, the overgrown gallium nitride layer is relatively defect free. The overgrown gallium nitride semiconductor layer may be overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The gallium nitride semiconductor layer may be grown using metalorganic vapor phase epitaxy. Microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.
    Type: Application
    Filed: February 9, 2001
    Publication date: July 12, 2001
    Inventors: Robert F. Davis, Ok-Hyun Nam, Tsvetanka Zheleva, Michael D. Bremser
  • Patent number: 6241821
    Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: June 5, 2001
    Assignee: Motorola, Inc.
    Inventors: Zhiyi Yu, Ravindranath Droopad, Corey Daniel Overgaard, Jamal Ramdani, Jay A. Curless, Jerald A. Hallmark, William J. Ooms, Jun Wang
  • Patent number: 6238482
    Abstract: A method of making a wafer is provided. A first semiconductor film is formed onto a semiconductor substrate. An epitaxial film is formed onto an epitaxial wafer. The epitaxial wafer is placed with the epitaxial film on the first semiconductor film. The epitaxial film is debonded from the EPI wafer. The epitaxial film is bonded to the first semiconductor film.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: May 29, 2001
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Kramadhati V. Ravi
  • Patent number: 6224669
    Abstract: A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: May 1, 2001
    Assignee: Motorola, Inc.
    Inventors: Zhiyi Yi, Ravindranath Droopad, Corey Daniel Overgaard, Jamal Ramdani, Jay A. Curless, Jerald A. Hallmark, William J. Ooms, Jun Wang
  • Patent number: 6206962
    Abstract: An n-type cladding layer, the first guiding layer, an active layer, the second guiding layer, a p-type cladding layer, a backing layer, a contact layer, a superlattice layer and a cap layer are stacked in this order on an n-type substrate. The cap layer comprises p-type ZnTe and has a thickness of less than 10 nm. The contact layer is comprised of p-type ZnSe and the concentration of nitrogen added to the contact layer is in the range of 1 to 2×1018 cm−3. The backing layer comprises p-type ZnSSe mixed crystal and the concentration of nitrogen added to the backing layer is higher than that of the contact layer, in the range of 1 to 3×1018 cm−3. Before the corresponding Group II-VI compound semiconductor layers are grown by the MBE method, the temperature of cells is once increased.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: March 27, 2001
    Assignee: Sony Corporation
    Inventors: Satoru Kijima, Hiroyuki Okuyama