With Pretreatment Of Substrate (e.g., Coacting Ablating) Patents (Class 117/90)
  • Patent number: 10446391
    Abstract: In various embodiments, a semiconductor device includes an aluminum nitride single-crystal substrate, a pseudomorphic strained layer disposed thereover that comprises at least one of AlN, GaN, InN, or an alloy thereof, and, disposed over the strained layer, a semiconductor layer that is lattice-mismatched to the substrate and substantially relaxed.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: October 15, 2019
    Assignee: CRYSTAL IS, INC.
    Inventors: James R. Grandusky, Leo J. Schowalter, Shawn R. Gibb, Joseph A. Smart, Shiwen Liu
  • Patent number: 10411092
    Abstract: A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mattias B. Borg, Kirsten E. Moselund, Heike E. Riel, Heinz Schmid
  • Patent number: 10269574
    Abstract: Surface treatment processes for treating a workpiece with organic radicals are provided. In one example implementation, a method for processing a workpiece having a semiconductor material and a carbon containing layer (e.g., photoresist) can include a surface treatment process on the workpiece. The surface treatment process can include generating one or more species in a first chamber (e.g., a plasma chamber). The surface treatment process can include mixing one or more hydrocarbon radicals with the species to create a mixture. The surface treatment process can include exposing the carbon containing layer to the mixture in a second chamber (e.g., a processing chamber).
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: April 23, 2019
    Assignee: MATTSON TECHNOLOGY, INC.
    Inventors: Michael X. Yang, Hua Chung, Xinliang Lu
  • Patent number: 9896780
    Abstract: Provided is a method for pretreatment of a group III nitride single crystal substrate having a high Al composition ratio, for manufacturing a high-quality group III nitride thin film. The method includes heating the base substrate at a temperature range of 1000 to 1250° C. for no less than 5 minutes under a first mixed gas atmosphere before a layer of a second group III nitride single crystal is grown, wherein the first mixed gas includes hydrogen gas and nitrogen gas; the base substrate includes a layer of a first group III nitride single crystal at least on a surface of the base substrate; the first group III nitride single crystal is represented by a composition formula of AlAGaBInCN; and the layer of the second group III nitride single crystal is to be grown on the layer of the first group III nitride single crystal.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: February 20, 2018
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Hiroshi Furuya, Toshiyuki Obata
  • Patent number: 9891521
    Abstract: Disclosed herein is a method of depositing a thin film. An exemplary embodiment of the present invention provides a method of depositing a thin film, including: a step of forming a protective layer containing silicon on a substrate; and a step of forming a sacrificial layer on the protective layer, wherein the protective layer and the sacrificial layer may include silicon (Si), and the step of forming the protective layer may include a step of supplying a precursor containing silicon and a step of supplying plasma activating a purge gas.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: February 13, 2018
    Assignee: ASM IP Holding B.V.
    Inventor: DongSeok Kang
  • Patent number: 9806264
    Abstract: A method of making N-type semiconductor layer includes following steps. An insulating substrate is provided. A semiconductor carbon nanotube layer is formed on the insulating substrate. An MgO layer is deposited on the semiconductor carbon nanotube layer. A functional dielectric layer is located on the MgO layer. A source electrode and drain electrode are formed to electrically connect the semiconductor carbon nanotube layer. A gate electrode is formed on the functional dielectric layer.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: October 31, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Guan-Hong Li, Qun-Qing Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 9768251
    Abstract: A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a dielectric layer on a surface of the substrate; forming an opening in the dielectric layer having a bottom reaching the substrate; providing a second semiconductor material in the opening and on the substrate, the second semiconductor material being en-capsulated by a further dielectric material thereby forming a filled cavity; melting the second semiconductor material in the cavity; recrystallizing the second semi-conductor material in the cavity; laterally removing the second semiconductor material at least partially for forming a lateral surface at the second semiconductor material; and forming a third semiconductor material on the lateral surface of the second semiconductor material, wherein the third semiconductor material is different from the second semiconductor material.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mattias B. Borg, Kirsten E. Moselund, Heike E. Riel, Heinz Schmid
  • Patent number: 9755022
    Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 5, 2017
    Assignees: SUMCO TECHXIV CORPORATION, SUMCO CORPORATION
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono
  • Patent number: 9711352
    Abstract: Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: July 18, 2017
    Assignee: Yale University
    Inventors: Jung Han, Jie Song, Danti Chen
  • Patent number: 9525067
    Abstract: An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: December 20, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel-Camille Bensahel, Aomar Halimaoui
  • Patent number: 9520479
    Abstract: A low-temperature epitaxial method manufactures backside field stop layer of insulated gate bipolar transistor (IGBT) first provides a first conductive type substrate and fabricates front-side elements and front metal layer on a front side of the IGBT. A second conductive type impurity layer is formed on a back side of the first conductive type substrate by low-temperature epitaxial process and a collector metal layer is formed on bottom face of the first conductive type substrate.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 13, 2016
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventors: Mei-Ling Chen, Kuan-Yu Chen
  • Patent number: 9431598
    Abstract: A simple, economical sol-gel method was invented to produce thick and dense lead zirconate titanate (PZT) thin films that exhibit the stoichiometric chemical composition and unprecedented electrical and dielectric properties. The PZT films are the foundation of many microelectromechanical systems (MEMS) and nanoelectromechanical systems (NEMS) for micro/nano sensors and actuators applications.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: August 30, 2016
    Assignee: Drexel University
    Inventors: Wei-Heng Shih, Wan Y. Shih, Zuyan Shen, Huidong Li, Xiaotong Gao
  • Patent number: 9312125
    Abstract: A cyclic deposition method for thin film formation includes forming a silicon thin film on an object by injecting a silicon precursor into a chamber in which the object is loaded, depositing silicon on the object, and performing a first purge, removing an unreacted portion of the silicon precursor and reaction by-products from the interior of the chamber, pre-processing a surface of the silicon thin film by forming a plasma atmosphere in the chamber and supplying a first reaction source having a hydrogen atom, and forming the silicon thin film as an insulating film including silicon, by forming the plasma atmosphere in the chamber and supplying a second reaction source having one or more oxygen atoms, one or more nitrogen atoms, or a mixture thereof.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 12, 2016
    Assignee: Eugene Technology Co., Ltd.
    Inventors: Hai-Won Kim, Seok-Yun Kim, Chang-Hun Shin, Jeong-Hoon Lee
  • Patent number: 9200366
    Abstract: Methods of making polycrystalline monolithic magnesium aluminate spinels are disclosed. The polycrystalline monolithic magnesium aluminate spinels have small grain sizes and may be deposited on substrates as thick one-piece deposits. The polycrystalline monolithic magnesium aluminate spinels may be prepared and deposited by chemical vapor deposition using magnesium and aluminum gaseous precursors.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 1, 2015
    Inventors: Jitendra S. Goela, Heather A. G. Stern
  • Patent number: 9194044
    Abstract: A deposition apparatus 50 includes a chamber 1 having at its top section a gas inlet 4 for supplying deposition gas 25. Inside chamber 1 is a susceptor 7 on which to place a substrate 6; a heater 8 located below the substrate 6; and a liner 2 for covering the inner walls of the chamber 1. Apparatus 50 deposits a film on the substrate 6 by supplying deposition gas 25 from gas inlet 4 into chamber 1 while heating substrate 6. An upper electric resistance heater cluster 35 is located between the inner walls of the chamber 1 and liner 2 such that the upper heater 35 surrounds the liner 2. The upper heater 35 is divided vertically into electric resistance heaters 36, 37, and 38 which are independently temperature-controlled. The substrate 6 is heated with the use of both heater 8 and the upper heater cluster 35.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: November 24, 2015
    Assignees: NuFlare Technology, Inc., Central Research Institute of Electric Power Industry, Denso Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Kunihiko Suzuki, Shinichi Mitani
  • Patent number: 9175417
    Abstract: The invention provides a method for manufacturing a nitride semiconductor substrate capable of reducing a cleavage during slicing of the nitride semiconductor single crystal and capable of improving a yield rate of the nitride semiconductor substrate. The method includes growing a nitride semiconductor single crystal on a seed crystal substrate by vapor phase epitaxy; grinding an outer peripheral surface the grown nitride semiconductor single crystal; and slicing the nitride semiconductor single crystal with its outer peripheral surface ground. A grinding amount of the outer peripheral surface of the nitride semiconductor single crystal in the step of grinding is 1.5 mm or more.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 3, 2015
    Assignee: SCIOCS COMPANY LIMITED
    Inventor: Hajime Fujikura
  • Patent number: 9165694
    Abstract: Aspects of the present disclosure are directed to apparatuses and methods involving nanowires having junctions therebetween. As consistent with one or more embodiments, an apparatus includes first and second sets of nanowires, in which the second set overlaps the first set. The apparatus further includes a plurality of nanowire joining recrystallization junctions, each junction including material from a nanowire of the first set that is recrystallized into an overlapping nanowire of the second set.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: October 20, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Erik C. Garnett, Mark L. Brongersma, Yi Cui, Michael D. McGehee, Mark Greyson Christoforo, Wenshan Cai
  • Patent number: 9157169
    Abstract: A method for fabricating a III-nitride semiconductor body that includes high temperature and low temperature growth steps.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: October 13, 2015
    Assignee: International Rectifier Corporation
    Inventors: Paul Bridger, Robert Beach
  • Patent number: 9142723
    Abstract: A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 22, 2015
    Assignee: Intellec Limited
    Inventors: Colin Humphreys, Clifford McAleese, Menno Kappers, Zhenyu Liu, Dandan Zhu
  • Patent number: 9054268
    Abstract: A method for manufacturing an absorber layer of thin film solar cells is revealed. Firstly vapors of different metal-organic sources are generated in a plurality of containers used for mounting different metal-organic sources. Then the vapors of the metal-organic sources are mixed with a carrier gas and are filled into a reaction together with a reaction gas chamber through pipelines. Next the metals and the compounds are deposited on a substrate in the reaction chamber to form an absorber layer of a thin film solar cell. A flow rate of each metalorganic vapors filled into the reaction chamber is controlled by a mass flow controller respectively.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 9, 2015
    Assignee: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Hwen-Fen Hong, Hou-Ying Huang, Hwa-Yuh Shin
  • Patent number: 9039834
    Abstract: Non-polar (11 20) a-plane gallium nitride (GaN) films with planar surfaces are grown on (1 102) r-plane sapphire substrates by employing a low temperature nucleation layer as a buffer layer prior to a high temperature growth of the non-polar (11 20) a-plane GaN thin films.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: May 26, 2015
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, James Stephen Speck
  • Patent number: 9023673
    Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Ostendo Technologies, Inc.
    Inventors: Lisa Shapovalov, Oleg Kovalenkov, Vladimir Ivantsov, Vitali Soukhoveev, Alexander Syrkin, Alexander Usikov
  • Patent number: 9023306
    Abstract: The invention relates to a single crystal boron doped CVD diamond that has a toughness of at least about 22 MPa m1/2. The invention further relates to a method of manufacturing single crystal boron doped CVD diamond. The growth rate of the diamond can be from about 20-100 ?m/h.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: May 5, 2015
    Assignee: Carnegie Institution of Washington
    Inventors: Russell J. Hemley, Ho-Kwang Mao, Chih-Shiue Yan, Qi Liang
  • Patent number: 9005362
    Abstract: The present invention is to provide a method for growing a group III nitride crystal that has a large size and has a small number of pits formed in the main surface of the crystal by using a plurality of tile substrates. A method for growing a group III nitride crystal includes a step of preparing a plurality of tile substrates 10 including main surfaces 10m having a shape of a triangle or a convex quadrangle that allows two-dimensional close packing of the plurality of tile substrates; a step of arranging the plurality of tile substrates 10 so as to be two-dimensionally closely packed such that, at any point across which vertexes of the plurality of tile substrates 10 oppose one another, 3 or less of the vertexes oppose one another; and a step of growing a group III nitride crystal 20 on the main surfaces 10m of the plurality of tile substrates arranged.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 14, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuki Hiromura, Koji Uematsu, Hiroaki Yoshida, Shinsuke Fujiwara
  • Patent number: 8999058
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 7, 2015
    Assignee: Solexel, Inc.
    Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Patent number: 8980003
    Abstract: In a method of manufacturing a silicon carbide single crystal, a silicon carbide substrate having a surface of one of a (11-2n) plane and a (1-10n) plane, where n is any integer number greater than or equal to 0, is prepared. An epitaxial layer having a predetermined impurity concentration is grown on the one of the (11-2n) plane and the (1-10n) plane of the silicon carbide substrate by a chemical vapor deposition method so that a threading dislocation is discharged from a side surface of the epitaxial layer. A silicon carbide single crystal is grown into a bulk shape by a sublimation method on the one of the (11-2n) plane and the (1-10n) plane of the epitaxial layer from which the threading dislocation is discharged.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: March 17, 2015
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Watanabe, Yasuo Kitou, Masami Naito
  • Patent number: 8961687
    Abstract: Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InxGayAl1-x-yN alloy. The lattice parameter of the InxGayAl1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a?)=?2(a) or (a?)=(a)/?2. The semiconductor alloy may be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 24, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Patent number: 8956453
    Abstract: The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H2 flux or hydrogen originating from dissociation of GeH4 and/or to a non-reactive gas source such as N2, He, Ne, Ar, Kr, Xe, Rn or mixtures thereof, and crystallizing the amorphous germanium layer by annealing the base substrate so as to provide a crystalline germanium layer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 17, 2015
    Assignees: IMEC, Vrije Universiteit Brussel
    Inventors: Ruben Lieten, Stefan Degroote
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8945304
    Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 3, 2015
    Assignee: The Board of Regents of the Nevada System of Higher Education on behalf of the University of Nevada, Las Vegas University of Nevada
    Inventors: Biswajit Das, Myung B. Lee
  • Publication number: 20150028286
    Abstract: A bulk manufacturing method for growing silicon-germanium stained-layer superlattice (SLS) using an ultra-high vacuum-chemical vapor deposition (UHV-CVD) system and a detector using it is disclosed. The growth method overcomes the stress caused by silicon and germanium lattice mismatch, and leads to uniform, defect-free layer-by-layer growth. Flushing hydrogen between the layer growths creates abrupt junctions between superlattice structure (SLS) layers. Steps include flowing a mixture of phosphine and germane gases over a germanium seed layer. This in-situ doped germanium growth step produces an n-doped germanium layer. Some of the phosphorus diffuses into the underlying germanium and reduces the stress in the underlying germanium that is initially created by the lattice mismatch between germanium and silicon. Phosphine can be replaced by diborane if a p-doped layer is desired. The reduction of stress results in a smooth bulk germanium growth.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 29, 2015
    Inventors: Vu Anh Vu, Sandra L. Hyland, Robert L. Kamocsai, Daniel J. O'Donnell, Andrew T. Pomerene
  • Patent number: 8940614
    Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 27, 2015
    Assignee: Dow Corning Corporation
    Inventors: Mark J. Loboda, Jie Zhang
  • Patent number: 8940266
    Abstract: The present invention provides a method for producing a large substrate of single-crystal diamond, including the steps of preparing a plurality of single-crystal diamond layers separated form an identical parent substrate, placing the single-crystal diamond layers in a mosaic pattern on a flat support, and growing a single-crystal diamond by a vapor-phase synthesis method on faces of the single-crystal diamond layers where they have been separated from the parent substrate. According to the method of the invention, a mosaic single-crystal diamond having a large area and good quality can be produced relatively easily.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 27, 2015
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hideaki Yamada, Akiyoshi Chayahara, Yoshiaki Mokuno, Shinichi Shikata
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8932403
    Abstract: A method for forming a surface-textured single-crystal film layer by growing the film atop a layer of microparticles on a substrate and subsequently selectively etching away the microparticles to release the surface-textured single-crystal film layer from the substrate. This method is applicable to a very wide variety of substrates and films. In some embodiments, the film is an epitaxial film that has been grown in crystallographic alignment with respect to a crystalline substrate.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sandia Corporation
    Inventors: Qiming Li, George T. Wang
  • Patent number: 8920560
    Abstract: A method for manufacturing an epitaxial wafer includes: a step of pulling a single crystal from a boron-doped silicon melt in a chamber based on a Czochralski process; and a step of forming an epitaxial layer on a surface of a silicon wafer sliced from the single crystal. The single crystal is allowed to grow while passed through a temperature region of 800 to 600° C. in the chamber in 250 to 180 minutes during the pulling step. The grown single crystal has an oxygen concentration of 10×1017 to 12×1017 atoms/cm3 and a resistivity of 0.03 to 0.01 ?cm. The silicon wafer is subjected to pre-annealing prior to the step of forming the epitaxial layer on the surface of the silicon wafer, for 10 minutes to 4 hours at a predetermined temperature within a temperature region of 650 to 900° C. in an inert gas atmosphere. The method is to fabricate an epitaxial wafer that has a diameter of 300 mm or more, and that attains a high IG effect, and involves few epitaxial defects.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: December 30, 2014
    Assignee: Sumco Corporation
    Inventors: Yasuo Koike, Toshiaki Ono, Naoki Ikeda, Tomokazu Katano
  • Patent number: 8906159
    Abstract: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 9, 2014
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 8888913
    Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: November 18, 2014
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
  • Patent number: 8888914
    Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tokuaki Nihashi, Masatomo Sumiya, Minoru Hagino, Shunro Fuke
  • Publication number: 20140327013
    Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 6, 2014
    Applicants: SOITEC, OMMIC, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
    Inventors: David Schenk, Alexis Bavard, Yvon Cordier, Eric Frayssinet, Mark Kennard, Daniel Rondi
  • Patent number: 8852341
    Abstract: The present invention discloses methods to produce large quantities of polycrystalline GaN for use in the ammonothermal growth of group III-nitride material. High production rates of GaN can be produced in a hydride vapor phase growth system. One drawback to enhanced polycrystalline growth is the increased incorporation of impurities, such as oxygen. A new reactor design using non-oxide material that reduces impurity concentrations is disclosed. Purification of remaining source material after an ammonothermal growth is also disclosed. The methods described produce sufficient quantities of polycrystalline GaN source material for the ammonothermal growth of group III-nitride material.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: October 7, 2014
    Assignee: Sixpoint Materials, Inc.
    Inventors: Edward Letts, Tadao Hashimoto, Masanori Ikari
  • Patent number: 8852343
    Abstract: Apparatus for vapor phase growing of crystals having a single multi-zone heater arranged to heat a heated zone to give a predetermined temperature profile along the length of the heated zone. A generally U-shaped tube having a first limb, a second limb, and a linkage connecting the first and second limbs is located on the heated zone. The first limb contains a source material. The second limb supports a seed such that the source material and seed are spaced longitudinally within the heated zone to provide a predetermined temperature differential between the source and seed. The crystal is grown on the seed.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: October 7, 2014
    Assignee: Kromek Limited
    Inventors: Arnab Basu, Ben Cantwell, Max Robinson
  • Patent number: 8853064
    Abstract: The present invention is directed to a method of manufacturing a substrate, which includes loading a base substrate into a reaction furnace; forming a buffer layer on the base substrate; forming a separation layer on the buffer layer; forming a semiconductor layer on the separation layer at least two; and separating the semiconductor layer from the base substrate via the separation layer through natural cooling by unloading the base substrate from the reaction furnace.
    Type: Grant
    Filed: October 21, 2012
    Date of Patent: October 7, 2014
    Assignee: Lumigntech Co., Ltd.
    Inventors: Hae Yong Lee, Young Jun Choi, Jin Hun Kim, Hyun soo Jang, Hea Kon Oh, Hyun Hee Hwang
  • Publication number: 20140264348
    Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.
    Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
  • Publication number: 20140251203
    Abstract: A selective epitaxial growth method includes preparing a target object including a single crystal substrate in which an epitaxial growth region is partitioned by a suppression film; and growing the epitaxial layer on the epitaxial growth region of the target object until a predetermined film thickness is obtained. The growing the epitaxial layer includes first source gas supply process of supplying a source gas onto the target object under a first pressure to grow a first epitaxial layer on the epitaxial growth region, first removing process of removing deposits on the suppression film, second source gas supply process of supplying the source gas onto the target object under a second pressure higher than the first pressure, and second removing process of removing the deposits on the suppression film. The second source gas supply process and the second removing process are repeated until the predetermined film thickness is obtained.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Daisuke SUZUKI, Akinobu KAKIMOTO, Satoshi ONODERA
  • Publication number: 20140255705
    Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.
    Type: Application
    Filed: January 30, 2014
    Publication date: September 11, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Neeraj Nepal, Virginia D. Wheeler, Charles R. Eddy, JR., Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Rachael L. Myers-Ward, Sandra C. Hangarter
  • Patent number: 8828140
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Publication number: 20140231830
    Abstract: Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga2O3 substrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure including: a Ga2O3 substrate; a buffer layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal on the Ga2O3 substrate; and a nitride semiconductor layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal including oxygen as an impurity on the buffer layer. The oxygen concentration in a region having a thickness of no less than 200 nm on the nitride semiconductor layer on the side towards the Ga2O3 substrate is no less than 1.0×1018/cm3.
    Type: Application
    Filed: October 12, 2012
    Publication date: August 21, 2014
    Applicants: Tamura Corporation, Koha Co., Ltd.
    Inventors: Kazuyuki Iizuka, Yoshikatsu Morishima, Shinkuro Sato
  • Patent number: 8795431
    Abstract: A gallium nitride layer is produced using a seed crystal substrate by flux method. The seed crystal substrate 8A includes a supporting body 1, a plurality of seed crystal layers 4A each comprising gallium nitride single crystal and separated from one another, a low temperature buffer layer 2 provided between the seed crystal layers 4A and the supporting body and made of a nitride of a group III metal element, and an exposed layer 3 exposed to spaces between the adjacent seed crystal layers 4A and made of aluminum nitride single crystal or aluminum gallium nitride single crystal. The gallium nitride layer is grown on the seed crystal layers by flux method.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: August 5, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Katsuhiro Imai, Makota Iwai, Takanao Shimodaira, Masahiro Sakai, Shuhei Higashihara, Takayuki Hirao
  • Patent number: 8790461
    Abstract: The invention provides a method for manufacturing the silicon carbide single crystal wafer capable of improving the utilization ratio of the bulk silicon carbide single crystal, capable of improving characteristics of the element and capable of improving cleavability, and the silicon carbide single crystal wafer obtained by the manufacturing method. An ?(hexagonal)-silicon carbide single crystal wafer which has a flat homoepitaxial growth surface with a surface roughness of 2 nm or less and which has an off-angle from the (0001)c plane of 0.4° or less.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: July 29, 2014
    Assignee: Showa Denko K.K.
    Inventors: Takayuki Maruyama, Toshimi Chiba