With Pretreatment Of Substrate (e.g., Coacting Ablating) Patents (Class 117/90)
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Patent number: 6723165Abstract: A method for fabricating a Group III nitride semiconductor substrate according to the present invention includes the steps of: (a) preparing a substrate; (b) forming, on the substrate, a first semiconductor layer composed of a Group III nitride semiconductor; (c) forming, on the first semiconductor layer, a heat diffusion suppressing layer lower in thermal conductivity than the first semiconductor layer; (d) forming, on the heat diffusion suppressing layer, a second semiconductor layer composed of a Group III nitride semiconductor; and (e) irradiating the first semiconductor layer through the substrate with a light beam transmitted by the substrate and absorbed by the first semiconductor layer to decompose the first semiconductor layer.Type: GrantFiled: April 10, 2002Date of Patent: April 20, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Ogawa, Masahiro Ishida, Satoshi Tamura, Shinichi Takigawa
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Patent number: 6723164Abstract: The present invention provides a method for stabilizing an oxide-semiconductor interface, which is free from the formation of an interface layer (reactive layer) between a semiconductor and an interface oxide and which thereby allows satisfactory exhibition of performance capabilities of a functional oxide and achievement of the stability of oxide-semiconductor interface, yet independent of temperature; it also provides a stabilized semiconductor.Type: GrantFiled: September 24, 2002Date of Patent: April 20, 2004Assignees: Japan Science and Technology Corporation, National Institute for Materials ScienceInventors: Toyohiro Chikyo, Mamoru Yoshimoto
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Patent number: 6719841Abstract: A method of fabricating a high-density magnetic data-storage medium, the method comprising the steps of: (a) forming a plurality of nanodots of non-magnetic material in a regular array on a surface of a substrate, said array being notionally dividable into a plurality of clusters that each comprise a plurality of nanodots, wherein each nanodot of a said cluster overlaps with neighbouring nanodots of that cluster to form a well between them; (b) depositing magnetic material onto said substrate to at least partly fill the wells of each cluster; and (c) removing material to reveal a regular array of wells filled with magnetic material, each of said wells being separated from neighbouring wells by non-magnetic material.Type: GrantFiled: May 9, 2002Date of Patent: April 13, 2004Assignee: Data Storage InstituteInventors: Yunjie Chen, Jian-Ping Wang
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Patent number: 6709513Abstract: In a process for producing a substrate for use in a semiconductor element: a porous anodic alumina film having a great number of minute pores is formed on a surface of a base substrate; the surface of the base substrate is etched by using the porous anodic alumina film as a mask so as to form a great number of pits on the surface of the base substrate; the porous anodic alumina film is removed; and a GaN layer is formed on the surface of the base substrate by crystal growth.Type: GrantFiled: July 3, 2002Date of Patent: March 23, 2004Assignee: Fuji Photo Film Co., Ltd.Inventors: Toshiaki Fukunaga, Toshiaki Kuniyasu, Mitsugu Wada, Yoshinori Hotta
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Patent number: 6709512Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.Type: GrantFiled: August 29, 2001Date of Patent: March 23, 2004Assignee: Sony CorporationInventors: Hisayoshi Yamoto, Hideo Yamanaka
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Patent number: 6695913Abstract: A light-emitting diode or laser diode comprises a sapphire substrate and, grown on the substrate, a GaN buffer layer, an n-doped GaN contact layer, an n-doped (AlGa)N cladding layer, a Zn-doped (InGa)N active layer, a p-doped (AlGa)N cladding layer and a p-doped GaN contact layer. Graded layers are introduced at the interfaces between the cladding layers and both the contact layers and the active layer. The constituency of each graded layer is graded from one side to the other of the layer such that the layer is lattice matched with the adjacent layer on each side with the result that the strain at the interfaces between the layers is reduced and the possibility of deleterious dislocations being introduced at the interfaces is minimised. By removing or reducing such dislocations, the efficiency of the operation of the device is increased.Type: GrantFiled: February 8, 2000Date of Patent: February 24, 2004Assignee: Sharp Kabushiki KaishaInventor: Geoffrey Duggan
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Patent number: 6673149Abstract: A method for the production of a crack-free epitiaxial film having a thickness greater than that which can be achieved by continuous epitaxial crystal growth. This epitaxial film can be used as is in a device, used as a substrate platform for further epitaxy, or separated from the initial substrate material and used as a free-standing substrate platform. The method utilizes a defect-rich initial layer that absorbs epitaxially derived stresses and another layer, which is not defect-rich, which planarizes the crystal growth front, if necessary and provides high quality epitaxial region near the surface.Type: GrantFiled: September 6, 2000Date of Patent: January 6, 2004Assignees: Matsushita Electric Industrial Co., LTD, CBL Technologies, Inc.Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
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Patent number: 6666916Abstract: A mandrel for use in a diamond deposition process has surfaces with different diamond adhesion properties. According to one embodiment, a mandrel is provided and has first and second surfaces on which a diamond film is deposited, with the second surface forming a perimeter around the first surface. The first surface of the mandrel has a first diamond bonding strength which is less than a second diamond bonding strength of the second surface. In an embodiment for forming a cup-shaped diamond film, the mandrel is a titanium nitride (TiN) coated molybdenum (Mo) substrate having a stepped solid cylindrical shape with a central mesa having a side wall or flank. The side wall is etched near the top surface of the mesa to expose a molybdenum band and to form a second surface which bounds the TiN first surface.Type: GrantFiled: October 18, 2002Date of Patent: December 23, 2003Assignee: Saint-Gobain/Norton Industrial Ceramics CorporationInventors: Randy D. Fellbaum, Volker R. Ulbrich
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Patent number: 6652648Abstract: A method for fabricating a gallium nitride single crystal substrate is provided. The method involves: forming a GaN layer on the front side of a sapphire substrate; heating the sapphire substrate at a temperature of 600-1,000° C.; and separating the GaN layer from the sapphire substrate by radiating a laser onto the back side of the sapphire substrate. Before or after forming the GaN layer on the front side of the sapphire substrate, a silicon oxide layer may be formed on the back side of the sapphire substrate. In this case, the silicon oxide layer is removed from the back side of the sapphire substrate in a subsequent process. A high-quality GaN substrate having no crack is attained by the method.Type: GrantFiled: April 25, 2001Date of Patent: November 25, 2003Assignee: Samsung Corning Co., Ltd.Inventor: Sung-soo Park
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Patent number: 6649494Abstract: A protector film is formed on the surface of a substrate to cover at least the side surface thereof. Then, a compound semiconductor film including nitrogen is grown through epitaxial growth on the substrate at an exposed portion. Then, the substrate and the compound semiconductor film are separated from each other by irradiation of laser light, polishing of the substrate, etching, cutting, etc. Consequently, the resulting compound semiconductor film is used as a free-standing wafer.Type: GrantFiled: January 25, 2002Date of Patent: November 18, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoshi Tamura, Masahiro Ogawa, Masahiro Ishida, Masaaki Yuri
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Patent number: 6645819Abstract: One embodiment of the present invention provides a method of fabricating a semiconductor device including the steps of forming a first semiconductor layer; forming a second semiconductor layer over the first semiconductor layer; forming a mask over a first portion the second semiconductor layer; removing a second portion of the second semiconductor layer not covered by the mask; forming a first electrical connector on the first semiconductor layer; and forming a second electrical connector on the first portion of the second semiconductor layer.Type: GrantFiled: October 19, 2001Date of Patent: November 11, 2003Assignee: GTRAN, Inc.Inventor: Rajashekhar Pullela
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Patent number: 6630023Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing treatment of a substrate and then depositing the film. The treatment step creates nucleation and growth sites on the substrate for the film deposition process and promotes election emission of the deposited film. With this process, a patterned emission can be achieved without post-deposition processing of the film. A field emitter device can be manufactured with such a film.Type: GrantFiled: January 4, 2001Date of Patent: October 7, 2003Assignee: SI Diamond Technology, Inc.Inventors: Zhidan Li Tolt, Zvi Yaniv, Richard Lee Fink
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Patent number: 6630024Abstract: A method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front, includes the following process steps: (a) preparing a substrate wafer having a polished front and a specific thickness; (b) pretreating the front of the substrate wafer in the presence of HCl gas and a silane source at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor, the thickness of the substrate wafer remaining substantially unchanged; and (c) depositing the epitaxial layer on the front of the pretreated substrate wafer.Type: GrantFiled: May 24, 2001Date of Patent: October 7, 2003Assignee: Wacker Siltronic Gesellschaft für Halbleitermaterialien AGInventors: Rüdiger Schmolke, Reinhard Schauer, Günther Obermeier, Dieter Gräf, Peter Storck, Klaus Messmann, Wolfgang Siebert
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Patent number: 6620238Abstract: A nitride semiconductor structure includes: a substrate having a growth surface, a convex portion and a concave portion being formed on the growth surface; and a nitride semiconductor film grown on the growth surface. A cavity is formed between the nitride semiconductor film and the substrate in the concave portion.Type: GrantFiled: October 2, 2001Date of Patent: September 16, 2003Assignee: Sharp Kabushiki KaishaInventors: Yuhzoh Tsuda, Takayuki Yuasa
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Patent number: 6620710Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.Type: GrantFiled: September 18, 2000Date of Patent: September 16, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: Theodore I. Kamins
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Patent number: 6617235Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. A first embodiment is directed to a method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller by volume.Type: GrantFiled: March 29, 1996Date of Patent: September 9, 2003Assignee: Sumitomo Chemical Company, LimitedInventors: Yasushi Iyechika, Yoshinobu Ono, Tomoyuki Takada
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Patent number: 6569238Abstract: An apparatus for depositing a semiconductor film on a wafer, which is held on a holder inside a reactor, with at least one source gas supplied onto the wafer. The apparatus includes a decontamination film made of a semiconductor that contains at least one constituent element of the semiconductor film to be deposited. The decontamination film covers inner walls of the reactor, which are located upstream with respect to the source gas supplied and/or over the holder.Type: GrantFiled: May 25, 2001Date of Patent: May 27, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masahiro Ishida
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Patent number: 6530991Abstract: A method for the formation of a semiconductor layer by which a defect density of structural defects, particularly a dislocation density of threading dislocations in the resulting semiconductor layer can be remarkably reduced, so that hours of work can be shortened as well as a manufacturing cost can be reduced without requiring any complicated process comprises supplying a structural defect suppressing material for suppressing structural defects in the semiconductor layer onto a surface of the layer of a material from which the semiconductor layer is to be formed.Type: GrantFiled: December 13, 2000Date of Patent: March 11, 2003Assignees: RikenInventors: Satoru Tanaka, Misaichi Takeuchi, Yoshinobu Aoyagi
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Patent number: 6530990Abstract: A susceptor is disclosed for minimizing or eliminating thermal gradients that affect a substrate wafer during epitaxial growth. The susceptor comprises a first susceptor portion including a surface for receiving a semiconductor substrate wafer thereon, and a second susceptor portion facing the substrate-receiving surface and spaced from the substrate-receiving surface. The spacing is sufficiently large to permit the flow of gases therebetween for epitaxial growth on a substrate on the surface, while small enough for the second susceptor portion to heat the exposed face of a substrate to substantially the same temperature as the first susceptor portion heats the face of a substrate that is in direct contact with the substrate-receiving surface.Type: GrantFiled: February 21, 2001Date of Patent: March 11, 2003Assignee: Cree, Inc.Inventors: Hua-Shuang Kong, Calvin Carter, Jr., Joseph Sumakeris
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Patent number: 6488767Abstract: A high quality wafer comprising AlxGayInzN, wherein 0<y≦1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 &mgr;m2 area at its Ga-side. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality AlxGayInzN wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefully employed to highlight crystal defects on the Ga-side of the AlxGayInzN wafer.Type: GrantFiled: June 8, 2001Date of Patent: December 3, 2002Assignee: Advanced Technology Materials, Inc.Inventors: Xueping Xu, Robert P. Vaudo
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Publication number: 20020174828Abstract: A process for manufacturing silicon wafers that reduces the size of silicon wafer surface and/or sub-surface defects without the forming excessive haze. The process entails cleaning the front surface of the silicon wafer at a temperature of at least about 1100 ° C. by exposing the front surface to a cleaning ambient comprising H2, HF gas, or HCl gas to remove silicon oxide from the front surface and exposing the cleaned front surface of the silicon wafer at a temperature of at least about 1100 ° C. to a vacuum or an annealing ambient consisting essentially of a mono-atomic noble gas selected from the group consisting of He, Ne, Ar, Kr, and Xe to facilitate the migration of silicon atoms to the exposed agglomerated defects without substantially etching silicon from the front surface of the heated silicon wafer.Type: ApplicationFiled: March 29, 2002Publication date: November 28, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Jiri L. Vasat, Andrei Stefanescu, Thomas A. Torack, Gregory M. Wilson
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Publication number: 20020157601Abstract: A polycrystalline thin film of MgO is formed on a substrate by an ion sputtering process wherein the thin film is obtained by irradiating a target with an ion beam to dislodge particles from the target and deposit the particles on the substrate. The film is preferably formed in an atmosphere at a reduced pressure of 3.0×10−2 Pa or lower while keeping the substrate temperature at 300° C. or lower.Type: ApplicationFiled: October 6, 2001Publication date: October 31, 2002Inventors: Yasuhiro Iijima, Mariko Kimura, Takashi Saito
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Patent number: 6464780Abstract: The invention relates to a method for the production of a monocrystalline layer on a substrate with a non-adapted lattice. To this end, a monocrystalline substrate with a buried amply defective layer and a monocrystalline layer produce thereon are used. The buried amply defective layer can be produced by hydrogen implantation.Type: GrantFiled: August 29, 2000Date of Patent: October 15, 2002Assignee: Forschungszentrum Julich GmbHInventors: Siegfried Mantl, Bernhard Holländer, Ralf Liedtke
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Publication number: 20020144645Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.Type: ApplicationFiled: December 13, 2001Publication date: October 10, 2002Inventors: Andrew Y. Kim, Eugene A. Fitzgerald
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Patent number: 6458205Abstract: By forming a silicon single-crystal thin film direct on a chemically etched substrate, a time required for all the process can be effectively shortened, which largely contributes to reduction in production cost of a silicon epitaxial wafer and improvement on production efficiency thereof, with the result that a reduced wafer price at a user's end and a short delivery time are ensured. In a technical aspect, an etching removal in a chemical etching treatment is set to be 60 &mgr;m or more and thereby, a glossiness of a front main surface of a chemically etched substrate can be ensured to be 95% or higher. With such a glossiness of the front main surface of the substrate employed, a surface glossiness of a silicon single-crystal thin film formed on the front main surface of the chemically etched substrate can be increased to 95% or higher, thereby, enabling an auto-alignment treatment in a lithographic step coming later with no trouble.Type: GrantFiled: December 19, 2000Date of Patent: October 1, 2002Assignees: Shin-Etsu Handotai Co., Ltd., Naoetsudenshikogyo-KabushikigaishaInventors: Koichi Hasegawa, Yuji Okubo
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Patent number: 6458206Abstract: AFM/STM probes are based on whiskers grown by the vapor-liquid-solid (VLS) mechanism. Silicon cantilevers oriented along the crystallographic plane (111) are prepared from silicon-on-insulator structures that contain a thin layer (111) on a (100) substrate with SiO2 interposed layer. At removal of solidified alloy globules inherent in the growth mechanism sharpening of the whiskers takes place and, in such a way, the probes are formed. Cross-sections of the wiskers grown by the mechanism on the cantilevers can be controllably changed during the growth process so that step-shaped whiskers optimal for fabrication of the probes can be prepared. Also, whiskers with expansions/contractions can be formed that are important for fabrication of probes suitable for investigations in coarse surfaces, complicated cavitites, grooves typical for semiconductor microelectronics, etc.Type: GrantFiled: March 9, 2001Date of Patent: October 1, 2002Assignee: Crystals and Technologies, Ltd.Inventors: Evgeny Invievich Givargizov, Lidiya Nikolaevna Obolenskaya, Ala Nikolaevna Stepanova, Evgeniya Sergeevna Mashkova, Michail Evgenievich Givargizov
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Patent number: 6454854Abstract: It is an object of the invention to provide a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity on a main surface of a semiconductor single crystal substrate of 300 mm or more in diameter. When a process gas is supplied to over a main surface of a silicon single crystal substrate 12 in rotation in almost parallel to the main surface thereof in one direction in a reaction chamber 10 through six inlet ports 18a to 18f disposed in width direction of the reaction chamber 10, H2 gas, a semiconductor raw material gas and a dopant gas are supplied onto an area in the vicinity of the center of the main surface of the silicon single crystal substrate 12 and an intermediate area thereof through the inner inlet ports 18a and 18b and the middle inlet ports 18c and 18d, and only H2 gas and the semiconductor raw material gas without the dopant gas are supplied onto an area in the vicinity of the outer periphery thereof from the outer inlet ports 18e and 18f.Type: GrantFiled: June 26, 2000Date of Patent: September 24, 2002Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Hiroki Ose
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Patent number: 6428619Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.Type: GrantFiled: October 23, 2000Date of Patent: August 6, 2002Assignee: Mitsubishi Materials Silicon CorporationInventors: Hiroshi Koya, Hisashi Furuya, Yoji Suzuki, Yukio Muroi, Takaaki Shiota
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Patent number: 6426320Abstract: A method for fabricating superconductor articles with an epitaxial layer is described. The method can be performed under conditions of relatively high pressure and low substrate surface temperature. The resulting epitaxial layers can demonstrate various advantageous features, including low pore density and/or inclusions with small average particle size diameter.Type: GrantFiled: December 29, 1999Date of Patent: July 30, 2002Assignee: American Superconductors CorporationInventors: Leslie G. Fritzemeier, David M. Buczek
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Patent number: 6419742Abstract: A method of forming lattice matched single crystal wide bandgap II-VI compound semiconductor films over a silicon substrate includes first cleaning (10) the silicon substrate. A passivation layer is formed (18), which may comprise arsenic, germanium, or CaF2, among others. The lattice matched layer is then grown (26) on the passivation layer.Type: GrantFiled: November 15, 1994Date of Patent: July 16, 2002Assignees: Texas Instruments Incorporated, Texas A&M University SystemInventors: Wiley P. Kirk, Joe X. Zhou, Bruce E. Gnade, Chih-Chen Cho
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Patent number: 6406981Abstract: A method of coupling a single crystal semiconductor layer on a surface of a substrate comprising a polycrystalline semiconductor material such that the single crystal layer and the polycrystalline material are in direct contact.Type: GrantFiled: June 30, 2000Date of Patent: June 18, 2002Assignee: Intel CorporationInventor: Kramadhati V. Ravi
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Patent number: 6395085Abstract: A method of manufacturing a high-purity epitaxial silicon wafer is provided. The method includes providing a quartz crucible for melting silicon; adding silicon to the crucible; heating the crucible to form a melt; applying an electrical potential across the crucible; pulling a silicon crystal from the melt; forming a silicon wafer from the silicon crystal, the wafer having a frontside and a backside; and simultaneously depositing an epitaxial first silicon film on the frontside of the wafer and a polycrystalline second silicon film on the backside of the wafer.Type: GrantFiled: January 11, 2001Date of Patent: May 28, 2002Assignee: SEH America, Inc.Inventors: Gerald R. Dietze, Sean G. Hanna, Zbigniew J. Radzimski
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Publication number: 20020045340Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. [1] A method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller in capacity.Type: ApplicationFiled: March 29, 1996Publication date: April 18, 2002Inventors: YASUSHI IYECHIKA, YOSHINOBU ONO, TOMOYUKI TAKADA
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Publication number: 20020038626Abstract: A method of crystallizing an amorphous silicon layer includes the steps of generating an excimer laser beam having a first energy density and a second energy density, irradiating an amorphous silicon layer with at least one exposure of the excimer, wherein the first energy density melts the amorphous silicon layer to a first depth from a surface of the amorphous silicon layer equal to the first thickness and the second energy density melts the amorphous silicon layer to a second depth from the surface of the amorphous silicon layer less than the first thickness.Type: ApplicationFiled: October 1, 2001Publication date: April 4, 2002Applicant: LG.PHILIPS LCD CO., LTD.Inventor: Se-Jin Chung
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Patent number: 6337220Abstract: An ion implanter vacuum integrity check process and apparatus that enables a vacuum integrity check at a pressure substantially below the ion implantation process pressure, while storing an ion implantation process pressure set point for a subsequent ion implantation process. An ion implanter includes an end station chamber, a high vacuum system, a disk, a gas supply system and a controller for storing at least a vacuum integrity check pressure set point and an ion implantation process pressure set point. A disk inserted into the end station is accelerated to a predetermined rotational speed, while the high vacuum system is used to pump down the end station chamber. The end station chamber is, then, purged with an inert gas for a first predetermined time period, while maintaining the disk rotational speed and continuing to pump down the end station chamber. The pressure of the end station chamber is monitored, while the disk rotational speed and pumping of the chamber are maintained.Type: GrantFiled: February 28, 2001Date of Patent: January 8, 2002Assignee: Fairchild Semiconductor CorporationInventors: Donald L. Wilcox, Randy M. Underwood
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Patent number: 6331209Abstract: An easy method of forming purified carbon nanotubes from which graphitic phase or carbon particles are removed, using a high-density plasma. Carbon nanotubes are grown on a substrate using a plasma chemical vapor deposition method at a high plasma density of 1011 cm−3 or more. The carbon nanotube formation includes: growing a carbon nanotube layer on a substrate to have a predetermined thickness by plasma deposition; purifying the carbon nanotube layer by plasma etching; and repeating the growth and the purification of the carbon nanotube layer. For the plasma etching, a halogen-containing gas, for example, a carbon tetrafluoride gas, is used as a source gas.Type: GrantFiled: April 21, 2000Date of Patent: December 18, 2001Assignees: Iljin Nanotech Co., Ltd.Inventors: Jin Jang, Suk-jae Chung
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Publication number: 20010039917Abstract: A surface roughness distribution in the surface of a silicon epitaxial wafer is made uniform by optimizing a temperature distribution in the surface of a susceptor used in a vapor phase thin film growth apparatus. The susceptor is not supported by its center of the rear surface thereof, but only the peripheral portion thereof is supported using vertical pins respectively provided at the far ends of spokes radially branched from a rotary shaft. The susceptor is constituted so that a difference in temperature between the maximum and minimum in the surface of a silicon wafer is suppressed to a value equal to or less than 7° C. Hence, a surface roughness distribution in the surface of the silicon epitaxial wafer can be suppressed to a value equal to or less than 0.02 ppm.Type: ApplicationFiled: July 10, 2001Publication date: November 15, 2001Applicant: Shin-Etsu Handotai, Co., Ltd.Inventors: Takeshi Arai, Tadaaki Honma, Hitoshi Habuka
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Publication number: 20010032581Abstract: This invention is directed to a novel a single crystal silicon wafer. In one embodiment, this wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.Type: ApplicationFiled: May 16, 2001Publication date: October 25, 2001Inventors: Gregory M. Wilson, Jon A. Rossi, Charles C. Yang
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Patent number: 6294018Abstract: The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.Type: GrantFiled: September 15, 1999Date of Patent: September 25, 2001Assignee: Lucent TechnologiesInventors: Robert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
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Patent number: 6280523Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.Type: GrantFiled: February 5, 1999Date of Patent: August 28, 2001Assignee: LumiLeds Lighting, U.S., LLCInventors: Carrie Carter Coman, Fred A. Kish, Jr., R. Scott Kern, Michael R. Krames, Paul S. Martin
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Patent number: 6217651Abstract: In the process of thin film growth, actual temperature of a substrate is measured and corrected with low cost in short time. With first thin film growth equipment of which a difference between set temperature of a heating source and an actual temperature of the substrate (hereinafter, referred to as temperature characteristic) is known, a first calibration curve representing “thin film growth rate vs. substrate actual temperature” is prepared. Next, thin film growth is conducted at one set temperature T2 with use of second thin film growth equipment whose temperature characteristic is unknown, where a difference from a set temperature T1 reading from the first calibration curve in correspondence to a thin film growth rate G resulting from the thin film growth process is determined.Type: GrantFiled: July 16, 1999Date of Patent: April 17, 2001Assignee: Shin-Etsu Handotai, Co., Ltd.Inventors: Hisashi Kashino, Koichi Kanaya
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Patent number: 6168659Abstract: With an object of providing gallium nitride thick film crystals excelling in crystallization, the structure thereof is formed of an amorphous silicon dioxide thin film 2 formed on a silicon substrate 1 and then a single crystal silicon thin film 3 is formed on the foregoing amorphous silicon dioxide thin film 2 and further gallium nitride 4 is formed on this silicon thin film 3.Type: GrantFiled: April 9, 1998Date of Patent: January 2, 2001Assignee: Matsushita Electronics CorporationInventors: Masaaki Yuri, Tetsuzo Ueda, Takaaki Baba
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Patent number: 6146457Abstract: A method for producing thick, high quality GaN substrates uses an epitaxially deposited film is used as a substrate material for further device or epitaxial processing. The film is deposited using an epitaxial technique on a thin substrate called the disposable substrate. The deposited film is thick enough so that upon cooling the thermal mismatched strain is relieved through cracking of the lower disposable substrate and not the newly deposited epitaxy. The epitaxial film now becomes a platform for either further epitaxial deposition or device processing.Type: GrantFiled: July 2, 1998Date of Patent: November 14, 2000Assignee: CBL Technologies, Inc.Inventor: Glenn S. Solomon
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Patent number: 6123767Abstract: A liquid raw material is heated to its boiling point or higher at a vaporizer to mix the vaporized ingredient gas and a carrier gas at a mixer at predetermined concentrations. The flow of the mixed gas is adjusted while the mixed gas is heated to over its condensing point and the temperature thereof is kept. Subsequently, the mixed gas is fed to a reactor for epitaxial growth while the mixed gas is heated to over its condensing point and the temperature thereof is kept. When the temperature of a heating medium is kept constant at the vaporizer to vaporize the liquid raw material and the feeding amount of the liquid into the vaporizer is adjusted by the pressure of the gas inside the vaporizer, the liquid surface level can be controlled to be constant.Type: GrantFiled: May 21, 1999Date of Patent: September 26, 2000Assignees: Mitsubishi Materials Silicon Corporation, Mitsubishi Materials Polycrystalline Silicon CorporationInventors: Yoshiharu Toyama, Akikazu Kuroda, Tokuji Kiyama, Sumio Kida, Shunji Yoshida, Takashi Yamamoto, Tetsuya Atsumi
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Patent number: 6117233Abstract: Thin, single-crystal SiC films are obtained by means of a pyrolysis process, the substrate to be coated being covered with a carbonaceous polysilane, the adhering layer being pyrolyzed in an inert atmosphere and the amorphous layer of SiC obtained in this way being crystallized by maintaining it at a temperature of over 700.degree. C. Using a special variation of the process, it is easy to form doped SiC films. To this end the dopant is added in the form of a silane compound.Type: GrantFiled: August 6, 1997Date of Patent: September 12, 2000Assignee: Max-Planck-Gesellschaft zur Forderung DEInventors: Joachim Bill, Frederick F. Lange, Thomas Wagner, Fritz Aldinger, Detlef Heimann
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Patent number: 6107197Abstract: A method of removing a carbon-contaminated layer from a silicon substrate surface before a silicon epitaxial growth on the silicon substrate surface. A carbon-contaminated layer on the silicon substrate is exposed to a chlorine radical to cause a chemical reaction of the chlorine radical with carbon atoms of the carbon-contaminated layer to generate chlorine carbide to form chlorine carbide for removal of the carbon-contaminated layer from the silicon substrate surface, wherein the chlorine radical has been generated by passing a chlorine gas through a heating filament so that the chlorine radical is generated at a much higher generation efficiency than when the chlorine radical were generated by using a deep ultraviolet ray.Type: GrantFiled: January 10, 1997Date of Patent: August 22, 2000Assignee: NEC CorporationInventor: Tatsuya Suzuki
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Patent number: 6086673Abstract: Provided is a method for producing a nitride layer on a growth substrate. First a pretreatment layer is formed on the growth substrate, and then the formed pretreatment layer is exposed to a gaseous environment that is thermochemically reactive with the pretreatment layer. After gaseous environment exposure of the pretreatment layer, there is carried out an epitaxial growing process to produce on the substrate a nitride layer material defined as In.sub.x Ga.sub.y Al.sub.1-x-y N, where 0.ltoreq.x.ltoreq.1; 0.ltoreq.y.ltoreq.1; and 0.ltoreq.x+y.ltoreq.1. For example, a pretreatment layer of ZnO can be deposited on a sapphire growth substrate and then subjected to a gaseous environment, e.g., including HCl- and/or NH.sub.3 -containing gas, that is thermochemically reactive with the ZnO. Then an epitaxial layer of GaN can be grown by a hydride vapor phase epitaxial process on the pretreated substrate.Type: GrantFiled: April 2, 1998Date of Patent: July 11, 2000Assignee: Massachusetts Institute of TechnologyInventor: Richard J. Molnar
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Patent number: 6048398Abstract: In a method for epitaxially growing objects of SiC, a Group III-nitride or alloys thereof on a substrate (13) received in a susceptor (7) having circumferential walls (8) these walls and by that the substrate and a source material (24) for the growth are heated above a temperature level from which sublimation of the material grown starts to increase considerably. The carrier gas flow is fed into the susceptor towards the substrate for carrying said source material to the substrate for said growth. At least a part of said source material for said growth is added to the carrier gas flow upstream the susceptor (7) and carried by the carrier gas flow to the susceptor in one of a) a solid state and b) a liquid state for being brought to a vapor state in a container comprising said susceptor by said heating and carried in a vapor state to said substrate for said growth.Type: GrantFiled: October 16, 1995Date of Patent: April 11, 2000Assignees: ABB Research Ltd., Okmetic Ltd.Inventors: Asko Erkki Vehanen, Rositza Todorova Yakimova, Marko Tuominen, Olle Kordina, Christer Hallin, Erik Janzen
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Patent number: 6028020Abstract: A single crystal quartz thin film having a thickness of 5 nm to 50 .mu.m can be prepared by forming the thin film on a single crystal substrate by a sol-gel process and peeling the thin film from the substrate. The present invention can provide the single crystal quartz thin film at a low price without a large and complex apparatus.Type: GrantFiled: December 5, 1995Date of Patent: February 22, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventors: Motoyuki Tanaka, Takahiro Imai, Naoji Fujimori
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Patent number: 6022832Abstract: A method for fabricating superconductor articles with an epitaxial layer is described. The method can be performed under conditions of relatively high pressure and low substrate surface temperature. The resulting epitaxial layers can demonstrate various advantageous features, including low pore density and/or inclusions with small average particle size diameter.Type: GrantFiled: January 15, 1998Date of Patent: February 8, 2000Assignee: American Superconductor CorporationInventors: Leslie G. Fritzemeier, David M. Buczek