With Pretreatment Of Substrate (e.g., Coacting Ablating) Patents (Class 117/90)
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Publication number: 20140255705Abstract: A method of growing crystalline materials on two-dimensional inert materials comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material. A crystalline material grown on a two-dimensional inert material made from the process comprising functionalizing a surface of a two-dimensional inert material, growing a nucleation layer on the functionalized surface, and growing a crystalline material.Type: ApplicationFiled: January 30, 2014Publication date: September 11, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Neeraj Nepal, Virginia D. Wheeler, Charles R. Eddy, JR., Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Rachael L. Myers-Ward, Sandra C. Hangarter
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Patent number: 8828140Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.Type: GrantFiled: July 3, 2013Date of Patent: September 9, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
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Publication number: 20140231830Abstract: Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga2O3 substrate, and a method for manufacturing the same. In one embodiment, there is provided a crystal layered structure including: a Ga2O3 substrate; a buffer layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal on the Ga2O3 substrate; and a nitride semiconductor layer comprising an AlxGayInzN (0?x?1, 0?y?1, 0?z?1, x+y+z=1) crystal including oxygen as an impurity on the buffer layer. The oxygen concentration in a region having a thickness of no less than 200 nm on the nitride semiconductor layer on the side towards the Ga2O3 substrate is no less than 1.0×1018/cm3.Type: ApplicationFiled: October 12, 2012Publication date: August 21, 2014Applicants: Tamura Corporation, Koha Co., Ltd.Inventors: Kazuyuki Iizuka, Yoshikatsu Morishima, Shinkuro Sato
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Patent number: 8795431Abstract: A gallium nitride layer is produced using a seed crystal substrate by flux method. The seed crystal substrate 8A includes a supporting body 1, a plurality of seed crystal layers 4A each comprising gallium nitride single crystal and separated from one another, a low temperature buffer layer 2 provided between the seed crystal layers 4A and the supporting body and made of a nitride of a group III metal element, and an exposed layer 3 exposed to spaces between the adjacent seed crystal layers 4A and made of aluminum nitride single crystal or aluminum gallium nitride single crystal. The gallium nitride layer is grown on the seed crystal layers by flux method.Type: GrantFiled: September 20, 2013Date of Patent: August 5, 2014Assignee: NGK Insulators, Ltd.Inventors: Katsuhiro Imai, Makota Iwai, Takanao Shimodaira, Masahiro Sakai, Shuhei Higashihara, Takayuki Hirao
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Patent number: 8790461Abstract: The invention provides a method for manufacturing the silicon carbide single crystal wafer capable of improving the utilization ratio of the bulk silicon carbide single crystal, capable of improving characteristics of the element and capable of improving cleavability, and the silicon carbide single crystal wafer obtained by the manufacturing method. An ?(hexagonal)-silicon carbide single crystal wafer which has a flat homoepitaxial growth surface with a surface roughness of 2 nm or less and which has an off-angle from the (0001)c plane of 0.4° or less.Type: GrantFiled: August 24, 2005Date of Patent: July 29, 2014Assignee: Showa Denko K.K.Inventors: Takayuki Maruyama, Toshimi Chiba
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Patent number: 8728622Abstract: Provided is a base substrate with which a Group-III nitride crystal having a large area and a large thickness can be grown while inhibiting crack generation. A single-crystal substrate for use in growing a Group-III nitride crystal thereon, which satisfies the following expression (1), wherein Z1 (?m) is an amount of warpage of physical shape in a growth surface of the single-crystal substrate and Z2 (?m) is an amount of warpage calculated from a radius of curvature of crystallographic-plane shape in a growth surface of the single-crystal substrate: ?40<Z2/Z1<?1: Expression (1).Type: GrantFiled: July 13, 2012Date of Patent: May 20, 2014Assignee: Mitsubishi Chemical CorporationInventors: Kenji Fujito, Yasuhiro Uchiyama
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Patent number: 8722526Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.Type: GrantFiled: July 27, 2012Date of Patent: May 13, 2014Assignee: Veeco ALD Inc.Inventor: Sang In Lee
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Patent number: 8715414Abstract: There are provided a Si(1-v-w-x)CwAlxNv substrate that achieves high crystallinity and low costs, an epitaxial wafer, and manufacturing methods thereof. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate according to the present invention includes the steps of preparing a different type of substrate 11 and growing a Si(1-v-w-x)CwAlxNv layer having a main surface on the different type of substrate 11. The component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer is 0<x+v<1. The component ratio x+v increases or decreases monotonically from the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 to the main surface of the Si(1-v-w-x)CwAlxNv layer. The component ratio x+v at the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 is closer to that of the material of the different type of substrate 11 than the component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer.Type: GrantFiled: April 17, 2009Date of Patent: May 6, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, Hideaki Nakahata
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Patent number: 8709156Abstract: Epitaxially coated silicon wafers are produced by placing a wafer polished on its front side on a susceptor in an epitaxy reactor, first pretreating under a hydrogen atmosphere and in a second and a third step with addition of an etching medium to the hydrogen atmosphere, and subsequently providing an epitaxial layer, wherein during the first and second steps the hydrogen flow rate is 20-100 slm, during the second and third steps the flow rate of the etching medium is 0.5-1.5 slm, during the second step the average temperature in the reactor chamber is 950-1050° C., and the power of heating elements above and below the susceptor is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical region encompassing the central axis of and a part lying outside this region; and during the third step the hydrogen flow rate is reduced to 0.5-10 slm. In a second method, during the third pretreatment step the flow rate of the etching medium is increased to 1.Type: GrantFiled: April 23, 2010Date of Patent: April 29, 2014Assignee: Siltronic AGInventor: Joerg Haberecht
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Patent number: 8696809Abstract: A manufacturing method of an epitaxial silicon wafer is provided. The epitaxial silicon wafer includes: a substrate cut out from a silicon monocrystal that has been manufactured, doped with nitrogen and pulled up in accordance with Czochralski method; and an epitaxial layer formed on the substrate. The manufacturing method includes: cleaning a surface of the substrate with fluorinated acid by spraying onto the surface of the substrate fluorinated acid vaporized by a bubbling tank of a substrate cleaning apparatus; and forming an epitaxial layer on the cleaned surface of the substrate.Type: GrantFiled: June 12, 2008Date of Patent: April 15, 2014Assignee: Sumco Techxiv CorporationInventors: Kazuaki Kozasa, Kosuke Miyoshi
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Publication number: 20140027777Abstract: Embodiments relate to growing an epitaxy gallium-nitride (GaN) layer on a porous silicon (Si) substrate. The porous Si substrate has a larger surface area compared to non-porous Si substrate to distribute and accommodate stress caused by materials deposited on the substrate. An interface adjustment layer (e.g., transition metal silicide layer) is formed on the porous silicon substrate to promote growth of a buffer layer. A buffer layer formed for GaN layer may then be formed on the silicon substrate. A seed-layer for epitaxial growth of GaN layer is then formed on the buffer layer.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: SYNOS TECHNOLOGY, INC.Inventor: Sang In LEE
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Patent number: 8632633Abstract: Engineered defects are reproduced in-situ with graphene via a combination of surface manipulation and epitaxial reproduction. A substrate surface that is lattice-matched to graphene is manipulated to create one or more non-planar features in the hexagonal crystal lattice. These non-planar features strain and asymmetrically distort the hexagonal crystal lattice of epitaxially deposited graphene to reproduce “in-situ” engineered defects with the graphene. These defects may be defects in the classic sense such as Stone-Wales defect pairs or blisters, ridges, ribbons and metacrystals. Nano or micron-scale structures such as planar waveguides, resonant cavities or electronic devices may be constructed from linear or closed arrays of these defects. Substrate manipulation and epitaxial reproduction allows for precise control of the number, density, arrangement and type of defects. The graphene may be removed and template reused to replicate the graphene and engineered defects.Type: GrantFiled: August 25, 2010Date of Patent: January 21, 2014Assignee: Raytheon CompanyInventors: Delmar L. Barker, Brian J. Zelinski, William R. Owens
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Patent number: 8617310Abstract: Methods of evaluating a superabrasive volume or a superabrasive compact are disclosed. One method may comprise exposing a superabrasive volume to beta particles and detecting a quantity of scattered beta particles. Further, a boundary may be perceived between a first region and a second region of the superabrasive volume in response to detecting the quantity of scattered beta particles. In another embodiment, a boundary between a catalyst-containing region and a catalyst-diminished region of a polycrystalline diamond volume may be perceived. In a further embodiment, a boundary may be perceived between a catalyst-containing region and a catalyst-diminished region of a polycrystalline diamond compact. Additionally, a depth to which a catalyst-diminished region extends within a polycrystalline diamond volume of a polycrystalline diamond compact may be measured in response to detecting a quantity of scattered beta particles. A system configured to evaluate a superabrasive volume is disclosed.Type: GrantFiled: May 7, 2010Date of Patent: December 31, 2013Assignee: US Synthetic CorporationInventor: Michael A. Vail
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Patent number: 8551246Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.Type: GrantFiled: May 7, 2009Date of Patent: October 8, 2013Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
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Patent number: 8529698Abstract: Methods, devices, and compositions of matter related to high efficiency InGaN-based photovoltaic devices. The disclosed synthesis of semiconductor heterostructures may be exploited to produce higher efficiency, longer lasting, photovoltaic cells.Type: GrantFiled: November 11, 2009Date of Patent: September 10, 2013Assignee: Arizona Board Of Regents For And On Behalf Of Arizona State UniversityInventors: Fernando A. Ponce, Rafael Garcia
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Patent number: 8512471Abstract: In a physical vapor transport growth technique for silicon carbide a silicon carbide powder and a silicon carbide seed crystal are introduced into a physical vapor transport growth system and halosilane gas is introduced separately into the system. The source powder, the halosilane gas, and the seed crystal are heated in a manner that encourages physical vapor transport growth of silicon carbide on the seed crystal, as well as chemical transformations in the gas phase leading to reactions between halogen and chemical elements present in the growth system.Type: GrantFiled: May 15, 2012Date of Patent: August 20, 2013Assignee: II-VI IncorporatedInventors: Ilya Zwieback, Thomas E. Anderson, Avinash K. Gupta
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Publication number: 20130178049Abstract: The present invention is directed to a method of manufacturing a substrate, which includes loading a base substrate into a reaction furnace; forming a buffer layer on the base substrate; forming a separation layer on the buffer layer; forming a semiconductor layer on the separation layer at least two; and separating the semiconductor layer from the base substrate via the separation layer through natural cooling by unloading the base substrate from the reaction furnace.Type: ApplicationFiled: October 21, 2012Publication date: July 11, 2013Applicant: LUMIGNTECH CO., LTD.Inventor: LUMIGNTECH CO., LTD.
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Patent number: 8465587Abstract: Hydride vapor-phase deposition (HVPE) systems are disclosed. An HVPE hydride vapor-phase deposition system may include a reactant source chamber and a growth chamber containing a susceptor coupled to the reactant source chamber. The reactant source chamber may be configured to create a reactant gas through a chemical reaction between a solid or liquid precursor and a different precursor gas. The reactant source chamber can be configured to operate at a temperature T(M) significantly above room temperature. The reactant gas can be chemically unstable at or near room temperature. The susceptor is configured to receive a substrate and maintain the substrate at a substrate temperature T(S). The growth chamber includes walls can be configured to operate at a temperature T(C) such that T(M), T(S) are greater than T(C).Type: GrantFiled: December 30, 2009Date of Patent: June 18, 2013Assignee: CBL Technologies, Inc.Inventors: Glenn S. Solomon, David J. Miller
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Patent number: 8460464Abstract: A method for producing one or more single crystalline diamonds. The method comprises placing one or more substrates on a substrate holder in chemical vapor vaporization (CVD) chamber. A mixture of gases including at least one gas having a carbon component is provided adjacent to the one or more substrates in the CVD chamber. Thereafter, the mixture of gases is exposed to microwave radiation to generate a plasma. Reactive species of nitrogen produced in a remote reactive gas generator are introduced in the plasma. Then, the one or more substrates are exposed to the plasma, such that diamond growth occurs at a rate of 10 to 100 microns per hour, to produce one or more single crystalline diamonds.Type: GrantFiled: July 20, 2009Date of Patent: June 11, 2013Inventor: Rajneesh Bhandari
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Patent number: 8449675Abstract: A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an n++ or p++ doped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n+ or p+ to the level n++ or p++, and an epitaxial layer is then deposited on this layer.Type: GrantFiled: July 28, 2008Date of Patent: May 28, 2013Assignee: Siltronic AGInventors: Rupert Krautbauer, Gerhard Huettl, Andrej Lenz, Erwin-Peter Mayer, Rainer Winkler
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Patent number: 8419856Abstract: Disclosed is a substrate processing apparatus in which a plurality of rod-like ceramic heaters are arranged in the form of islands and affixed to the top plate of a process chamber so as to face a wafer, and the lower end portion of each ceramic heater is provided with a metal catalyst layer in such a manner that the metal catalyst layer faces a gas discharge hole of a gas diffusion plate. Consequently, the metal catalyst layer is indirectly heated by the ceramic heater (a resistance heating wire), thereby activating a processing gas.Type: GrantFiled: July 12, 2012Date of Patent: April 16, 2013Assignee: Tokyo Electron LimitedInventor: Isao Gunji
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Patent number: 8419853Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.Type: GrantFiled: November 23, 2009Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
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Patent number: 8404571Abstract: Provided is a film deposition method capable of improving the crystal characteristic near an interface according to the lattice constant of a material that will constitute a thin film to be deposited. Specifically, a substrate is curved relative to the direction along one main surface on which the thin film is to be deposited, according to the lattice constant the material that will constitute the thin film to be deposited and the lattice constant of a material constituting the one main surface. The thin film is deposited on the one main surface of the substrate with the substrate curved.Type: GrantFiled: June 25, 2009Date of Patent: March 26, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Tatsuya Tanabe
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Patent number: 8404045Abstract: An underlying film 2 of a group III nitride is formed on a substrate 1 by vapor phase deposition. The substrate 1 and the underlying film 2 are subjected to heat treatment in the present of hydrogen to remove the underlying film 2 so that the surface of the substrate 1 is roughened. A seed crystal film 4 of a group III nitride single crystal is formed on a surface of a substrate 1A by vapor phase deposition. A group III nitride single crystal 5 is grown on the seed crystal film 4 by flux method.Type: GrantFiled: January 8, 2010Date of Patent: March 26, 2013Assignee: NGK Insulators, Ltd.Inventors: Yoshitaka Kuraoka, Shigeaki Sumiya, Makoto Miyoshi, Minoru Imaeda
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Patent number: 8394197Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.Type: GrantFiled: July 11, 2008Date of Patent: March 12, 2013Assignee: Sub-One Technology, Inc.Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
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Patent number: 8372196Abstract: In a manufacturing apparatus for manufacturing an epitaxial wafer with a wafer being mounted substantially concentrically with a susceptor, a center rod is provided to extend in an up-and-down direction on a side of a non-mounting surface of the susceptor so that its upper end is adjacent to the center of the susceptor. With this arrangement, part of radiation light irradiated toward the susceptor is diffusely reflected by the center rod before reaching the central portion of the susceptor, thereby reducing the amount of the radiation light irradiated to the central portion of the susceptor as well as lowering the temperature of the portion. Since the center rod and the susceptor are not in surface contact, the center rod does not take the heat from the susceptor, thereby suppressing the temperature from decreasing locally at the central portion of the susceptor.Type: GrantFiled: November 2, 2009Date of Patent: February 12, 2013Assignee: Sumco Techxiv CorporationInventors: Motonori Nakamura, Yoshinobu Mori, Takeshi Masuda, Hidenori Kobayashi, Kazuhiro Narahara
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Patent number: 8349076Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.Type: GrantFiled: October 11, 2006Date of Patent: January 8, 2013Assignee: Samsung Corning Precision Materials Co., Ltd.Inventors: In-Jae Song, Jai-yong Han
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Patent number: 8328933Abstract: The invention provides a method to enforce face-to-face stacking of organic semiconductors in the solid state that employs semiconductor co-crystal formers (SCCFs), to align semiconductor building blocks (SBBs). Single-crystal X-ray analysis reveals ?-orbital overlap optimal for organic semiconductor device applications.Type: GrantFiled: December 9, 2008Date of Patent: December 11, 2012Assignee: University of Iowa Research FoundationInventors: Leonard R. MacGillivray, Anatoliy N. Sokolov
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Publication number: 20120299061Abstract: Disclosed is a technology of manufacturing, at low cost, an epitaxial crystal substrate provided with a high-quality and uniform epitaxial layer, said technology being useful in the case of growing the epitaxial layer composed of a semiconductor having a lattice constant different from that of the substrate. The substrate, which is composed of a first compound semiconductor, and which has a step-terrace structure on the surface, is used, and on the surface of the substrate, a composition modulation layer composed of a second compound semiconductor is grown by step-flow, while changing the composition in the same terrace. Then, the epitaxial crystal substrate is manufactured by growing, on the composition modulation layer, the epitaxial layer composed of the third compound semiconductor having the lattice constant different from that of the first compound semiconductor.Type: ApplicationFiled: January 19, 2011Publication date: November 29, 2012Inventors: Hajime Momoi, Koji Kakuta
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Patent number: 8273177Abstract: An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition.Type: GrantFiled: August 31, 2009Date of Patent: September 25, 2012Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 8268076Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.Type: GrantFiled: May 13, 2010Date of Patent: September 18, 2012Assignee: Siltronic AGInventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
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Patent number: 8226767Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.Type: GrantFiled: October 20, 2008Date of Patent: July 24, 2012Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
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Patent number: 8221546Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.Type: GrantFiled: March 26, 2008Date of Patent: July 17, 2012Assignee: SS SC IP, LLCInventor: Jie Zhang
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Publication number: 20120161287Abstract: A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.Type: ApplicationFiled: January 17, 2012Publication date: June 28, 2012Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Michael Iza, Troy J. Baker, Benjamin A. Haskell, Steven P. DenBaars, Shuji Nakamura
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Patent number: 8198628Abstract: A semiconductor structure that is to be heated. The structure includes a substrate for the front face deposition of a useful layer intended to receive components for electronics, optics or optoelectronics. The structure contains doped elements that absorb infrared radiation so as to substantially increase infrared absorption by the structure so that the front face reaches a given temperature when a given infrared power is supplied to the structure. At least one part of the doped elements have insufficient electrical activity or localization in the structure, such that they cannot disturb the operation of the components. In addition, a method of producing this structure and a method of forming a useful layer of semiconductor material on the structure.Type: GrantFiled: March 25, 2008Date of Patent: June 12, 2012Assignee: SoitecInventors: Robert Langer, Hacène Lahreche
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Patent number: 8197598Abstract: A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600˜1200° C.Type: GrantFiled: November 6, 2008Date of Patent: June 12, 2012Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
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Patent number: 8187379Abstract: A method for minimizing particle generation during deposition of a graded Si1-xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1-xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.Type: GrantFiled: March 29, 2011Date of Patent: May 29, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
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Patent number: 8168000Abstract: A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.Type: GrantFiled: June 14, 2006Date of Patent: May 1, 2012Assignee: International Rectifier CorporationInventors: Mike Briere, Robert Beach
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Patent number: 8147612Abstract: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.Type: GrantFiled: April 24, 2007Date of Patent: April 3, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tomoki Uemura, Takashi Sakurada, Shinsuke Fujiwara, Takuji Okahisa, Koji Uematsu, Hideaki Nakahata
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Patent number: 8133321Abstract: A process for producing a silicon carbide single crystal in which a silicon carbide single crystal layer is homo-epitaxially or hetero-epitaxially grown on a surface of a single crystal substrate, wherein a plurality of substantially parallel undulation ridges that extend in a first direction on the single crystal substrate surface is formed on said single crystal substrate surface; each of the undulation ridges on said single crystal substrate surface has a height that undulates as each of the undulation ridges extends in the first direction; and the undulation ridges are disposed so that planar defects composed of anti-phase boundaries and/or twin bands that propagate together with the epitaxial growth of the silicon carbide single crystal merge with each other.Type: GrantFiled: May 23, 2006Date of Patent: March 13, 2012Assignee: Hoya CorporationInventors: Takamitsu Kawahara, Kuniaki Yagi, Naoki Hatta, Hiroyuki Nagasawa
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Patent number: 8128749Abstract: An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI substrate, or a seeded SOI substrate. The gettering layer may disposed under a buried oxide (BOX) layer. The gettering layer may be disposed on a backside of the substrate.Type: GrantFiled: October 4, 2007Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Junedong Lee, Devendra K. Sadana, Dominic J. Schepis
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Patent number: 8088222Abstract: A novel approach for the growth of high-quality on-axis epitaxial silicon carbide (SiC) films and boules, using the Chemical Vapor Deposition (CVD) technique, is described here. The method includes a method of substrate preparation, which allows for the growth of “on-axis” SiC films, plus an approach giving the opportunity to grow silicon carbide on singular (a small-angle miscut) substrates, using halogenated carbon-containing precursors (carbon tetrachloride, CCl4, or halogenated hydrocarbons, CHCl3, CH2Cl2, or CH3Cl, or similar compounds or chemicals), or introducing other chlorine-containing species, in the gas phase, in the growth chamber. At gas mixtures greater than the critical amount, small clusters of SiC are etched, before they can become stable nuclei. The presence of chlorine and the formation of gas species allow an increased removal rate of these nuclei, in contrast to the growth without the presence of chlorine.Type: GrantFiled: July 27, 2007Date of Patent: January 3, 2012Assignee: Widetronix Inc.Inventors: Yuri Makarov, Michael Spencer
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Patent number: 8080106Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.Type: GrantFiled: July 20, 2009Date of Patent: December 20, 2011Assignee: Sumco CorporationInventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
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Patent number: 8071167Abstract: Embodiments of the present invention relate to a surface preparation treatment for the formation of thin films of high k dielectric materials over substrates. One embodiment of a method of forming a high k dielectric layer over a substrate includes pre-cleaning a surface of a substrate to remove native oxides, pre-treating the surface of the substrate with a hydroxylating agent, and forming a high k dielectric layer over the surface of the substrate. One embodiment of a method of forming a hafnium containing layer over a substrate includes introducing an acid solution to a surface of a substrate, introducing a hydrogen containing gas and an oxygen containing gas to the surface of the substrate, and forming a hafnium containing layer over the substrate.Type: GrantFiled: June 4, 2010Date of Patent: December 6, 2011Assignee: Applied Materials, Inc.Inventors: Shreyas S. Kher, Shixue Han, Craig R. Metzner
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Patent number: 8048223Abstract: The present invention provides in one example embodiment a synthetic diamond and a method of growing such a diamond on a plurality of seed diamonds, implanting the grown diamond with ions, and separating the grown diamond from the plurality of seed diamonds.Type: GrantFiled: July 21, 2005Date of Patent: November 1, 2011Assignee: Apollo Diamond, Inc.Inventors: Alfred Genis, Robert C. Linares, Patrick J. Doering
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Patent number: 8048224Abstract: Embodiments of the invention relate to a process for producing a III-N bulk crystal, wherein III denotes at least one element selected from group III of the periodic system, selected from Al, Ga and In, wherein the III-N bulk crystal is grown by vapor phase epitaxy on a substrate, and wherein the growth rate is measured in real-time. By actively measuring and controlling the growth rate in situ, i.e. during the epitaxial growth, the actual growth rate can be maintained essentially constant. In this manner, III-N bulk crystals and individualized III-N single crystal substrates separated therefrom, which respectively have excellent crystal quality both in the growth direction and in the growth plane perpendicular thereto, can be obtained.Type: GrantFiled: May 7, 2007Date of Patent: November 1, 2011Assignee: Freiberger Compound Materials GmbHInventors: Gunnar Leibiger, Frank Habel, Stefan Eichler
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Patent number: 8038793Abstract: The invention provides an epitaxial growth method which is a single wafer processing epitaxial growth method by which at least a single crystal substrate is placed in a reaction chamber with an upper wall having a downward convexity and an epitaxial layer is deposited on the single crystal substrate by introducing raw material gas and carrier gas into the reaction chamber through a gas feed port, in which, after any one of the radius of curvature of the upper wall of the reaction chamber and a difference between an upper end of the gas feed port and a lower end of the upper wall of the reaction chamber in the height direction or both are adjusted in accordance with the flow rate of the carrier gas which is introduced into the reaction chamber through the gas feed port, an epitaxial layer is deposited on the single crystal substrate.Type: GrantFiled: November 18, 2008Date of Patent: October 18, 2011Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Masato Ohnishi
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Patent number: 8029620Abstract: In a first aspect, a method is provided for forming an epitaxial layer stack on a substrate. The method includes (1) selecting a target carbon concentration for the epitaxial layer stack; (2) forming a carbon-containing silicon layer on the substrate, the carbon-containing silicon layer having at least one of an initial carbon concentration, a thickness and a deposition time selected based on the selected target carbon concentration; and (3) forming a non-carbon-containing silicon layer on the carbon-containing silicon layer prior to etching. Numerous other aspects are provided.Type: GrantFiled: July 31, 2007Date of Patent: October 4, 2011Assignee: Applied Materials, Inc.Inventors: Yihwan Kim, Zhiyuan Ye, Ali Zojaji
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Patent number: 8016943Abstract: A method for preparing film oxides deposited on a substrate with a resulting grain boundary junction that is atomistically straight. A bicrystal substrate having a straight grain boundary is prepared as a template. The Miller indices h1, k1, h2, k2 of the two grains of the substrate are chosen such that the misorientation angle of the film is equal to arctan k1/h1+arctan k2/h2. The film is grown on the substrate using a layer-by-layer growth mode.Type: GrantFiled: November 27, 2007Date of Patent: September 13, 2011Assignee: The Trustees of Columbia University in the City of New YorkInventor: Siu-Wai Chan