Abstract: Methods are provided of selectively obtaining n-type and p-type regions from the same III-Nitride layer deposited on a substrate without using diffusion or ion-implantation techniques. The III-Nitride layer is co-doped simultaneously with n-type and p-type dopants, with p-type dopant concentration higher than n-type dopant to generate p-n junctions. The methods rely on obtaining activated p-type dopants only in selected regions to generate p-type layers, whereas the rest of the regions effectively behave as an n-type layer by having deactivated p-type dopant atoms.

Abstract: A photovoltaic cell can include a dopant in contact with a semiconductor layer.

Abstract: A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is Hz, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH3 (arsine), PH3 (phosphine), H2Se (hydrogen selenide), H2Te (hydrogen telluride), SbH3 (hydrogen antimonide), H2S (hydrogen sulfide), and NH3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

Abstract: The invention provides a SiC single crystal production apparatus with high uniformity of temperature distribution in a crystal growth vessel. The SiC single crystal production apparatus includes a crystal growth vessel containing SiC raw material; an insulation part covering the periphery of the crystal growth vessel; a heater used to heat the crystal growth vessel; and a holding member used to hold the crystal growth vessel, wherein the crystal growth vessel is held in a suspended state by the holding member.

Abstract: An electrostatic harvester device for charging an energy storage device is provided. The electrostatic harvester device comprises an inductor, a variable capacitor device, a semiconductor device, and a plurality of transistors. The inductor is operable to receive electric charge and store the electric charge. The variable capacitor device is configured to receive electric charge from the inductor and to change capacitance in response to physical stimulation. The semiconductor device is operable to allow electric current to flow from the variable capacitor device. The transistors are operable to connect at least two of the aforementioned devices. At least one of the transistors comprises at least one of gallium nitride or aluminum gallium nitride.

Abstract: A method of manufacturing a SiC single crystal includes: a storing step of storing a SiC source, which is a powder, in an inner bottom part of a crucible, wherein the crucible is configured to store the SiC source and to attach a seed crystal to a position of the crucible which faces the SiC source; a placing step of placing a porous material on at least a portion of a first surface of the SiC source, wherein the first surface is positioned on a side of the seed crystal; and a crystal growth step of sublimating the SiC source by heating to grow a crystal on the seed crystal, in which the porous material is formed of carbon or a carbide, and the hole diameter of the porous material is smaller than the average particle diameter of the SiC source.

Abstract: An object of the present invention is to provide a method for producing a group III nitride crystal in which generation of breaking or cracks is less likely to occur. To achieve the object, the method for producing a group III nitride crystal includes: seed crystal preparation including disposing a plurality of crystals of a group III nitride as a plurality of seed crystals on a substrate; and crystal growth including growing group III nitride crystals by contacting a surface of each of the seed crystals with a melt containing at least one group III element selected from gallium, aluminum, and indium and an alkali metal in an atmosphere containing nitrogen. In the seed crystal preparation, the plurality of seed crystals are disposed within a hexagonal region provided on the substrate.

Abstract: A gas distribution unit in connection with an atomic layer deposition reactor includes an inlet surface, an outlet surface, a process gas channel extending through the gas distribution unit and being open to the inlet surface and to the outlet surface, a barrier gas inlet fitting connected to the process gas channel between the inlet surface and the outlet surface for supplying barrier gas to the process gas channel, and a barrier gas outlet fitting connected to the process gas channel between the inlet surface and the barrier gas inlet fitting for discharging barrier gas from the process gas channel.

Abstract: The present disclosure provides a wafer annealing method, including: preparing a wafer, the wafer includes a plurality of regions concentrically disposed on the wafer; heating the plurality of regions, the heating process includes a plurality of heating stages, each of the heating stages has a different heating rate, temperatures of the plurality of regions vary in each of the heating stages; performing heat preservation on the plurality of regions; and cooling the plurality of regions through blowing nitrogen. The wafer annealing method can improve the electrical uniformity of the wafer.

Abstract: A silicon carbide ingot manufacturing method and a silicon carbide ingot manufacturing system are provided. The silicon carbide ingot manufacturing method and the silicon carbide ingot manufacturing system may change a temperature gradient depending on the growth of an ingot by implementing a guide which has a tilted angle to an external direction from the interior of a reactor, in an operation to grow an ingot during a silicon carbide ingot manufacturing process.

Abstract: A multijunction solar cell includes a base substrate comprising a Group IV semiconductor and a dopant of a first carrier type. A patterned emitter is formed at a first surface of the base substrate. The patterned emitter comprises a plurality of well regions doped with a dopant of a second carrier type in the Group IV semiconductor. The base substrate including the patterned emitter form a first solar subcell. The multijunction solar cell further comprises an upper structure comprising one or more additional solar subcells over the first solar subcell. Methods of making a multijunction solar cell are also described.

Abstract: What is provided here are: a step of forming a first semiconductor layer on a base member; a step of forming a mask on the first semiconductor layer; a step of etching the first semiconductor layer by using the mask, to thereby form a semiconductor structure; a step of forming a second semiconductor layer in a region abutting on a side surface of the semiconductor structure, said second semiconductor layer having a convex portion abutting to the mask; a convex-portion removing step of removing the convex portion by supplying an etching gas thereto; and a regrown-layer forming step of supplying a material gas onto the semiconductor structure and the second semiconductor layer, to thereby form a regrown layer; wherein the convex-portion removing step and the regrown-layer forming step are executed in a same manufacturing apparatus.

Abstract: Embodiments of the disclosed subject matter provide a device including a nozzle, a source of material to be deposited on a substrate in fluid communication with the nozzle, a delivery gas source in fluid communication with the source of material to be deposited with the nozzle, an exhaust channel disposed adjacent to the nozzle, and a confinement gas source in fluid communication with the nozzle and the exhaust channel, and disposed adjacent to the exhaust channel.

Abstract: Disclosed is a Group III nitride semiconductor template for a 300-400 nm near-ultraviolet light emitting semiconductor device, the template including: a growth substrate; a nucleation layer based on AlxGa1-xN (0<x?1, x>y); and a monocrystalline Group III nitride semiconductor layer based on AlyGa1-yN (y>0), and a near-ultraviolet light emitting semiconductor device using the template.

Abstract: A silicon carbide semiconductor substrate includes an epitaxial layer. A difference of a donor concentration and an acceptor concentration of the epitaxial layer is within a range from 1×1014/cm3 to 1×1015/cm3. Further, the donor concentration and the acceptor concentration of the epitaxial layer are a concentration unaffected by an impurity inside epitaxial growth equipment.

Abstract: Vapor cells are disclosed that include a dielectric body having a first surface and a second surface. The dielectric body includes a plurality of walls extending from the first surface to the second surface. A perimeter wall surrounds an open volume of the dielectric body and interconnected walls are arranged within the open volume to partition the open volume into a plurality of cells. Each cell has a first opening defined by the first surface and a second opening defined by the second surface. The vapor cells additionally include a first optical window covering the first openings and having a surface bonded to the first surface of the dielectric body to form a seal around each of the first openings. A second optical window covers the second openings and has a surface bonded to the second surface of the dielectric body to form a seal around each of the second openings.

Abstract: There is provided a method for manufacturing a nitride semiconductor template constituted by forming a nitride semiconductor layer on a substrate, comprising: (a) preparing a pattern-substrate as the substrate, with a concavo-convex pattern formed on a front surface of the pattern-substrate, (b) forming a first layer by epitaxially growing a nitride semiconductor containing aluminum on the concavo-convex pattern of the pattern-substrate, in a thickness of not flattening a front surface; (c) applying annealing to the first layer; and (d) forming a second layer by epitaxially growing a nitride semiconductor containing aluminum so as to overlap on the first layer after performing (c), and in a thickness of flattening a front surface, and constituting the nitride semiconductor layer by the first layer and the second layer.

Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.

Abstract: A laser annealing process of a drive backplane includes: providing a mask, which has a light transmission area; and sequentially moving the mask to cover different areas of an amorphous silicon layer of the drive backplane, and annealing the amorphous silicon layer exposed in the light transmission area to form a poly-silicon pattern.

Abstract: A method for monolithically depositing a monocrystalline IV-IV layer that glows when excited and that is composed of a plurality of elements of the IV main group, in particular a GeSn or Si—GeSn layer, the IV-IV layer having a dislocation density less than 6 cm?2, on an IV substrate, in particular a silicon or germanium substrate, including the following steps: providing a hydride of a first IV element (A), such as Ge2H6 or Si2H6; providing a halide of a second IV element (B), such as SnCl4; heating the substrate to a substrate temperature that is less than the decomposition temperature of the pure hydride or of a radical formed therefrom and is sufficiently high that atoms of the first element (A) and of the second element (B) are integrated into the surface in crystalline order, wherein the substrate temperature lies, in particular, in a range between 300° C. and 475° C.

Abstract: A method and apparatus for delivering gases to a semiconductor processing system are provided. In some embodiments, the apparatus includes a gas inlet line having an inlet valve; a gas outlet line having an outlet valve; a gas flow controller arranged to control the flow through the inlet valve; an orifice contained within at least one of the gas outlet line, the outlet valve, a chemical ampoule outlet valve, or outlet isolation valve; a chemical ampoule fluidly coupled to at least one of the gas inlet line and the gas outlet line; and a processing chamber. In some embodiments, the apparatus further includes a check valve, one or more orifices, and/or a heated divert line.

Abstract: A cooling device for a heat source, such as an electronic component, has a single or set of nano- and/or micro-sized channel(s) connected to a single or multiple reservoir(s). The heat source causes nucleation within a channel, and a vapor bubble forms removing heat from the heat source via evaporation of liquid to vapor in the bubble and condensation of the generated vapor at the cooler ends of the bubble. Thus, the channel operates as a passive heat pipe and removes heat from the source by passively circulating the cooling fluid between the vapor bubble and the reservoir(s).

Abstract: A photovoltaic cell can include a dopant in contact with a semiconductor layer.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

Abstract: A method for manufacturing a restored substrate includes: removing a nitride semiconductor layer from a stacked-layer in which the nitride semiconductor layer has been laminated on a substrate; oxidizing material adhering to the substrate to produce an oxide deposit after the removing of the nitride semiconductor layer from the stacked-layer; and removing the oxide deposit from the substrate. A method for manufacturing a light emitting element includes stacking nitride semiconductor layers including an active layer on the restored substrate obtained by the above method.

Abstract: A method of applying a multi-layer plasma resistant coating on an article comprises performing plating or ALD to form a conformal first plasma resistant layer on an article, wherein the conformal first plasma resistant layer is formed on a surface of the article and on walls of high aspect ratio features in the article. The conformal first plasma resistant coating has a porosity of approximately 0% and a thickness of approximately 200 nm to approximately 1 micron. One of electron beam ion assisted deposition (EB-IAD), plasma enhanced chemical vapor deposition (PECVD), aerosol deposition or plasma spraying is then performed to form a second plasma resistant layer that covers the conformal first plasma resistant layer at a region of the surface but not at the walls of the high aspect ratio features.

Abstract: An embodiment discloses a vertical cavity surface emitting laser and a method for manufacturing the same, the vertical cavity surface emitting laser comprising: a substrate; a lower reflective layer disposed on the substrate; an active layer disposed on the lower reflective layer; an oxide layer disposed on the active layer and comprising a first hole disposed at the center thereof; a capping layer disposed on the oxide layer; and an upper reflective layer disposed on the capping layer and the first hole.

Abstract: To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.

Abstract: The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.

Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.

Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

Abstract: An optoelectronic device and a method for fabricating the optoelectronic device are disclosed. The optoelectronic device comprises a p-n structure, a patterned dielectric layer comprising a dielectric material and a metal layer disposed on the dielectric layer. The metal layer makes one or more contact to the p-n structure through the patterned dielectric layer. The dielectric material may be chemically resistant to acids and may provide adhesion to the p-n structure and the metal layer. The method for fabricating an optoelectronic device comprises providing a p-n structure, providing a dielectric layer on the p-n structure and providing a metal layer on the dielectric layer and then lifting the device off the substrate, such that after the lift off the p-n structure is closer than the patterned dielectric layer to a front side of the device; wherein the device comprises the p-n structure, the patterned dielectric layer, and the metal layer.

Abstract: Methods for large-scale manufacturing of semipolar gallium nitride boules are disclosed. The disclosed methods comprise suspending large-area single crystal seed plates in a rack, placing the rack in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and growing crystals ammonothermally. A bi-faceted growth morphology may be maintained to facilitate fabrication of large area semipolar wafers without growing thick boules.

Abstract: A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.

Abstract: The invention provides a semiconductor structure and a method of preparing a semiconductor structure, which solves the problems of easy cracking, large warpage and large dislocation density which exist in epitaxial growth of a semiconductor compound epitaxial structure on a substrate in the prior art. The semiconductor structure includes: a substrate; at least one periodic structure disposed over the substrate; wherein each of the periodic structures includes at least one period, each period including a first periodic layer and a second periodic layer which are sequentially stacked in an epitaxial direction; wherein the thickness of the nth periodic structure is smaller than the thickness of the (n+1)th periodic structure, wherein n is an integer greater than or equal to 1.

Abstract: The present inventors have conceived of a multi-stage process gas delivery system for use in a substrate processing apparatus. In certain implementations, a first process gas may first be delivered to a substrate in a substrate processing chamber. A second process gas may be delivered, at a later time, to the substrate to aid in the even dosing of the substrate. Delivery of the first process gas and the second process gas may cease at the same time or may cease at separate times.

Abstract: A method for manufacturing a compound semiconductor device includes causing epitaxial growth of a p-type impurity layer containing a compound semiconductor on a foundation layer containing the compound semiconductor. The causing the epitaxial growth includes performing pre-doping to preliminarily introduce dopant gas before introducing material gas for the epitaxial growth of the compound semiconductor. The dopant gas contains an organic metal material providing dopant of p-type impurities. An impurity concentration profile of the p-type impurity layer is controlled by controlling a time of the pre-doping.

Abstract: A laser structure includes a substrate, a buffer layer formed on the substrate and a light emitting diode (LED) formed on the buffer layer. A photonic crystal layer is formed on the LED. A monolayer semiconductor nanocavity laser is formed on the photonic crystal layer for receiving light through the photonic crystal layer from the LED, wherein the LED and the laser are formed monolithically and the LED acts as an optical pump for the laser.

Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Abstract: A method of processing a gallium nitride substrate, includes providing a gallium nitride substrate, polishing a surface of the gallium nitride substrate, and cleaning the polished surface of the gallium nitride substrate. The polished surface includes a GaL?/CK? peak intensity ratio in energy dispersive X-ray microanalysis (EDX) spectrum which is not less than 2, the EDX spectrum being obtained in an EDX of the surface of the gallium nitride substrate using a scanning electron microscope (SEM) at an accelerating voltage of 3 kV.

Abstract: Provided is a SiC single crystal wafer, which is manufactured from a SiC single crystal ingot grown by the sublimation-recrystallization method, and which brings about high device performance and high device manufacture yield when used as a wafer for manufacturing a device. The SiC single crystal wafer has, in a surface thereof, a basal plane dislocation density of 1,000 dislocations per cm2 or less, a threading screw dislocation density of 500 dislocations per cm2 or less, and a Raman index of 0.2 or less. Further provided is a method of manufacturing a SiC single crystal ingot, including controlling heat input from a side surface of the single crystal ingot during growth of a single crystal, to thereby grow the crystal while changes in the temperature distribution of the single crystal ingot are reduced.

Abstract: An aluminium gallium indium phosphide (AlGaInP)-based semiconductor laser device is provided. On a main surface of a semiconductor substrate formed of n-type GaAs (gallium arsenide), from the bottom layer, an n-type buffer layer, an n-type cladding layer formed of an AlGaInP-based semiconductor containing silicon (Si) as a dopant, an active layer, a p-type cladding layer formed of an AlGaInP-based semiconductor containing magnesium (Mg) or zinc (Zn) as a dopant, an etching stopper layer, and a p-type contact layer are formed. Here, when an Al composition ratio x of the AlGaInP-based semiconductor is taken as a composition ratio of Al and Ga defined as (AlxGa1-x)0.5In0.5P, a composition of the n-type cladding layer is expressed as (AlxnGa1-xn)0.5In0.5P (0.9<xn<1) and a composition of the p-type cladding layer is expressed as (AlxpGa1-xp)0.5In0.5P (0.9<xp?1), and xn and xp satisfy a relationship of xn<xp.

Abstract: A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.

Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.

Abstract: An optical element comprising: synthetic diamond material; and a flattened lens surface structure in the form of a zone plate, Fresnel lens, or a spherical lens formed directly in at least one surface of the synthetic diamond material, wherein the synthetic diamond material has an absorption coefficient measured at room temperature of ?0.5 cm?1 at a wavelength of 10.6 ?m, and wherein the synthetic diamond material has a laser induced damage threshold meeting one or both of the following characteristics: the laser induced damage threshold is at least 30 Jcm?2 measured using a pulsed laser at a wavelength of 10.6 ?m with a pulse duration of 100 ns and a pulse repetition frequency in a range 1 to 10 Hz; and the laser induced damage threshold is at least 1 MW/cm2 measured using a continuous wave laser at a wavelength of 10.6 ?m.

Abstract: There is provided a method of growing a gallium nitride-based crystal, including: forming an interlayer including aluminum nitride or aluminum oxide on a silicon substrate at a film forming temperature of 350 to 700 degrees C.; heating the silicon substrate and the interlayer in an atmosphere containing ammonia or oxygen such that crystal nuclei of the aluminum nitride or the aluminum oxide included in the interlayer are distributed on the silicon substrate; and growing gallium nitride-based crystals on the silicon substrate from the crystal nuclei distributed on the silicon substrate.

Abstract: A light emitting diode (LED) includes a plurality of Group III-nitride nanowires extending from a substrate, at least one Group III-nitride pyramidal shell layer located on each of the plurality of Group III-nitride nanowires, a continuous Group III-nitride pyramidal layer located over the at least one Group III-nitride pyramidal shell layer, and a continuous pyramidal contact layer located over the continuous Group III-nitride pyramidal layer. The at least one Group III-nitride pyramidal shell layer is located in an active region of the LED. The plurality of Group III-nitride nanowires are doped one of n- or p-type. The continuous Group III-nitride pyramidal layer is doped another one of p- or n-type to form a junction with the plurality of Group III-nitride nanowires. A distance from a side portion of the continuous contact layer to the plurality of Group III-nitride nanowires is shorter than a distance of an apex of the continuous contact layer to the plurality of Group III-nitride nanowires.

Abstract: In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate (70) to mechanical polishing is removed by heating the substrate (70) under Si vapor pressure. An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed. In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate (70) performed the ion activation step are removed by heating the substrate (70) under Si vapor pressure. After that, an electrode formation step in which electrodes are formed on the substrate (70) is performed.

Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.