Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/89)
  • Patent number: 11069833
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Patent number: 10998189
    Abstract: A laser annealing process of a drive backplane includes: providing a mask, which has a light transmission area; and sequentially moving the mask to cover different areas of an amorphous silicon layer of the drive backplane, and annealing the amorphous silicon layer exposed in the light transmission area to form a poly-silicon pattern.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 4, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Guan, Zhi Wang, Chen Xu
  • Patent number: 10988858
    Abstract: A method for monolithically depositing a monocrystalline IV-IV layer that glows when excited and that is composed of a plurality of elements of the IV main group, in particular a GeSn or Si—GeSn layer, the IV-IV layer having a dislocation density less than 6 cm?2, on an IV substrate, in particular a silicon or germanium substrate, including the following steps: providing a hydride of a first IV element (A), such as Ge2H6 or Si2H6; providing a halide of a second IV element (B), such as SnCl4; heating the substrate to a substrate temperature that is less than the decomposition temperature of the pure hydride or of a radical formed therefrom and is sufficiently high that atoms of the first element (A) and of the second element (B) are integrated into the surface in crystalline order, wherein the substrate temperature lies, in particular, in a range between 300° C. and 475° C.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: April 27, 2021
    Assignee: Forschungszentrum Jülich GmbH
    Inventors: Detlev Grützmacher, Stephan Wirths, Dan Mihai Buca, Siegfried Mantl
  • Patent number: 10947621
    Abstract: A method and apparatus for delivering gases to a semiconductor processing system are provided. In some embodiments, the apparatus includes a gas inlet line having an inlet valve; a gas outlet line having an outlet valve; a gas flow controller arranged to control the flow through the inlet valve; an orifice contained within at least one of the gas outlet line, the outlet valve, a chemical ampoule outlet valve, or outlet isolation valve; a chemical ampoule fluidly coupled to at least one of the gas inlet line and the gas outlet line; and a processing chamber. In some embodiments, the apparatus further includes a check valve, one or more orifices, and/or a heated divert line.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Adib Khan, Qiwei Liang, Srinivas D. Nemani, Tobin Kaufman-Osborn
  • Patent number: 10881034
    Abstract: A cooling device for a heat source, such as an electronic component, has a single or set of nano- and/or micro-sized channel(s) connected to a single or multiple reservoir(s). The heat source causes nucleation within a channel, and a vapor bubble forms removing heat from the heat source via evaporation of liquid to vapor in the bubble and condensation of the generated vapor at the cooler ends of the bubble. Thus, the channel operates as a passive heat pipe and removes heat from the source by passively circulating the cooling fluid between the vapor bubble and the reservoir(s).
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 29, 2020
    Assignee: Syracuse University
    Inventors: Shalabh C. Maroo, An Zou, Manish Gupta
  • Patent number: 10861994
    Abstract: A photovoltaic cell can include a dopant in contact with a semiconductor layer.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: December 8, 2020
    Assignee: First Solar, Inc.
    Inventors: Anke Abken, Markus Gloeckler, Roger Green, Akhlesh Gupta, Upali Jayamaha, Peter Meyers, Rick Powell
  • Patent number: 10784146
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
  • Patent number: 10763100
    Abstract: A method for manufacturing a restored substrate includes: removing a nitride semiconductor layer from a stacked-layer in which the nitride semiconductor layer has been laminated on a substrate; oxidizing material adhering to the substrate to produce an oxide deposit after the removing of the nitride semiconductor layer from the stacked-layer; and removing the oxide deposit from the substrate. A method for manufacturing a light emitting element includes stacking nitride semiconductor layers including an active layer on the restored substrate obtained by the above method.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 1, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Takayuki Mitsunaga
  • Patent number: 10755900
    Abstract: A method of applying a multi-layer plasma resistant coating on an article comprises performing plating or ALD to form a conformal first plasma resistant layer on an article, wherein the conformal first plasma resistant layer is formed on a surface of the article and on walls of high aspect ratio features in the article. The conformal first plasma resistant coating has a porosity of approximately 0% and a thickness of approximately 200 nm to approximately 1 micron. One of electron beam ion assisted deposition (EB-IAD), plasma enhanced chemical vapor deposition (PECVD), aerosol deposition or plasma spraying is then performed to form a second plasma resistant layer that covers the conformal first plasma resistant layer at a region of the surface but not at the walls of the high aspect ratio features.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 25, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Toan Tran, Laksheswar Kalita, Tae Won Kim, Dmitry Lubomirsky, Xiaowei Wu, Xiao-Ming He, Cheng-Hsuan Chou, Jennifer Y. Sun
  • Patent number: 10720756
    Abstract: An embodiment discloses a vertical cavity surface emitting laser and a method for manufacturing the same, the vertical cavity surface emitting laser comprising: a substrate; a lower reflective layer disposed on the substrate; an active layer disposed on the lower reflective layer; an oxide layer disposed on the active layer and comprising a first hole disposed at the center thereof; a capping layer disposed on the oxide layer; and an upper reflective layer disposed on the capping layer and the first hole.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 21, 2020
    Assignee: RAYIR, CO.
    Inventor: Won Jin Choi
  • Patent number: 10707309
    Abstract: To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 7, 2020
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hajime Fujikura
  • Patent number: 10693032
    Abstract: The seed substrate comprises a base substrate and a base layer comprising a Group III nitride semiconductor formed on the base substrate, which has a high dislocation density region and a low dislocation density region. The planar pattern of the high dislocation density region is a honeycomb pattern. A hollow exists between the base substrate and the low dislocation density region. The object layer is grown through a flux method using the seed substrate. The high dislocation density region is melted back at an initial stage of crystal growth, and thereafter, the object layer is grown on the top surface of the low dislocation density region. A cavity remains between the high dislocation density region and the object layer. The presence of the cavity and the hollow makes easy to peel the object layer from the seed substrate.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 23, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Miki Moriyama, Shiro Yamazaki, Shohei Kumegawa
  • Patent number: 10686090
    Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu, Norma E. Sosa Cortes
  • Patent number: 10651375
    Abstract: Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Timothy A. Quick, Eugene P. Marsh, Stefan Uhlenbrock, Chet E. Carter, Scott E. Sills
  • Patent number: 10615304
    Abstract: An optoelectronic device and a method for fabricating the optoelectronic device are disclosed. The optoelectronic device comprises a p-n structure, a patterned dielectric layer comprising a dielectric material and a metal layer disposed on the dielectric layer. The metal layer makes one or more contact to the p-n structure through the patterned dielectric layer. The dielectric material may be chemically resistant to acids and may provide adhesion to the p-n structure and the metal layer. The method for fabricating an optoelectronic device comprises providing a p-n structure, providing a dielectric layer on the p-n structure and providing a metal layer on the dielectric layer and then lifting the device off the substrate, such that after the lift off the p-n structure is closer than the patterned dielectric layer to a front side of the device; wherein the device comprises the p-n structure, the patterned dielectric layer, and the metal layer.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 7, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Melissa J. Archer, Thomas J. Gmitter, Gang He
  • Patent number: 10604865
    Abstract: Methods for large-scale manufacturing of semipolar gallium nitride boules are disclosed. The disclosed methods comprise suspending large-area single crystal seed plates in a rack, placing the rack in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and growing crystals ammonothermally. A bi-faceted growth morphology may be maintained to facilitate fabrication of large area semipolar wafers without growing thick boules.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 31, 2020
    Assignee: SLT TECHNOLOGIES, INC.
    Inventors: Mark P. D'Evelyn, Dirk Ehrentraut, Derrick S. Kamber, Bradley C. Downey
  • Patent number: 10535515
    Abstract: A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: January 14, 2020
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Joachim Hertkorn
  • Patent number: 10535739
    Abstract: The invention provides a semiconductor structure and a method of preparing a semiconductor structure, which solves the problems of easy cracking, large warpage and large dislocation density which exist in epitaxial growth of a semiconductor compound epitaxial structure on a substrate in the prior art. The semiconductor structure includes: a substrate; at least one periodic structure disposed over the substrate; wherein each of the periodic structures includes at least one period, each period including a first periodic layer and a second periodic layer which are sequentially stacked in an epitaxial direction; wherein the thickness of the nth periodic structure is smaller than the thickness of the (n+1)th periodic structure, wherein n is an integer greater than or equal to 1.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: January 14, 2020
    Assignee: ENKRIS SEMICONDUCTOR, INC
    Inventors: Kai Cheng, Peng Xiang
  • Patent number: 10526700
    Abstract: The present inventors have conceived of a multi-stage process gas delivery system for use in a substrate processing apparatus. In certain implementations, a first process gas may first be delivered to a substrate in a substrate processing chamber. A second process gas may be delivered, at a later time, to the substrate to aid in the even dosing of the substrate. Delivery of the first process gas and the second process gas may cease at the same time or may cease at separate times.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: January 7, 2020
    Assignee: Lam Research Corporation
    Inventors: Purushottam Kumar, Hu Kang, Adrien LaVoie, Yi Chung Chiu, Frank L. Pasquale, Jun Qian, Chloe Baldasseroni, Shankar Swaminathan, Karl F. Leeser, David Charles Smith, Wei-Chih Lai
  • Patent number: 10439037
    Abstract: A method for manufacturing a compound semiconductor device includes causing epitaxial growth of a p-type impurity layer containing a compound semiconductor on a foundation layer containing the compound semiconductor. The causing the epitaxial growth includes performing pre-doping to preliminarily introduce dopant gas before introducing material gas for the epitaxial growth of the compound semiconductor. The dopant gas contains an organic metal material providing dopant of p-type impurities. An impurity concentration profile of the p-type impurity layer is controlled by controlling a time of the pre-doping.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 8, 2019
    Assignee: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Katsumi Suzuki, Yusuke Yamashita
  • Patent number: 10431956
    Abstract: A laser structure includes a substrate, a buffer layer formed on the substrate and a light emitting diode (LED) formed on the buffer layer. A photonic crystal layer is formed on the LED. A monolayer semiconductor nanocavity laser is formed on the photonic crystal layer for receiving light through the photonic crystal layer from the LED, wherein the LED and the laser are formed monolithically and the LED acts as an optical pump for the laser.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10410918
    Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Wu, Nikolaos Bekiaris, Mehul B. Naik, Jin Hee Park, Mark Hyun Lee
  • Patent number: 10381260
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Inc.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Patent number: 10381230
    Abstract: A method of processing a gallium nitride substrate, includes providing a gallium nitride substrate, polishing a surface of the gallium nitride substrate, and cleaning the polished surface of the gallium nitride substrate. The polished surface includes a GaL?/CK? peak intensity ratio in energy dispersive X-ray microanalysis (EDX) spectrum which is not less than 2, the EDX spectrum being obtained in an EDX of the surface of the gallium nitride substrate using a scanning electron microscope (SEM) at an accelerating voltage of 3 kV.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 13, 2019
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Shunsuke Yamamoto
  • Patent number: 10202706
    Abstract: Provided is a SiC single crystal wafer, which is manufactured from a SiC single crystal ingot grown by the sublimation-recrystallization method, and which brings about high device performance and high device manufacture yield when used as a wafer for manufacturing a device. The SiC single crystal wafer has, in a surface thereof, a basal plane dislocation density of 1,000 dislocations per cm2 or less, a threading screw dislocation density of 500 dislocations per cm2 or less, and a Raman index of 0.2 or less. Further provided is a method of manufacturing a SiC single crystal ingot, including controlling heat input from a side surface of the single crystal ingot during growth of a single crystal, to thereby grow the crystal while changes in the temperature distribution of the single crystal ingot are reduced.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 12, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Masashi Nakabayashi, Kota Shimomura, Yukio Nagahata, Kiyoshi Kojima
  • Patent number: 10170891
    Abstract: An aluminium gallium indium phosphide (AlGaInP)-based semiconductor laser device is provided. On a main surface of a semiconductor substrate formed of n-type GaAs (gallium arsenide), from the bottom layer, an n-type buffer layer, an n-type cladding layer formed of an AlGaInP-based semiconductor containing silicon (Si) as a dopant, an active layer, a p-type cladding layer formed of an AlGaInP-based semiconductor containing magnesium (Mg) or zinc (Zn) as a dopant, an etching stopper layer, and a p-type contact layer are formed. Here, when an Al composition ratio x of the AlGaInP-based semiconductor is taken as a composition ratio of Al and Ga defined as (AlxGa1-x)0.5In0.5P, a composition of the n-type cladding layer is expressed as (AlxnGa1-xn)0.5In0.5P (0.9<xn<1) and a composition of the p-type cladding layer is expressed as (AlxpGa1-xp)0.5In0.5P (0.9<xp?1), and xn and xp satisfy a relationship of xn<xp.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: January 1, 2019
    Assignee: USHIO OPTO SEMICONDUCTORS, INC.
    Inventors: Masato Hagimoto, Haruki Fukai, Tsutomu Kiyosumi, Shinji Sasaki, Satoshi Kawanaka
  • Patent number: 9991208
    Abstract: A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 5, 2018
    Assignee: SILTRONIC AG
    Inventors: Reinhard Schauer, Christian Hager
  • Patent number: 9984873
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9977149
    Abstract: An optical element comprising: synthetic diamond material; and a flattened lens surface structure in the form of a zone plate, Fresnel lens, or a spherical lens formed directly in at least one surface of the synthetic diamond material, wherein the synthetic diamond material has an absorption coefficient measured at room temperature of ?0.5 cm?1 at a wavelength of 10.6 ?m, and wherein the synthetic diamond material has a laser induced damage threshold meeting one or both of the following characteristics: the laser induced damage threshold is at least 30 Jcm?2 measured using a pulsed laser at a wavelength of 10.6 ?m with a pulse duration of 100 ns and a pulse repetition frequency in a range 1 to 10 Hz; and the laser induced damage threshold is at least 1 MW/cm2 measured using a continuous wave laser at a wavelength of 10.6 ?m.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 22, 2018
    Assignee: Element Six Technologies Limited
    Inventors: Daniel Twitchen, Andrew Michael Bennett, Yevgeny Vasilievich Anoikin, Hendrikus Gerardus Maria DeWit
  • Patent number: 9966258
    Abstract: There is provided a method of growing a gallium nitride-based crystal, including: forming an interlayer including aluminum nitride or aluminum oxide on a silicon substrate at a film forming temperature of 350 to 700 degrees C.; heating the silicon substrate and the interlayer in an atmosphere containing ammonia or oxygen such that crystal nuclei of the aluminum nitride or the aluminum oxide included in the interlayer are distributed on the silicon substrate; and growing gallium nitride-based crystals on the silicon substrate from the crystal nuclei distributed on the silicon substrate.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: May 8, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kota Umezawa, Yosuke Watanabe
  • Patent number: 9947831
    Abstract: A light emitting diode (LED) includes a plurality of Group III-nitride nanowires extending from a substrate, at least one Group III-nitride pyramidal shell layer located on each of the plurality of Group III-nitride nanowires, a continuous Group III-nitride pyramidal layer located over the at least one Group III-nitride pyramidal shell layer, and a continuous pyramidal contact layer located over the continuous Group III-nitride pyramidal layer. The at least one Group III-nitride pyramidal shell layer is located in an active region of the LED. The plurality of Group III-nitride nanowires are doped one of n- or p-type. The continuous Group III-nitride pyramidal layer is doped another one of p- or n-type to form a junction with the plurality of Group III-nitride nanowires. A distance from a side portion of the continuous contact layer to the plurality of Group III-nitride nanowires is shorter than a distance of an apex of the continuous contact layer to the plurality of Group III-nitride nanowires.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 17, 2018
    Assignee: QUNANO AB
    Inventors: Werner Seifert, Damir Asoli, Zhaoxia Bi, Jonas Ohlsson, Lars Ivar Samuelson
  • Patent number: 9941116
    Abstract: In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate (70) to mechanical polishing is removed by heating the substrate (70) under Si vapor pressure. An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed. In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate (70) performed the ion activation step are removed by heating the substrate (70) under Si vapor pressure. After that, an electrode formation step in which electrodes are formed on the substrate (70) is performed.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: April 10, 2018
    Assignee: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Noboru Ohtani, Kenta Hagiwara
  • Patent number: 9875926
    Abstract: A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: January 23, 2018
    Assignee: Infineon Technologies AG
    Inventors: Iris Moder, Ingo Muri, Johannes Baumgartl, Oliver Hellmund, Manfred Engelhardt, Hans-Joachim Schulze
  • Patent number: 9876080
    Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 23, 2018
    Assignee: IMEC VZW
    Inventors: Bernardette Kunert, Robert Langer, Geert Eneman
  • Patent number: 9777403
    Abstract: A single-crystal silicon carbide and a single-crystal silicon carbide wafer of good-quality are disclosed that are low in dislocations, micropipes and other crystal defects and enable high yield and high performance when applied to a device, wherein the ratio of doping element concentrations on opposite sides in the direction of crystal growth of the interface between the seed crystal and the grown crystal is 5 or less and the doping element concentration of the grown crystal in the vicinity of the seed crystal is 2×1019 cm?3 to 6×1020 cm?3.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: October 3, 2017
    Assignee: NIPPON STEEL & SUMITOMO METAL CORPORATION
    Inventors: Masashi Nakabayashi, Tatsuo Fujimoto, Masakazu Katsuno, Hiroshi Tsuge
  • Patent number: 9570296
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9552983
    Abstract: A manufacturing method for a semiconductor device, including: loading a wafer into a reaction chamber; placing the wafer on a push-up shaft moved up; preheating the wafer under controlling an in-plane temperature distribution of the wafer to be a recess state under a state of placing the wafer on the push-up shaft moved up; lowering the push-up shaft with the wafer kept in the recess state to hold the wafer on a wafer holding member; heating the wafer to a predetermined temperature; rotating the wafer; and supplying a process gas onto the wafer.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: January 24, 2017
    Assignee: NuFlare Technology, Inc.
    Inventors: Hironobu Hirata, Masayoshi Yajima, Yoshikazu Moriyama
  • Patent number: 9548218
    Abstract: There is disclosed a method of preserving the integrity of a growth substrate in a epitaxial lift-off method, the method comprising providing a structure comprising a growth substrate, one or more protective layers, a sacrificial layer, and at least one epilayer, wherein the sacrificial layer and the one or more protective layers are positioned between the growth substrate and the at least one epilayer; releasing the at least one epilayer by etching the sacrificial layer with an etchant; and heat treating the growth substrate and/or at least one of the protective layers.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 17, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Kyusang Lee, Jeramy Zimmerman, Stephen R. Forrest
  • Patent number: 9508550
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Keun-Ting Shiu, Yanning Sun
  • Patent number: 9484490
    Abstract: An epitaxy substrate (11, 12, 13) for a nitride compound semiconductor material is specified, which has a nucleation layer (2) directly on a substrate (1) wherein the nucleation layer (2) has at least one first layer (21) composed of AlON with a column structure. A method for producing an epitaxy substrate and an optoelectronic semiconductor chip comprising an epitaxy substrate are furthermore specified.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: November 1, 2016
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Joachim Hertkorn, Alexander Frey, Christian Schmid
  • Patent number: 9425249
    Abstract: A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: August 23, 2016
    Assignee: Alliance for Sustainable Energy, LLC
    Inventor: Andrew Norman
  • Patent number: 9406514
    Abstract: The present invention provides a Group III nitride semiconductor light-emitting device having a low drive voltage and a production method therefor. A p-type semiconductor layer formation step comprises a p-type cladding layer formation step of forming a p-side superlattice layer on a light-emitting layer by supplying a first raw material gas containing at least a Group III element and a dopant gas, a p-type intermediate layer formation step of forming a p-type intermediate layer on the p-side superlattice layer by supplying a first raw material gas and a dopant gas, a dopant gas supply step of supplying the dopant gas while stopping the supply of the first raw material gas after the p-type intermediate layer formation step, and a p-type contact layer formation step of forming a p-type contact layer on the p-type intermediate layer by supplying a first raw material gas and a dopant gas after the dopant gas supply step.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 2, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 9385013
    Abstract: Provided is a technique including forming a film by performing a cycle a predetermined number of times. The cycle includes: (a) forming a discontinuous first layer including the first element and having a thickness of less than one atomic layer on the substrate by supplying a gas containing the first element into a process vessel accommodating the substrate; and (b) forming a second layer including the first element and the second element by supplying a gas containing the second element into the process vessel to modify the first layer under a condition where a modifying reaction of the first layer by the gas containing the second element is not saturated.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: July 5, 2016
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yushin Takasawa, Hajime Karasawa, Yoshiro Hirose
  • Patent number: 9368670
    Abstract: Disclosed herein are embodiments of methods for making GaAs thin films, such as photovoltaic GaAs thin films. The methods disclosed herein utilize sources, precursors, and reagents that do not produce (or require) toxic gas and that are readily available and relatively low in cost. In some embodiments, the methods are readily scalable for industrial applications and can provide GaAs thin films having properties that are at least comparable to or potentially superior to GaAs films obtained from conventional methods.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: June 14, 2016
    Assignee: University of Oregon
    Inventors: Shannon Boettcher, Andrew Ritenour, Jason Boucher, Ann Greenaway
  • Patent number: 9343436
    Abstract: A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Li Hsiao, Li-Yen Lin, Chih-Hang Tung
  • Patent number: 9337375
    Abstract: The invention discloses a seed used for crystalline silicon ingot casting. A seed according to a preferred embodiment of the invention includes a crystal and an impurity diffusion-resistant layer. The crystal is constituted by at least one grain. The impurity diffusion-resistant layer is formed to overlay an outer surface of the crystal. A crystalline silicon ingot fabricated by use of the seed of the invention has significantly reduced red zone and yellow zone.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 10, 2016
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Hung-Sheng Chou, Yu-Tsung Chiang, Yu-Min Yang, Ming-Kung Hsiao, Wen-Huai Yu, Sung-Lin Hsu, I-Ching Li, Chung-Wen Lan, Wen-Ching Hsu
  • Patent number: 9330902
    Abstract: A method for forming a HfOx film based on atomic layer deposition (ALD) process includes: providing a substrate; dividing a plurality of ALD cycles as needed into multiple depositing stages, wherein each of the ALD cycles includes applying HfCl4 pulse and applying H2O pulse over the substrate and a content ratio of HfCl4 to H2O is different and increasing for the depositing stages; and performing the depositing stages to form a HfOx film.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 3, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Shih-Cheng Chen, Shan Ye, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9305779
    Abstract: A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the preconditioned silicon substrate is then decreased, and germane gas is flowed over the preconditioned silicon substrate to form an intrinsic germanium seed layer. Next, a mixture of germane and phosphine gases can be flowed over the intrinsic germanium seed layer to produce an n-doped germanium seed layer. Otherwise, a mixture of diborane and germane gases can be flowed over the intrinsic germanium seed layer to produce a p-doped germanium seed layer. At this point, a bulk germanium layer can be grown on top of the doped germanium seed layer.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: April 5, 2016
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Daniel N. Carothers, Craig M. Hill, Andrew T. S. Pomerene, Vu A. Vu
  • Patent number: 9273413
    Abstract: Wafer carrier arranged to hold a plurality wafers and to inject a fill gas into gaps between the wafers and the wafer carrier for enhanced heat transfer and to promote uniform temperature of the wafers. The apparatus is arranged to vary the composition, flow rate, or both of the fill gas so as to counteract undesired patterns of temperature non-uniformity of the wafers. In various embodiments, the wafer carrier utilizes at least one plenum structure contained within the wafer carrier to source a plurality of weep holes for passing a fill gas into the wafer retention pockets of the wafer carrier. The plenum(s) promote the uniformity of the flow, thus providing efficient heat transfer and enhanced uniformity of wafer temperatures.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 1, 2016
    Assignee: Veeco Instruments Inc.
    Inventors: Sandeep Krishnan, Alexander I. Gurary, Keng Moy
  • Patent number: 9240449
    Abstract: A semiconductor device comprises a substrate and quantum dots, wherein a peak emission of the quantum dots has a FWHM of less than 20 meV when the semiconductor is measured at a temperature of 4 Kelvin.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: January 19, 2016
    Inventor: Yu-Chen Chang