Abstract: Magnetic regions of at least one of a chiplet or a receiving substrate are used to permit magnetically guided precision placement of a plurality of chiplets on the receiving substrate. In the present application, a solution containing dispersed chiplets is employed to facilitate the placement of the dispersed chiplets on bond pads that are present on a receiving substrate.

Abstract: A layer I vanadium-doped PIN-type nuclear battery, including from top to bottom a radioisotope source layer(1), a p-type ohm contact electrode(4), a SiO2 passivation layer(2), a SiO2 compact insulation layer(3), a p-type SiC epitaxial layer(5), an n-type SiC epitaxial layer(6), an n-type SiC substrate(7) and an n-type ohm contact electrode(8). The doping density of the p-type SiC epitaxial layer(5) is 1×1019 to 5×1019 cm?3, the doping density of the n-type SiC substrate(7) is 1×1018 to 7×1018 cm?3. The n-type SiC epitaxial layer(6) is a low-doped layer I formed by injecting vanadium ions, with the doping density thereof being 1×1013 to 5×1014 cm?3. Also provided is a preparation method for a layer I vanadium-doped PIN-type nuclear battery. The present invention solves the problem that the doping density of layer I of the exiting SiC PIN-type nuclear battery is high.

Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described., as well as a system for use in performing such a method, and articles incorporating such a composition.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: When a group III nitride crystal is grown in a pressurized atmosphere of a nitrogen-containing gas from a melt 50 including at least a group III element, nitrogen and an alkali metal or an alkali earth metal, a melt-holding vessel 160 that holds the above-described melt 50 is swung about two axes different in direction from each other such as an X-axis and a Y-axis.

Abstract: Apparatus for vapor phase growing of crystals having a single multi-zone heater arranged to heat a heated zone to give a predetermined temperature profile along the length of the heated zone. A generally U-shaped tube having a first limb, a second limb, and a linkage connecting the first and second limbs is located on the heated zone. The first limb contains a source material. The second limb supports a seed such that the source material and seed are spaced longitudinally within the heated zone to provide a predetermined temperature differential between the source and seed. The crystal is grown on the seed.

Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.

Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.

Abstract: Methods of evaluating a superabrasive volume or a superabrasive compact are disclosed. One method may comprise exposing a superabrasive volume to beta particles and detecting a quantity of scattered beta particles. Further, a boundary may be perceived between a first region and a second region of the superabrasive volume in response to detecting the quantity of scattered beta particles. In another embodiment, a boundary between a catalyst-containing region and a catalyst-diminished region of a polycrystalline diamond volume may be perceived. In a further embodiment, a boundary may be perceived between a catalyst-containing region and a catalyst-diminished region of a polycrystalline diamond compact. Additionally, a depth to which a catalyst-diminished region extends within a polycrystalline diamond volume of a polycrystalline diamond compact may be measured in response to detecting a quantity of scattered beta particles. A system configured to evaluate a superabrasive volume is disclosed.

Abstract: A method for growing low-dislocation-density material atop a layer of the material with an initially higher dislocation density using a monolayer of spheroidal particles to bend and redirect or directly block vertically propagating threading dislocations, thereby enabling growth and coalescence to form a very-low-dislocation-density surface of the material, and the structures made by this method.

Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.

Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.

Abstract: Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.

Abstract: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.

Abstract: To provide a manufacturing method of a semiconductor device, comprising: loading a substrate, with a silicon surface exposed at a part of the substrate, into a processing chamber; heating an inside of said processing chamber; performing pre-processing of supplying at least silane-based gas, halogen-based gas, and hydrogen gas into said processing chamber, removing at least a natural oxide film or a contaminated matter that exist on a surface of said silicon surface, and growing an epitaxial film on said silicon surface; and supplying gas containing at least silicon into said processing chamber after said pre-processing, and further growing the epitaxial film on said epitaxial film.

Abstract: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores is provided. The method produces nano-networks made of the non-polar III-V nitride material and the substrate used to grow it where the network is continuous along the surface of the template, and where the nano-pores can be of any shape.

Abstract: The present invention relates to a method for fabricating a filament type high-temperature superconducting wire in which a thin film type high-temperature superconducting wire is fabricated into a filament shape suitable for use with alternating current.

Abstract: An epitaxial growth process for producing a thick III-N layer, wherein III denotes at least one element of group III of the periodic table of elements, is disclosed, wherein a thick III-N layer is deposited above a foreign substrate. The epitaxial growth process preferably is carried out by HVPE. The substrate can also be a template comprising the foreign substrate and at least one thin III-N intermediate layer. The surface quality is improved by providing a slight intentional misorientation of the substrate, and/or a reduction of the N/III ratio and/or the reactor pressure towards the end of the epitaxial growth process. Substrates and semiconductor devices with such improved III-N layers are also disclosed.

Abstract: A diamond single crystal substrate obtained by a vapor-phase growth method, wherein the diamond intrinsic Raman shift of the diamond single crystal substrate surface measured by microscopic Raman spectroscopy with a focused beam spot diameter of excitation light of 2 ?m is deviated by +0.5 cm?1 or more to +3.0 cm?1 or less from the standard Raman shift quantity of strain-free diamond, in a region (region A) which is more than 0% to not more than 25% of the surface, and is deviated by ?1.0 cm?1 or more to less than +0.5 cm?1 from the standard Raman shift quantity of strain-free diamond, in a region (region B) of the surface other than the region A. The diamond single crystal substrate can be obtained with a large size and high-quality without cracking and is suitable for semiconductor materials, electronic components, and optical components or the like.

Abstract: The invention provides systems and methods for the deposition of an improved diamond-like carbon material, particularly for the production of magnetic recording media. The diamond-like carbon material of the present invention is highly tetrahedral, that is, it features a large number of the sp3 carbon-carbon bonds which are found within a diamond crystal lattice. The material is also amorphous, providing a combination of short-range order with long-range disorder, and can be deposited as films which are ultrasmooth and continuous at thicknesses substantially lower than known amorphous carbon coating materials. The carbon protective coatings of the present invention will often be hydrogenated. In a preferred method for depositing of these materials, capacitive coupling forms a highly uniform, selectively energized stream of ions from a dense, inductively ionized plasma.

Abstract: A method for manufacturing a diamond single crystal substrate, in which a single crystal is grown from a diamond single crystal serving as a seed substrate by vapor phase synthesis, said method comprising: preparing a diamond single crystal seed substrate which has a main surface whose planar orientation falls within an inclination range of not more than 8 degrees relative to a {100} plane or a {111} plane, as a seed substrate; forming a plurality of planes of different orientation which are inclined in the outer peripheral direction of the main surface relative to the main surface on one side of this seed substrate, by machining; and then growing a diamond single crystal by vapor phase synthesis.

Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).

Abstract: Hydride phase vapor epitaxy (HVPE) growth apparatus, methods and materials and structures grown thereby. A HVPE growth apparatus includes generation, accumulation and growth zones. A first reactive gas reacts with an indium source inside the generation zone to produce a first gas product having an indium-containing compound. The first gas product is transported to the accumulation zone where it cools and condenses into a source material having an indium-containing compound. The source material is collected in the accumulation zone and evaporated. Vapor or gas resulting from evaporation of the source material forms reacts with a second reactive gas in the growth zone for growth of ternary and quaternary materials including indium gallium nitride, indium aluminum nitride, and indium gallium aluminum nitride.

Abstract: Work from several laboratories has shown that metal nanofilaments cause problems in some molecular electronics testbeds. A new testbed for exploring the electrical properties of single molecules has been developed to eliminate the possibility of metal nanofilament formation and to ensure that molecular effects are measured. This metal-free system uses single-crystal silicon and single-walled carbon nanotubes as electrodes for the molecular monolayer. A direct Si-arylcarbon grafting method is used. Use of this structure with ?-conjugated organic molecules results in a hysteresis loop with current-voltage measurements that are useful for an electronic memory device. The memory is non-volatile for more than 3 days, non-destructive for more than 1,000 reading operations and capable of more than 1,000 write-erase cycles before device breakdown.

Abstract: An object is to provide an ultraviolet light-emitting device in which a p-type semiconductor which has high conductivity and an emission peak in ultraviolet region, and emits light efficiently is used. The p-type semiconductor is prepared by supplying a p-type impurity raw material at the same time or after starting supply of predetermined types of crystal raw materials, besides before starting supply of other types of crystal raw materials than the predetermined types of crystal raw materials in one cycle wherein all the types of crystal raw materials of the plural types of crystal raw materials are supplied in one time each in case of making crystal growth by supplying alternately the plural types of crystal raw materials in a pulsed manner.

Abstract: In some embodiments, the present invention addresses the challenges of fabricating nanorod arrays comprising a heterogeneous composition and/or arrangement of the nanorods. In some embodiments, the present invention is directed to multicomponent nanorod arrays comprising nanorods of at least two different chemical compositions, and to methods of making same. In some or other embodiments, the nanorods are spatially positioned within the array in a pre-defined manner.

Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

Abstract: The invention relates to a device for depositing especially crystalline layers on at least one especially crystalline substrate in a process chamber comprising a top and a vertically opposing heated bottom for receiving the substrates. A gas-admittance body forming vertically superimposed gas-admittance regions is used to separately introduce at least one first and one second gaseous starting material, said starting materials flowing through the process chamber with a carrier gas in the horizontal direction. The gas flow homogenises in an admittance region directly adjacent to the gas-admittance body, and the starting materials are at least partially decomposed, forming decomposition products which are deposited on the substrates in a growth region adjacent to the admittance region, under continuous depletion of the gas flow. An additional gas-admittance region of the gas-admittance body is essential for one of the two starting materials, in order to reduce the horizontal extension of the admittance region.

Abstract: Methods of selectively forming nanocrystals on semiconductor devices are disclosed. Regions of a workpiece are masked with a masking material, and the nanocrystals are formed on the unmasked regions. The nanocrystals may be formed by exposing the masked workpiece to a first substance, and exposing the workpiece to at least one second substance either before or after the masking material is removed.

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract: A method for manufacturing a diamond single crystal substrate, in which a single crystal is grown from a diamond single crystal serving as a seed substrate by vapor phase synthesis, said method comprising: preparing a diamond single crystal seed substrate which has a main surface whose planar orientation falls within an inclination range of not more than 8 degrees relative to a {100} plane or a {111} plane, as a seed substrate; forming a plurality of planes of different orientation which are inclined in the outer peripheral direction of the main surface relative to the main surface on one side of this seed substrate, by machining; and then growing a diamond single crystal by vapor phase synthesis.

Abstract: The invention provides a method to enforce face-to-face stacking of organic semiconductors in the solid state that employs semiconductor co-crystal formers (SCCFs), to align semiconductor building blocks (SBBs). Single-crystal X-ray analysis reveals n-orbital overlap optimal for organic semiconductor device applications.

Abstract: The invention relates to a process for the growth of nanotubes or nanofibers on a substrate comprising at least an upper layer made of a first material, wherein: the formation, on the surface of the upper layer, of a barrier layer made of an alloy of the first material and of a second material, said alloy being stable at a first temperature; the formation of spots of catalyst that are made of the second material, on the surface of the alloy layer; and the growth of nanotubes or nanofibers at a second temperature below said first temperature. The alloy layer allows effective growth of nanotubes/nanofibers from catalyst spots on the surface of said alloy layer. This is because the alloy layer constitutes a diffusion barrier preventing the catalyst from diffusing into the growth substrate, which barrier is stable at the catalytic nanotube/nanofiber growth temperature.

Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

Abstract: Gallium nitride substrates are grown by epitaxial lateral overgrowth using multiple steps. On a masked substrate having openings areas, selective growth produces first triangular stripes in which most of the threading dislocations are bent at 90°. In a second step, growth conditions are changed to increase the lateral growth rate and produce a flat (0001) surface. At this stage the density of dislocations on the surface is <5×107 cm 2. Dislocations are primarily located at the coalescence region between two laterally grown facets pinching off together. To further decrease the dislocation density a second masking step is achieved, with the openings exactly located above the first ones. Threading dislocations (TDs) of the coalescence region do not propagate in the top layer. Therefore the density of dislocations is lowered below <1×107 cm lover the entire surface.

Abstract: A diamond single crystal composite substrate which are constructed from a plurality of diamond single crystal substrates with uniform plane orientations disposed side by side and integrated overall by growing diamond single crystals thereon by vapor phase synthesis, in which the deviation of the plane orientation of the main plane of each of said plurality of diamond single crystal substrates, excluding one diamond single crystal substrate, from the {100} plane is less than 1 degree, the deviation of the plane orientation of the main plane of the excluded one substrate from the {100} plane is 1 to 8 degrees, said one diamond single crystal substrate is disposed in the outermost circumferential part when the diamond single crystal substrates are disposed side by side, and is disposed so that the <100> direction in the main plane of said one substrate faces in the outer circumferential direction of the disposed substrates, and diamond single crystals are then grown by vapor phase synthesis so that the dia

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract: A film structure of a ferroelectric single crystal which can be beneficially used in the fabrication of high-performance electric and electronic parts and devices is prepared by forming an electrode layer having a perovskite crystal structure on a substrate made of a silicon or ferroelectric single crystal optionally polished to have a off-axis crystal structure, and epitaxially growing a layer of a ferroelectric single crystal thereon by pulsed laser deposition (PLD) or metallorganic chemical vapor deposition (MOCVD).

Abstract: A method for producing a large homoepitaxial monocrystalline diamond. The method comprises placing at least two substrates in a substrate holder in a chemical vapor deposition (CVD) chamber. The substrates are positioned in such a manner that the growth faces of the substrates form a wedge. A diamond forming gas is provided adjacent to the substrates in the CVD chamber. The diamond forming gas is exposed to microwave radiation to generate a plasma. Then, the substrates are exposed to the plasma under such conditions that diamond growth occurs in the wedge between the substrates, to form a large homoepitaxial monocrystalline diamond.

Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layer with a thickness of about 2 molecular layers or less.

Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).

Abstract: In a first exemplary embodiment of the present invention, a method is provided for marking a sample of a doped crystalline material. According to a feature of the present invention, the method comprises the steps of causing a controlled alteration to the crystalline material at a preselected spot on the sample of the crystalline material, sufficient to cause a change in a cathodoluminescence spectrum of the crystalline material at the preselected spot and utilizing the altered cathodoluminescence spectrum to mark the crystalline material.

Abstract: Patterned zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. The seed layer is patterned, such as by etching, and growth of at least one zinc-oxide nanostructure is induced substantially over the patterned seed layer by, for example, exposing the patterned seed layer to zinc vapor in the presence of a trace amount of oxygen. The seed layer can alternatively be formed by using a spin-on technique, such as a metal organic deposition technique, a spray pyrolisis technique, an RF sputtering technique or by oxidation of a zinc thin film layer formed on the substrate.

Abstract: Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations from neighboring regions, accumulate the dislocations into pit bottoms, and make closed defect accumulating regions (H) on the seeds. The polycrystalline or slanting orientation single crystal closed defect accumulating regions (H) induce microcracks due to thermal expansion anisotropy. The best one is orientation-inversion single crystal closed defect accumulating regions (H). At an early stage, orientation-inverse protrusions are induced on tall facets and unified with each other above the seeds. Orientation-inverse crystals growing on the unified protrusions become the orientation-inverse single crystal closed defect accumulating regions (H).

Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

Abstract: A method for fabricating an epitaxial substrate. The technique includes providing a crystalline or mono-crystalline base substrate, implanting atomic species into a front face of the base substrate to a controlled mean implantation depth to form a zone of weakness within the base substrate that defines a sub-layer, and growing a stiffening layer on a front face of the base substrate by using a thermal treatment in a first temperature range. The stiffening layer has a thickness sufficient to form an epitaxial substrate. In addition, the method includes detaching the stiffening layer and the sub-layer from the base substrate by using a thermal treatment in a second temperature range higher than the first temperature range. An epitaxial substrate and a remainder of the base substrate are obtained. The epitaxial substrate is suitable for use in growing high quality homoepitaxial or heteroepitaxial films thereon.

Abstract: The present invention provides a method of manufacturing Group III nitride crystals that are of high quality, are manufactured efficiently, and are useful and usable as a substrate for semiconductor manufacturing processes. A semiconductor layer that is made of a semiconductor and includes crystal-nucleus generation regions at its surface is formed. The semiconductor is expressed by a composition formula of AluGavIn1-u-vN (where 0?u?1, 0?v?1, and u+v?1). Group III nitride crystals then are grown on the semiconductor layer by bringing the crystal-nucleus generation regions of the semiconductor layer into contact with a melt in an atmosphere including nitrogen. The melt contains nitrogen, at least one Group III element selected from the group consisting of gallium, aluminum, and indium, and at least one of alkali metal and alkaline-earth metal.

Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 ?, a length in the range of 1000 ? to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 ?.

Abstract: The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites.

Abstract: A method for forming an array of zinc oxide nanowires on a substrate is disclosed, which includes forming a crystal phase adjusting buffer on the surface of the substrate and growing 1D zinc oxide nanowires on the buffer by zinc vapor deposition, which are normal to the surface of the substrate. The crystal phase adjusting buffer includes, for example, nitride and oxide layers on a silicon substrate, or a gallium nitride epitaxial layer on a sapphire substrate, and is used as a growth buffer layer for the zinc oxide nanowires. The zinc vapor phase deposition includes forming a zinc oxide layer on the crystal phase adjusting buffer and forming vertical zinc oxide nanowires on the zinc oxide layer.