For Autodoping Control Patents (Class 117/96)
  • Patent number: 7229499
    Abstract: A manufacturing method for a semiconductor device formed in a device region composed of a plurality of semiconductor layers on a substrate, the method including a trench forming step of forming a trench on the substrate around the device region and a semiconductor growth step of growing the semiconductor layer in the device region.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: June 12, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masahiro Ishida
  • Patent number: 7226509
    Abstract: A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent processing, and detaching the stiffening layer from the base substrate to obtain the carrier substrate and a remainder of the base substrate. The carrier substrate is suitable for use in growing high quality homo-epitaxial or hetero-epitaxial films thereon.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: June 5, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Bruce Faure
  • Patent number: 7208044
    Abstract: This invention disclosure describes methods for the fabrication metal oxide films on surfaces by topotactic anion exchange, and laminate structures enabled by the method. A precursor metal-nonmetal film is deposited on the surface, and is subsequently oxidized via topotactic anion exchange to yield a topotactic metal-oxide product film. The structures include a metal-oxide layer(s) and/or a metal-nonmetal layer(s).
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: April 24, 2007
    Inventor: Mark A. Zurbuchen
  • Patent number: 7115166
    Abstract: A method of forming (and apparatus for forming) a layer, such as a strontium titanate, barium titanate, or barium-strontium titanate layer, on a substrate by employing a vapor deposition method, particularly a multi-cycle atomic layer deposition process.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brian A. Vaartstra, Stefan Uhlenbrock
  • Patent number: 7101435
    Abstract: Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: September 5, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Jingyan Zhang, Er-Xuan Ping
  • Patent number: 7097708
    Abstract: This invention concerns nanoscale products, such as electronic devices fabricated to nanometer accuracy. It also concerns atomic scale products. These products may have an array of electrically active dopant atoms in a silicon surface, or an encapsulated layer of electrically active donor atoms. In a further aspect the invention concerns a method of fabricating such products. The methods include forming a preselected array of donor atoms incorporated into silicon. Encapsulation by growing silicon over a doped surface, after desorbing the passivating hydrogen. Also, using an STM to view donor atoms on the silicon surface during fabrication of a nanoscale device, and measuring the electrical activity of the donor atoms during fabrication of a nanoscale device. Such products and processes are useful in the fabrication of a quantum computer, but could have many other uses.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: August 29, 2006
    Assignee: Qucor Pty Ltd.
    Inventors: Robert Graham Clark, Neil Jonathan Curson, Toby Hallam, Lars Oberbeck, Steven Richard Schofield, Michelle Yvonne Simmons
  • Patent number: 7077903
    Abstract: Methods for generating a nanostructure and for enhancing etch selectivity, and a nanostructure are disclosed. The invention implements a tunable etch-resistant anti-reflective (TERA) material integration scheme which gives high etch selectivity for both etching pattern transfer through the TERA layer (used as an ARC and/or hardmask) with etch selectivity to the patterned photoresist, and etching to pattern transfer through a dielectric layer of nitride. This is accomplished by oxidizing a TERA layer after etching pattern transfer through the TERA layer to form an oxidized TERA layer having chemical properties similar to oxide. The methods provide all of the advantages of the TERA material and allows for high etch selectivity (approximately 5–10:1) for etching to pattern transfer through nitride. In addition, the methodology reduces LER and allows for trimming despite reduced photoresist thickness.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Katherina E. Babich, Scott D. Halle, David V. Horak, Arpan P. Mahorowala, Wesley C. Natzle, Dirk Pfeiffer, Hongwen Yan
  • Patent number: 7025826
    Abstract: Methods for biaxially-texturing a surface-region of an amorphous material are disclosed, comprising depositing an amorphous material onto a substrate, and supplying active oxygen near the substrate during ion beam bombardment of the amorphous material to create an amorphous material having a biaxially textured surface, wherein the ion beam bombardment occurs at a predetermined oblique incident angle. Methods for producing high-temperature coated superconductors are also disclosed, comprising depositing an amorphous buffer film onto a metal alloy substrate, bombarding a surface-region of the amorphous buffer film with an ion beam at an oblique incident angle while supplying active oxygen to the surface-region of the amorphous buffer film in order to create a biaxially textured surface-region thereon, and growing a superconducting film on the biaxially textured surface-region of the amorphous buffer film to create a high-temperature coated superconductor.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: April 11, 2006
    Assignee: Superpower, Inc.
    Inventors: Venkat Selvamanickam, Xuming Xiong
  • Patent number: 7022191
    Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, and a heater at the substrate support wherein the heater supplies the substrate with heat.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: April 4, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Jin Jang, Soo-Young Yoon, Jae-Young Oh, Woo-Sung Shon, Seong-Jin Park
  • Patent number: 6802902
    Abstract: A process for producing an epitaxial layer of gallium nitride (GaN). A film of a dielectric whose thickness is about one monolayer is formed on a surface of a substrate. A continuous gallium nitride layer is then deposited on the dielectric film at a temperature sufficiently low to suppress island formation of the gallium nitride. The deposited gallium nitride layer is annealed at a temperature sufficiently high to promote island formation of the gallium nitride. An epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride then takes place. This method makes it possible to avoid having to use ex situ etching of masks by photolitographiy or chemical ethching techniques.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: October 12, 2004
    Assignee: Lumilog
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6790279
    Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: September 14, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai
  • Patent number: 6776842
    Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: August 17, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Patrick Jerier
  • Patent number: 6666916
    Abstract: A mandrel for use in a diamond deposition process has surfaces with different diamond adhesion properties. According to one embodiment, a mandrel is provided and has first and second surfaces on which a diamond film is deposited, with the second surface forming a perimeter around the first surface. The first surface of the mandrel has a first diamond bonding strength which is less than a second diamond bonding strength of the second surface. In an embodiment for forming a cup-shaped diamond film, the mandrel is a titanium nitride (TiN) coated molybdenum (Mo) substrate having a stepped solid cylindrical shape with a central mesa having a side wall or flank. The side wall is etched near the top surface of the mesa to expose a molybdenum band and to form a second surface which bounds the TiN first surface.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: December 23, 2003
    Assignee: Saint-Gobain/Norton Industrial Ceramics Corporation
    Inventors: Randy D. Fellbaum, Volker R. Ulbrich
  • Patent number: 6645295
    Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: November 11, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai
  • Patent number: 6589333
    Abstract: A method is described for the production of a suitable substrate for the subsequent growth of a mono-crystalline diamond layer. This method includes the following steps: Selection of a substrate of a mono-crystalline material having a fixed lattice constant (aSi) or with a layer consisting of such a material. Manufacture of a strained silicon layer with foreign material atoms incorporated at substitutional lattice sites on the mono-crystalline material of the substrate. Transfer of the strained layer into an at least partly relaxed state in which it adopts by relaxation and through the selected foreign material concentration a lattice constant (aSi(C) which satisfies the condition n.aSi(C)=m.aD, wherein n and m are integers and aD is the lattice constant of diamond, with the relaxed layer forming the substrate or substrate surface for the epitaxial growth.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Ulrich Gösele, Andreas Plössl
  • Patent number: 6530991
    Abstract: A method for the formation of a semiconductor layer by which a defect density of structural defects, particularly a dislocation density of threading dislocations in the resulting semiconductor layer can be remarkably reduced, so that hours of work can be shortened as well as a manufacturing cost can be reduced without requiring any complicated process comprises supplying a structural defect suppressing material for suppressing structural defects in the semiconductor layer onto a surface of the layer of a material from which the semiconductor layer is to be formed.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: March 11, 2003
    Assignees: Riken
    Inventors: Satoru Tanaka, Misaichi Takeuchi, Yoshinobu Aoyagi
  • Patent number: 6468348
    Abstract: An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 22, 2002
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Grüning, Hermann Wendt, Volker Lehmann, Reinhard Stengl, Hans Reisinger
  • Patent number: 6428635
    Abstract: An alloy capable of forming a (100) [001] cube-texture by thermo-mechanical techniques has 5 to 45 atomic percent nickel with the balance being copper. The alloy is useful as a conductive substrate for superconducting composites where the substrate is coated with a superconducting oxide. A buffer layer can optionally be coated on the substrate to enhance deposition of the superconducting oxide. Methods for producing the alloys, substrates, and superconductors are included.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: August 6, 2002
    Assignees: American Superconductor Corporation, The Regents of the University of California
    Inventors: Leslie G. Fritzemeier, Elliott D. Thompson, Edward J. Siegal, Cornelis Leo Hans Thieme, Robert D. Cameron, James L. Smith, W. Larry Hults
  • Patent number: 6358313
    Abstract: A method of manufacturing a crystalline silicon base semiconductor thin film on a substrate, includes the steps of forming a thin film primarily made of silicon on the substrate by forming plasma of a film material gas containing at least a silicon base gas at the vicinity of the substrate; and crystallizing the silicon in the thin film primarily made of the silicon by emitting excited particles produced from an excited particle material gas to the substrate. At least one of the film material gas and the excited particle material gas contains an impurity gas for forming the silicon semiconductor, and thereby the crystalline silicon base semiconductor thin film is formed on the substrate.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 19, 2002
    Assignees: Sharp Kabushiki Kaisha, Nissin Electric Co., Ltd.
    Inventors: Shuhei Tsuchimoto, Hirohisa Tanaka, Kiyoshi Ogata, Hiroya Kirimura
  • Patent number: 6325850
    Abstract: The invention concerns a method for producing a gallium nitride (GaN) epitaxial layer characterised in that it consists in depositing on a substrate a dielectric layer acting as a mask and depositing on the masked gallium nitride, by epitaxial deposit, so as to induce the deposit of gallium nitride patterns and the anisotropic lateral growth of said patterns, the lateral growth being pursued until the different patterns coalesce. The deposit of the gallium nitride patterns can be carried out ex-situ by dielectric etching or in-situ by treating the substrate for coating it with a dielectric film whereof the thickness is of the order of one angstrom. The invention also concerns the gallium nitride layers obtained by said method.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: December 4, 2001
    Assignee: Centre National de la Recherché Scientifique (CNRS)
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6315826
    Abstract: Disclosed are a structure of a semiconductor substrate and a method of manufacturing the semiconductor substrate preventing a reduction of gettering capability due to a high-temperature heat treatment. In a semiconductor substrate containing a highly concentrated impurity having a polysilicon layer to be a gettering site on a rear surface side and an epitaxial layer 6 on a front surface side, an impurity concentration is lower near the rear and front surfaces and higher at the center in a cross section of the semiconductor substrate. The method of manufacturing the semiconductor substrate comprises the steps of: performing the heat treatment of a silicon substrate at a temperature of 1100° C. or more and a melting temperature or less of the silicon substrate before forming the polysilicon layer 4 and the epitaxial layer 6; forming the polysilicon layer 4 on the rear surface side of the silicon substrate; and forming the epitaxial layer 6 on the front surface side of the silicon substrate.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Satoru Muramatsu
  • Patent number: 6294019
    Abstract: In the present method, a group III-V compound semiconductor wafer includes a substrate consisting of a group III-V compound whose outer peripheral edge portion is so chamfered that its section has an arcuate shape substantially with a radius R, and an epitaxial layer consisting of a group III-V compound layer formed on the substrate. A portion of the wafer is removed at the outer peripheral edge thereof, up to a distance L from the original peripheral edge, and the distance L satisfies the expression R≦L≦3L. thereby an abnormally grown part of the epitaxial layer is reliably removed.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: September 25, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Miura, Toshiyuki Morimoto
  • Patent number: 6294018
    Abstract: The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: September 25, 2001
    Assignee: Lucent Technologies
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
  • Patent number: 6254676
    Abstract: A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: July 3, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Michael W C Huang, Chien Chao Huang, Hsien-Ta Chung, Tri-Rung Yew
  • Patent number: 6168659
    Abstract: With an object of providing gallium nitride thick film crystals excelling in crystallization, the structure thereof is formed of an amorphous silicon dioxide thin film 2 formed on a silicon substrate 1 and then a single crystal silicon thin film 3 is formed on the foregoing amorphous silicon dioxide thin film 2 and further gallium nitride 4 is formed on this silicon thin film 3.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Masaaki Yuri, Tetsuzo Ueda, Takaaki Baba
  • Patent number: 6110278
    Abstract: A template for seeding growth of a desired single-crystal material (e.g., Si, GaAs) is created by passing through a monocrystalline channelizing mask, in a channelizing direction thereof, at least one of a nucleation-friendly species (e.g., Si, Ga) and a knock-off species (e.g., Ar, F) for respective implant of a nucleation-friendly species within or removal of a nucleation-unfriendly material (e.g., SiO.sub.2) of a supplied substrate. The desired single-crystal material is then grown in epitaxial-like manner from the thus-formed seeding-template. In one embodiment, silicon ions are projected through a monocrystalline silicon mask of a selected crystal orientation ((100), or (111)) in its channelizing direction so as to implant the silicon ions in a silicon dioxide layer of a supplied substrate according to the selected crystal orientation of the channelizing mask. Monocrystalline silicon is then epitaxially grown on top of the silicon dioxide layer with the same crystal orientation.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: August 29, 2000
    Inventor: Arjun N. Saxena
  • Patent number: 6103019
    Abstract: A method for producing a pattern of regularly spaced-apart nucleation sites and corresponding devices are disclosed. The method enables formation of a device having an amorphous or otherwise non-single crystal surface from which single crystal layers of a desired orientation may be grown using the regularly spaced nucleation sites as a growth template. The method can be used to produce a single crystal semiconductor layer of a desired orientation (e.g., <100> or <111>) on an amorphous insulating layer (e.g. of SiO.sub.2 or Si.sub.3 N.sub.4). For example, single crystal Si of a <100> orientation may be grown on an SiO.sub.2 layer. Monocrystalline semiconductor films may be similarly grown on amorphous glass substrates or the like for producing solar cells of high efficiency and low cost.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: August 15, 2000
    Inventor: Arjun Saxena
  • Patent number: 6007624
    Abstract: A method for controlling the autodoping during epitaxial silicon deposition. First, the substrate (10) is cleaned to remove any native oxide. After being cleaned, the substrate (10) is transferred to the deposition chamber in an inert or vacuum atmosphere to inhibit the growth of a native oxide on the surface of the wafers. A lower temperature (i.e., 500-850.degree. C.) capping layer (14) is deposited to prevent autodoping. Then, the temperature is increased to the desired deposition temperature and the remainder of the epitaxial layer (18) is deposited.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: December 28, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Rick L. Wise
  • Patent number: 5891242
    Abstract: An apparatus for and a method of determining the epitaxial layer thickness and transition width in epitaxial single crystal silicon wafers are provided. The apparatus provides an epitaxial single crystal silicon wafer comprising an isotopically enriched doped substrate. The method involves a process of applying Second Ion Mass Spectrometry (SIMS) to the isotopically enriched doped wafer for determining its epitaxial layer thickness and transition width.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: April 6, 1999
    Assignee: Seh America, Inc.
    Inventors: William Charles Pesklak, Bruce Laurence Colburn
  • Patent number: 5882400
    Abstract: The invention concerns a method of producing a surface layer structure by doping a matrix with metal ions. The aim of the invention is to provide a method of this kind in which the depth distribution of the metal ions in the substrate can be regulated, thus optimumizing the doping without incurring any of the disadvantages inherent in the prior art methods. This is achieved by first depositing matrix material on a suitable substrate by laser ablation in an atmosphere of oxygen, thus forming a on surface of the substrate a first layer a matrix material. Dopant is then deposited on the surface of the first layer, followed by more matrix material. The result is a uniform doping of the deposited matrix at a defined depth in the surface layer structure.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: March 16, 1999
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Stefanie Bauer, Martin Fleuster, Willi Zander, Jurgen Schubert, Christoph Buchal
  • Patent number: 5843224
    Abstract: The invention relates to a composite structure including a semiconductor layer arranged on a diamond layer and/or a diamond-like layer, for subsequent processing to produce electronic components and/or groups of components and to a process for producing such a composite structure. In order to improve the quality of the subsequent components, the diamond layer is deposited underneath the component source zones from which the components are subsequently produced, and the diamond or diamond-like layer is provided at the margins of the component source zones and/or outside of the component source zones with edges where the thickness of the layer changes abruptly such that the edges have an edge height amounting to at least 1O%, preferably at least 50%, of the layer thickness of the diamond layer.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: December 1, 1998
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventors: Reinhard Zachai, Tim Gutheit, Kenneth Goodson
  • Patent number: 5709745
    Abstract: A method of controlling the amount of impurity incorporation in a crystal grown by a chemical vapor deposition process. Conducted in a growth chamber, the method includes the controlling of the concentration of the crystal growing components in the growth chamber to affect the demand of particular growth sites within the growing crystal thereby controlling impurity incorporation into the growth sites.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: January 20, 1998
    Assignee: Ohio Aerospace Institute
    Inventors: David J. Larkin, Philip G. Neudeck, J. Anthony Powell, Lawrence G. Matus
  • Patent number: 5696004
    Abstract: A method of producing a semiconductor device having a high concentration N-type buried layer on a P-type silicon substrate, the buried layer being covered with a P-type silicon epitaxial layer. The method comprises forming a P-type high concentration layer at a surface portion of the silicon substrate in a region in which no N-type buried layer is to be formed, thereby preventing an inversion layer from being formed at the boundary between the silicon substrate and the epitaxial layer.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: December 9, 1997
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Nobuhiro Kanai
  • Patent number: 5653802
    Abstract: A method for forming a crystal comprises implanting ions on the surface of a substrate to change the ion concentration in the depth direction of said substrate surface by said ion implantation, subjecting a desired position of said substrate surface with a sufficient area for crystal growth from a single crystal to exposure treatment to/he depth where an exposed surface having larger nucleation density than the nucleation density of the surface of said substrate is exposed, thereby forming a nucleation surface comprising said exposed surface exposed by said exposure treatment and a nonnucleation surface comprising the surface of the substrate remaining without subjected to said exposure treatment, applying a crystal growth treatment for crystal growth from a single nucleus on said substrate to grow a single crystal from said single nucleus or form a polycrystal of a mass of single crystals grown from said single nucleus.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: August 5, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 5562770
    Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: October 8, 1996
    Assignee: International Business Machines Corporation
    Inventors: Bomy A. Chen, Terence B. Hook, Subhash B. Kulkarni
  • Patent number: 5423286
    Abstract: A method for forming a crystal comprises applying a crystal growth treatment to a substrate comprising:a non-nucleation surface; anda nucleation surface constituted of an amorphous material with a higher nucleation density than said non-nucleation surface, having a sufficiently small area so as to form only a single nucleus from which a single crystal is grown, and having regular anisotropy.Also a crystal article is formed by said method for forming a crystal.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: June 13, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara