Coating (e.g., Masking, Implanting) Patents (Class 117/95)
  • Patent number: 10403509
    Abstract: A method for removing existing basal plane dislocations (BPDs) from silicon carbide epilayers by using a pulsed rapid thermal annealing process where the BPDs in the epilayers were eliminated while preserving the epitaxial surface. This high temperature, high pressure method uses silicon carbide epitaxial layers with a carbon cap to protect the surface. These capped epilayers are subjected to a plurality of rapid heating and cooling cycles.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: September 3, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Marko J. Tadjer, Boris N. Feigelson, Nadeemullah A. Mahadik, Robert E. Stahlbush, Eugene A. Imhoff, Jordan Greenlee
  • Patent number: 10354865
    Abstract: A method for procuring a nitride compound semiconductor device is disclosed. In an embodiment the method includes growing a first nitride compound semiconductor layer onto a growth substrate, depositing a masking layer, growing a second nitride compound semiconductor layer onto the masking layer, growing a third nitride compound semiconductor layer onto the second nitride compound semiconductor layer such that the third nitride compound semiconductor layer has non-planar structures and growing a fourth nitride compound semiconductor layer onto the non-planar structures such that the fourth nitride compound semiconductor layer has an essentially planar surface. The method further includes growing a functional layer sequence of the nitride compound semiconductor device, connecting a side of the functional layer sequence located opposite to the growth substrate to a carrier and removing the growth substrate.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: July 16, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Lorenzo Zini, Alexander Frey
  • Patent number: 10354870
    Abstract: First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: July 16, 2019
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann Bogumilowicz, Jean-Michel Hartmann
  • Patent number: 10329689
    Abstract: A subject of present invention is to enable reducing, even in growth at a high C/Si ratio, contamination by different polytypes with respect to a silicon carbide epitaxial wafer having a low off-angle, and to provide the silicon carbide epitaxial wafer which enables forming a reliable high voltage silicon carbide semiconductor element. The silicon carbide epitaxial wafer of the present invention is a silicon carbide epitaxial wafer comprising an epitaxially grown layer disposed on a silicon carbide substrate having an ?-type crystal structure and an off-angle tilted at an angle of more than 0° and less than 4° from a (0001) Si plane or a (000-1) C plane, wherein a region of a step bunching including five to ten bunched steps of 1 nm in height occupies 90% or more of the surface of the silicon carbide substrate.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 25, 2019
    Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventor: Keiko Masumoto
  • Patent number: 10325774
    Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Benjamin Chu-Kung, Marko Radosavljevic, Sanaz K. Gardner, Seung Hoon Sung, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 10309037
    Abstract: The present invention relates to the production of III-N templates and also the production of III-N single crystals, III signifying at least one element of the third main group of the periodic table, selected from the group of Al, Ga and In. By adjusting specific parameters during crystal growth, III-N templates can be obtained that bestow properties on the crystal layer that has grown on the foreign substrate which enable flawless III-N single crystals to be obtained in the form of templates or even with large III-N layer thickness.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 4, 2019
    Assignee: Freiberger Compound Materials GMBH
    Inventors: Frank Lipski, Ferdinand Scholz, Martin Klein, Frank Habel
  • Patent number: 10287625
    Abstract: Disclosed are methods and kits for isolating nucleic acids having a size above a desired cut-off size from a nucleic acid containing sample. The method comprises combining the sample with a binding buffer, alcohol and silicon carbide to provide a binding mixture. Nucleic acids having a size above the desired cut-off size are selectively bound to the silicon carbide. The cut-off size for selective binding to the silicon carbide is determined by the alcohol concentration of the binding mixture. The bound nucleic acids are separated from the remaining sample. The bound nucleic acids are optionally washed and then eluted from the silicon carbide. The kit comprises a buffer binding to be diluted with alcohol to provide an alcohol concentration of about 1 to about 50% (v/v), a wash solution, an elution solution, silicon carbide and instructions for adjusting the alcohol concentration to selectively bind nucleic acids having a size above the desired cut-off size.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: May 14, 2019
    Assignee: Norgen Biotek Corp.
    Inventor: Yousef Haj-Ahmad
  • Patent number: 10256093
    Abstract: Systems and methods for growing semiconductor materials on substrates by using patterned sol-gel materials are provided. According to a first aspect of the invention, a method includes forming a pattern of a sol-gel material on a first region of substrate, and depositing a semiconductor material on a second region of the substrate by selective area growth. The second region is adjacent to the first region.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Emily L. Warren, Adele Clare Tamboli
  • Patent number: 10249493
    Abstract: A method for depositing a layer on a semiconductor wafer by vapor deposition in a process chamber, involves removing native oxide from a surface of the wafer; and then depositing an epitaxial layer with a thickness of at least 40 ?m on the surface of the wafer by introducing a silicon containing gas and a carrier gas into the process chamber, wherein the flow rate of the silicon containing gas is lower than 10 standard liters per minute and the flow rate of the carrier gas is at least 40 standard liters per minute.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 2, 2019
    Assignee: SILTRONIC AG
    Inventors: Wilhelmus Aarts, Jason Van Horn, Randal Gieker
  • Patent number: 10170312
    Abstract: Present disclosure provides a method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, including providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type, forming a polysilicon layer over the front surface, removing the polysilicon layer from the front surface, and depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature. A transition width of the dopant having the first conductivity type across the semiconductor wafer and the epitaxial layer is controlled by the predetermined temperature to be at least about 0.75 micrometer. A semiconductor device and a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer are also disclosed.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Pu-Fang Chen, Wei-Zhe Chang, Shi-Jieh Lin, Victor Y. Lu
  • Patent number: 10014291
    Abstract: A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kong-Beng Thei, Jiun-Lei Jerry Yu, Chun Lin Tsai, Hsiao-Chin Tuan, Alex Kalnitsky
  • Patent number: 9945026
    Abstract: A sintered compact sputtering target in which a composition ratio based on atomicity is represented by a formula of (Fe100-x—Ptx)100-A—CA (provided A is a number which satisfies 20?A?50 and X is a number which satisfies 35?X?55), wherein C grains are finely dispersed in an alloy, and the relative density is 90% or higher. The production of a magnetic thin film with granular structure is provided without using an expensive simultaneous sputtering device, and a high-density sputtering target capable of reducing the amount of particles generated during sputtering is provided.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: April 17, 2018
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Atsushi Sato, Shin-ichi Ogino
  • Patent number: 9882010
    Abstract: A silicon carbide substrate includes a Si substrate (silicon substrate), a SiC base film (silicon carbide base film) which is stacked on the Si substrate and contains silicon carbide, a defective part (through-hole) which passes through the SiC base film, a hole which is located between the Si substrate and the SiC base film corresponding to the defective part, and an oxide film which is provided on the surface of the Si substrate in the hole and contains silicon oxide. Further, on the SiC base film, a SiC grown layer (silicon carbide grown layer) may be formed.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 30, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Yukimune Watanabe
  • Patent number: 9812527
    Abstract: Graphene is used as an interfacial layer to grow Si and other semiconductors or crystalline materials including two-dimensional Si and other structures on any foreign substrate that can withstand the growth temperature without the limitation matching condition typically required for epitaxial growth.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 7, 2017
    Assignee: THE UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE
    Inventors: Yong Zhang, Raphael Tsu, Naili Yue
  • Patent number: 9809903
    Abstract: A method of forming a TMDC monolayer comprises providing a multi-layer transition metal dichalcogenide (TMDC) film. The multi-layer TMDC film comprises a plurality of layers of the TMDC. The multi-layer TMDC film is positioned on a conducting substrate. The conducting substrate is contacted with an electrolyte solution. A predetermined electrode potential is applied on the conducting substrate and the TMDC monolayer for a predetermined time. A portion of the plurality of layers of the TMDC included in the multi-layer TMDC film is removed by application of the predetermined electrode potential, thereby leaving a TMDC monolayer film positioned on the conducting substrate.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: UChicago Argonne, LLC
    Inventors: Saptarshi Das, Mrinal K. Bera, Andreas K. Roelofs, Mark Antonio
  • Patent number: 9761446
    Abstract: Methods of producing arrays of thin crystal grains of layered semiconductors, including the creation of stable atomic-layer-thick to micron-thick membranes of crystalline semiconductors by chemical vapor deposition.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: September 12, 2017
    Assignee: UNIVERSITY OF HOUSTON SYSTEM
    Inventors: Haibing Peng, Guoxiong Su, Debtanu De
  • Patent number: 9691953
    Abstract: A light emitting element includes a semiconductor stack including an n-side semiconductor layer, and a p-side semiconductor layer disposed in a portion of an area above the n-side semiconductor layer, the semiconductor stack having a plurality of first lateral surfaces and a plurality of second lateral surfaces; an n-pad electrode disposed in an area different from an area where the p-side semiconductor layer is disposed above the n-side semiconductor layer, the n-pad electrode being electrically connected to the n-side semiconductor layer, and the n-pad electrode having a plurality of lateral surfaces that oppose the first lateral surfaces of the semiconductor stack; a first light transmissive film disposed in contact with the first lateral surfaces of the semiconductor stack; and a second light transmissive film disposed in contact with the second lateral surfaces of the semiconductor stack.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: June 27, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Hiroki Kondo
  • Patent number: 9680055
    Abstract: A hetero-substrate, a nitride-based semiconductor light emitting device, and a method of manufacturing the same are provided. The hetero-substrate may include a substrate including a silicon semiconductor, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including a nitride semiconductor, a second semiconductor layer disposed on the first semiconductor layer and including a first conductive type nitride semiconductor having a first doping concentration, and a stress control structure disposed between the first semiconductor layer and the second semiconductor layer and including at least one stress compensation layer and at least one third semiconductor layer including a first conductive type nitride semiconductor having a second doping concentration that is the same or lower than the first doping concentration.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: June 13, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Kiseong Jeon, Hojun Lee, Kyejin Lee
  • Patent number: 9673047
    Abstract: A method of making a SiC buffer layer on a Si substrate comprising depositing an amorphous carbon layer on a Si(001) substrate, controlling the thickness of the amorphous carbon layer by controlling the time of the step of depositing the amorphous carbon layer, and forming a deposited film. A 3C—SiC buffer layer on Si(001) comprising a porous buffer layer of 3C—SiC on a Si substrate wherein the porous buffer layer is produced through a solid state reaction.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: June 6, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Connie H. Li, Glenn G. Jernigan, Berend T. Jonker, Ramasis Goswami, Carl S. Hellberg
  • Patent number: 9410265
    Abstract: Semiconductor wafers composed of silicon with an epitaxially deposited layer, are prepared by: placing a dummy wafer on a susceptor of an epitaxy reactor; conducting an etching gas through the epitaxy reactor in order to remove residues on surfaces in the epitaxy reactor through the action of the etching gas; conducting a first deposition gas through the epitaxy reactor in order to deposit silicon on surfaces in the epitaxy reactor; replacing the dummy wafer by a substrate wafer composed of silicon; and conducting a second deposition gas through the epitaxy reactor in order to deposit an epitaxial layer on the substrate wafer.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 9, 2016
    Assignee: SILTRONIC AG
    Inventors: Christian Hager, Thomas Loch, Norbert Werner
  • Patent number: 9406564
    Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Johannes Baumgartl, Manfred Kotek, Hans-Joachim Schulze
  • Patent number: 9337027
    Abstract: This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 10, 2016
    Assignee: Dow Corning Corporation
    Inventors: Gilyong Chung, Mark Loboda
  • Patent number: 9255346
    Abstract: A system for depositing thin single crystal silicon wafers by epitaxial deposition in a silicon precursor depletion mode with cross-flow deposition may include: a substrate carrier with low total heat capacity, high emissivity and small volume; a lamp module with rapid heat-up, efficient heat production, and spatial control over heating; and a manifold designed for cross-flow processing. Furthermore, the substrate carrier may include heat reflectors to control heat loss from the edges of the carrier and/or heat chokes to thermally isolate the carrier from the manifolds, allowing independent temperature control of the manifolds. The carrier and substrates may be configured for deposition on both sides of the substrates—the substrates having release layers on both sides and the carriers being configured to have equal process gas flow over both surfaces of the substrate. High volume may be addressed by a deposition system comprising multiple mini-batch reactors.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 9, 2016
    Assignee: Crystal Solar, Incorporated
    Inventors: Visweswaren Sivaramakrishnan, Tirunelveli S. Ravi, Andrzej Kaszuba, Bozena Kaszuba, Quoc Vinh Truong, Jean R. Vatus
  • Patent number: 9245747
    Abstract: A method for releasing a semiconductor layer with a reduced active area from a base substrate is provided. A patterned release layer is first formed between a semiconductor layer comprised of an III-V compound semiconductor material and formed by a lateral epitaxial overgrowth technique and a base substrate. The patterned release layer is in contact with a Group III nitride surface. The patterned release layer is composed of a material having a lower fracture toughness than that of the III-V compound semiconductor material and that of the base substrate so that a crack will initiate in the pattern release layer during the controlled spalling process. The semiconductor layer is released from the underlying base substrate along a spalling plane located at a portion of the semiconductor layer enclosing the patterned release layer and the base substrate.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: January 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 9171717
    Abstract: The non-polar or semi-polar group III nitride layer disclosed in a specific example of the present invention can be used for substrates for various electronic devices, wherein problems of conventional polar group III nitride substrates are mitigated or solved by using the nitride substrate of the invention, and further the nitride substrate can be manufactured by a chemical lift-off process.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 27, 2015
    Assignee: KOREA PHOTONICS TECHNOLOGY INSTITUTE
    Inventors: Jin Woo Ju, Jong Hyeob Baek, Hyung Jo Park, Sang Hern Lee, Tak Jung, Ja Yeon Kim, Hwa Seop Oh, Tae Hoon Chung, Yoon Seok Kim, Dae Woo Jeon
  • Patent number: 9159553
    Abstract: A dislocation-free high quality template with relaxed lattice constant, fabricated by spatially restricting misfit dislocation(s) around heterointerfaces. This can be used as a template layer for high In composition devices. Specifically, the present invention prepares high quality InGaN templates (In composition is around 5-10%), and can grow much higher In-composition InGaN quantum wells (QWs) (or multi quantum wells (MQWs)) on these templates than would otherwise be possible.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: October 13, 2015
    Assignee: The Regents of the University of California
    Inventors: Hiroaki Ohta, Feng Wu, Anurag Tyagi, Arpan Chakraborty, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Erin C. Young
  • Patent number: 9153645
    Abstract: A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jizhong Li, Anthony J. Lochtefeld
  • Patent number: 9130036
    Abstract: A semiconductor device includes: a substrate with an off-angle; an SiC layer provided on a principal surface of the substrate, including an n type drift region, and having a trench whose bottom is located in the drift region; and a gate electrode provided in the trench in the SiC layer. In the trench in the SiC layer, a first angle formed by at least part of a first sidewall on an off-direction side and the principal surface of the substrate is an obtuse angle, and a second angle formed by at least part of a second sidewall opposite to the first sidewall and the principal surface of the substrate is an acute angle, in a cross section parallel to a direction of a normal line to the principal surface of the substrate and a direction of a c-axis of the substrate.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: September 8, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tsutomu Kiyosawa, Kazuhiro Kagawa, Yasuyuki Yanase, Haruyuki Sorada
  • Publication number: 20150129897
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten mixture (e.g., including KOH and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Application
    Filed: December 2, 2014
    Publication date: May 14, 2015
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Publication number: 20150128850
    Abstract: Non-destructive pretreatment methods are generally provided for a surface of a SiC substrate with substantially no degradation of surface morphology thereon. In one particular embodiment, a molten suspension mixture (e.g., including KOH (or KOH eutectic) and a buffering agent) is applied directly onto the surface of the SiC substrate to form a treated surface thereon. An epitaxial film (e.g., SiC) can then be grown on the treated surface to achieve very high (e.g., up to and including 100%) BPD to TED conversion rate close to the epilayer/substrate interface.
    Type: Application
    Filed: December 2, 2014
    Publication date: May 14, 2015
    Inventors: Tangali S. Sudarshan, Haizheng Song, Tawhid Rana
  • Patent number: 9017633
    Abstract: Single crystal diamond material produced using chemical vapour deposition (CVD), and particularly diamond material having properties suitable for use in optical applications such as lasers, is disclosed. In particular, a CVD single crystal diamond material having preferred characteristics of longest linear internal dimension, birefringence and absorption coefficient, when measured at room temperature, is disclosed. Uses of the diamond material, including in a Raman laser, and methods of producing the diamond are also disclosed.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 28, 2015
    Assignee: Element Six Technologies Limited
    Inventors: Ian Friel, Sarah Louise Geoghegan, Daniel James Twitchen, Joseph Michael Dodson
  • Publication number: 20150108504
    Abstract: A 3C-SiC epitaxial layer is produced by a production method including: epitaxially growing a first 3C-SiC layer on a Si substrate; oxidizing the first 3C-SiC layer; removing an oxide film on a surface of the 3C-SiC layer; and epitaxially growing a second 3C-SiC layer on the 3C-SiC layer after the oxide film is removed.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 23, 2015
    Inventors: Yukimune WATANABE, Noriyasu KAWANA
  • Patent number: 9005362
    Abstract: The present invention is to provide a method for growing a group III nitride crystal that has a large size and has a small number of pits formed in the main surface of the crystal by using a plurality of tile substrates. A method for growing a group III nitride crystal includes a step of preparing a plurality of tile substrates 10 including main surfaces 10m having a shape of a triangle or a convex quadrangle that allows two-dimensional close packing of the plurality of tile substrates; a step of arranging the plurality of tile substrates 10 so as to be two-dimensionally closely packed such that, at any point across which vertexes of the plurality of tile substrates 10 oppose one another, 3 or less of the vertexes oppose one another; and a step of growing a group III nitride crystal 20 on the main surfaces 10m of the plurality of tile substrates arranged.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 14, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuki Hiromura, Koji Uematsu, Hiroaki Yoshida, Shinsuke Fujiwara
  • Publication number: 20150083036
    Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Can Bayram, Christos D. Dimitrakopoulos, Keith E. Fogel, Jeehwan Kim, John A. Ott, Devendra K. Sadana
  • Patent number: 8986835
    Abstract: A GaN nanorod and formation method. Formation includes providing a substrate having a GaN film, depositing SiNx on the GaN film, etching a growth opening through the SiNx and into the GaN film, growing a GaN nanorod through the growth opening, the nanorod having a nanopore running substantially through its centerline. Focused ion beam etching can be used. The growing can be done using organometallic vapor phase epitaxy. The nanopore diameter can be controlled using the growth opening diameter or the growing step duration. The GaN nanorods can be removed from the substrate. The SiNx layer can be removed after the growing step. A SiOx template can be formed on the GaN film and the GaN can be grown to cover the SiOx template before depositing SiNx on the GaN film. The SiOx template can be removed after growing the nanorods.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: March 24, 2015
    Assignee: Purdue Research Foundation
    Inventors: Isaac Harshman Wildeson, Timothy David Sands
  • Patent number: 8986464
    Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Yukimune Watanabe
  • Patent number: 8980003
    Abstract: In a method of manufacturing a silicon carbide single crystal, a silicon carbide substrate having a surface of one of a (11-2n) plane and a (1-10n) plane, where n is any integer number greater than or equal to 0, is prepared. An epitaxial layer having a predetermined impurity concentration is grown on the one of the (11-2n) plane and the (1-10n) plane of the silicon carbide substrate by a chemical vapor deposition method so that a threading dislocation is discharged from a side surface of the epitaxial layer. A silicon carbide single crystal is grown into a bulk shape by a sublimation method on the one of the (11-2n) plane and the (1-10n) plane of the epitaxial layer from which the threading dislocation is discharged.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: March 17, 2015
    Assignee: DENSO CORPORATION
    Inventors: Hiroki Watanabe, Yasuo Kitou, Masami Naito
  • Patent number: 8974599
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described., as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: March 10, 2015
    Assignee: SCIO Diamond Technology Corporation
    Inventors: Robert C. Linares, Patrick J. Doering
  • Publication number: 20150053996
    Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.
    Type: Application
    Filed: November 1, 2012
    Publication date: February 26, 2015
    Applicants: Kabushiki Kaisha Toyota Chuo Kenkyusho, Denso Corporation
    Inventors: Tetsuo Narita, Kenji Ito, Kazuyoshi Tomita, Nobuyuki Otake, Shinichi Hoshi, Masaki Matsui
  • Publication number: 20150050471
    Abstract: The present invention relates to the production of III-N templates and also the production of III-N single crystals, III signifying at least one element of the third main group of the periodic table, selected from the group of Al, Ga and In. By adjusting specific parameters during crystal growth, III-N templates can be obtained that bestow properties on the crystal layer that has grown on the foreign substrate which enable flawless III-N single crystals to be obtained in the form of templates or even with large III-N layer thickness.
    Type: Application
    Filed: March 21, 2013
    Publication date: February 19, 2015
    Applicant: Freiberger Compound Materials GMBH
    Inventors: Frank Lipski, Ferdinand Scholz, Martin Klein, Frank Habel
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8940614
    Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 27, 2015
    Assignee: Dow Corning Corporation
    Inventors: Mark J. Loboda, Jie Zhang
  • Publication number: 20150024223
    Abstract: The present invention provides a monolithic integrated lattice mismatched crystal template and a preparation method thereof by using low-viscosity material, the preparation method for the crystal template includes: providing a first crystal layer with a first lattice constant; growing a buffer layer on the first crystal layer; below the melting point of the buffer layer, growing a second crystal layer and a template layer by sequentially performing the growth process of a second crystal layer and the growth process of a first template layer on the buffer layer, or growing a template layer by directly performing a first template layer growth process on the buffer layer; melting and converting the buffer layer to an amorphous state, performing a second template layer growth process on the template layer grown by the first template layer growth process at the growth temperature above the glass transition temperature of the buffer layer, sequentially growing a template layer until the lattice of the template laye
    Type: Application
    Filed: April 6, 2012
    Publication date: January 22, 2015
    Applicant: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY
    Inventor: Shumin Wang
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8932403
    Abstract: A method for forming a surface-textured single-crystal film layer by growing the film atop a layer of microparticles on a substrate and subsequently selectively etching away the microparticles to release the surface-textured single-crystal film layer from the substrate. This method is applicable to a very wide variety of substrates and films. In some embodiments, the film is an epitaxial film that has been grown in crystallographic alignment with respect to a crystalline substrate.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sandia Corporation
    Inventors: Qiming Li, George T. Wang
  • Publication number: 20150001556
    Abstract: A growth substrate including a substrate having a growth surface including a plurality of steps inclining in a first direction; a first layer disposed on the growth surface, the first layer including an A-plane or an M-plane in an upper part thereof, a plurality of protrusions having an inclined surface on an upper surface thereof, and nitride; a mask layer including a dielectric material and having at least a portion disposed on the protrusions; and a second layer disposed on the mask layer and including nitride.
    Type: Application
    Filed: June 30, 2014
    Publication date: January 1, 2015
    Inventors: Hyunggu KIM, Hwankuk YUH, Hyosang YU
  • Patent number: 8916124
    Abstract: When a group III nitride crystal is grown in a pressurized atmosphere of a nitrogen-containing gas from a melt 50 including at least a group III element, nitrogen and an alkali metal or an alkali earth metal, a melt-holding vessel 160 that holds the above-described melt 50 is swung about two axes different in direction from each other such as an X-axis and a Y-axis.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: December 23, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Hisashi Minemoto, Osamu Yamada, Takeshi Hatakeyama, Hiroaki Hoshikawa, Yasunori Tokunou
  • Patent number: 8906159
    Abstract: Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 9, 2014
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 8906487
    Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Shimada
  • Patent number: 8906788
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A first carbon nanotube layer is placed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A second carbon nanotube layer is placed on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 9, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan