With A Chemical Reaction (except Ionization) In A Disparate Zone To Form A Precursor (e.g., Transport Processes) Patents (Class 117/99)
  • Patent number: 10903389
    Abstract: Presented herein are reactors for growing or depositing semiconductor films or devices. The reactors disclosed may be used for the production of III-V materials grown by hydride vapor phase epitaxy (HVPE).
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Kevin Louis Schulte, Aaron Joseph Ptak, John David Simon
  • Patent number: 10655219
    Abstract: A containment structure is disclosed for holding a substrate (e.g., preform) during CVI/CVD treatment. The containment structure includes a support structure, a cover portion, a gas inlet and a gas outlet. During the CVI/CVD process, the substrate is contained within the containment structure, forming a first space between the support structure and the substrate, and a second space between the substrate and the cover portion. Reactant gas is introduced into the first space and forced through the substrate via delta pressure, forming a binding matrix within the substrate. Excess reactant gas exits the substrate into the second space and is removed from the containment structure through the gas outlet.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: May 19, 2020
    Assignee: GOODRICH CORPORATION
    Inventors: John E. Finley, Mark R. Wolke, Mark K. Lentz
  • Patent number: 10100433
    Abstract: A substrate holder having a base plate where a plurality of protruding poles is arranged, said poles spaced apart from one another by intermediate spaces. Alternatively or in addition, a plasma reactor for depositing diamond from the gas phase may be provided, the plasma reactor comprising such a substrate holder. A method for depositing diamond from the gas phase may be provided.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 16, 2018
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V
    Inventors: Christoph E. Nebel, Wolfgang Müller-Sebert, Claudia Widmann, Nicola Heidrich, Christoph Schreyvogel
  • Patent number: 9574286
    Abstract: A gas phase nanowire growth apparatus including a reaction chamber (200), a first input and a second input (202 B, 202 A). The first input is located concentrically within the second input and the first and second input are configured such that a second fluid delivered from the second input provides a sheath between a first fluid delivered from the first input and a wall of the reaction chamber. An aerosol of catalyst particles may be used to grow the nanowires.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: February 21, 2017
    Assignee: SOL VOLTAICS AB
    Inventors: Greg Alcott, Martin Magnusson, Olivier Postel, Knut Deppert, Lars Samuelson, Jonas Ohlsson
  • Patent number: 9181633
    Abstract: A device for heat treating (annealing) a III-V semiconductor wafer comprises at least one wafer support unit which is dimensioned such that a cover provided above the wafer surface is either spaced without any distance or with a distance of maximally about 2 mm to the wafer surface. A process for heat treating III-V semiconductor wafers having diameters larger than 100 mm and a dislocation density below 1×104 cm?2 is carried out in the device of the invention. SI GaAs wafers produced have an at least 25% increased characteristic fracture strength (Weibull distribution), an improved radial macroscopic and mesoscopic homogeneity and an improved quality of the mechano-chemically polished surface. The characteristic fracture strength is higher than 1900 MPa.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: November 10, 2015
    Assignee: FREIBERGER COMPOUND MATERIALS GMBH
    Inventors: Manfred Jurisch, Stefan Eichler, Thomas Bünger, Berndt Weinert, Frank Börner
  • Patent number: 8980002
    Abstract: Methods are disclosed for growing group III-nitride semiconductor compounds with advanced buffer layer technique. In an embodiment, a method includes providing a suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. The method includes forming an AlN buffer layer by flowing an ammonia gas into a growth zone of the processing chamber, flowing an aluminum halide containing precursor to the growth zone and at the same time flowing additional hydrogen halide or halogen gas into the growth zone of the processing chamber. The additional hydrogen halide or halogen gas that is flowed into the growth zone during buffer layer deposition suppresses homogeneous AlN particle formation. The hydrogen halide or halogen gas may continue flowing for a time period while the flow of the aluminum halide containing precursor is turned off.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
  • Patent number: 8980000
    Abstract: In a rotating disk reactor for growing epitaxial layers on substrate or other CVD reactor system, gas directed toward the substrates at gas inlets at different radial distances from the axis of rotation of the disk has both substantially the same gas flow rate/velocity and substantially the same gas density at each inlet. The gas directed toward portions of the disk remote from the axis may include a higher concentration of a reactant gas than the gas directed toward portions of the disk close to the axis, so that portions of the substrate surfaces at different distances from the axis receive substantially the same amount of reactant gas per unit area, and a combination of carrier gases with different relative molecular weights at different radial distances from the axis of rotation are employed to substantially make equal the gas density in each region of the reactor.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: March 17, 2015
    Assignee: Veeco Instruments Inc.
    Inventors: Bojan Mitrovic, Alex Gurary, William Quinn, Eric A. Armour
  • Patent number: 8945304
    Abstract: A system and method A method of growing an elongate nanoelement from a growth surface includes: a) cleaning a growth surface on a base element; b) providing an ultrahigh vacuum reaction environment over the cleaned growth surface; c) generating a reactive gas of an atomic material to be used in forming the nanoelement; d) projecting a stream of the reactive gas at the growth surface within the reactive environment while maintaining a vacuum of at most 1×10?4 Pascal; e) growing the elongate nanoelement from the growth surface within the environment while maintaining the pressure of step c); f) after a desired length of nanoelement is attained within the environment, stopping direction of reactive gas into the environment; and g) returning the environment to an ultrahigh vacuum condition.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 3, 2015
    Assignee: The Board of Regents of the Nevada System of Higher Education on behalf of the University of Nevada, Las Vegas University of Nevada
    Inventors: Biswajit Das, Myung B. Lee
  • Patent number: 8936681
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the epitaxial growth surface. The carbon nanotube layer is removed. The carbon nanotube layer can be removed by heating.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: January 20, 2015
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8882909
    Abstract: Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition. In conjunction with thermal annealing and/or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 11, 2014
    Assignee: Dichroic Cell S.R.L.
    Inventor: Hans Von Kaenel
  • Patent number: 8858708
    Abstract: This invention provides a process for producing high-purity dense polycrystalline III-nitride slabs. A vessel which contains a group III-metal such as gallium or an alloy of group III-metals of shallow depth is placed in a reactor. The group III-metal or alloy is heated until a molten state is reached after which a halide-containing source mixed with a carrier gas and a nitrogen-containing source is flowed through the reactor vessel. An initial porous crust of III-nitride forms on the surface of the molten III-metal or alloy which reacts with the nitrogen-containing source and the halide-containing source. The flow rate of the nitrogen-containing source is then increased and flowed into contact with the molten metal to produce a dense polycrystalline III-nitride. The products produced from the inventive process can be used as source material for III-nitride single crystal growth which material is not available naturally.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: October 14, 2014
    Assignee: The United States of America As represented by the Secretary of the Air Force
    Inventors: Michael J. Callahan, Buguo Wang, John S. Bailey
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8778078
    Abstract: A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga and In, wherein the doped crystalline III-N layer or the doped III-N bulk crystal is deposited on a substrate or template in a reactor, and wherein the feeding of at least one dopant into the reactor is carried out in admixture with at least one group III material. In this manner, III-N bulk crystals and III-N single crystal substrates separated therefrom can be obtained with a very homogeneous distribution of dopants in the growth direction as well as in the growth plane perpendicular thereto, a very homogeneous distribution of charge carriers and/or of the specific electric resistivity in the growth direction as well as in the growth plane perpendicular thereto, and a very good crystal quality.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: July 15, 2014
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Ferdinand Scholz, Peter Brückner, Frank Habel, Gunnar Leibiger
  • Patent number: 8663389
    Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.
    Type: Grant
    Filed: May 21, 2011
    Date of Patent: March 4, 2014
    Inventor: Andrew Peter Clarke
  • Patent number: 8652256
    Abstract: A manufacturing apparatus of polycrystalline silicon products polycrystalline silicon by depositing on a surface of a silicon seed rod by supplying raw-material gas to the heated silicon seed rod provided vertically in a reactor, includes: an electrode which holds the silicon seed rod and is made of carbon; an electrode holder which holds the electrode, and cooled by coolant medium flowing therein, wherein the electrode includes: a seed rod holding member which holds the silicon seed rod; a heat cap which is provided between the seed rod holding member and the electrode holder; and a cap protector having a ring-like plate shape, which covers an upper surface of the heat cap, and in which a through hole penetrating the lower-end portion of the seed rod holding member is formed.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: February 18, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshihide Endoh, Masayuki Tebakari, Toshiyuki Ishii, Masaaki Sakaguchi
  • Patent number: 8632633
    Abstract: Engineered defects are reproduced in-situ with graphene via a combination of surface manipulation and epitaxial reproduction. A substrate surface that is lattice-matched to graphene is manipulated to create one or more non-planar features in the hexagonal crystal lattice. These non-planar features strain and asymmetrically distort the hexagonal crystal lattice of epitaxially deposited graphene to reproduce “in-situ” engineered defects with the graphene. These defects may be defects in the classic sense such as Stone-Wales defect pairs or blisters, ridges, ribbons and metacrystals. Nano or micron-scale structures such as planar waveguides, resonant cavities or electronic devices may be constructed from linear or closed arrays of these defects. Substrate manipulation and epitaxial reproduction allows for precise control of the number, density, arrangement and type of defects. The graphene may be removed and template reused to replicate the graphene and engineered defects.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: January 21, 2014
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, Brian J. Zelinski, William R. Owens
  • Publication number: 20130319320
    Abstract: A production method of aluminum based group III nitride single crystal includes a reaction step, wherein a halogenated gas and an aluminum contact at 300° C. or more to 700° C. or less, producing a mixed gas including an aluminum trihalide gas and an aluminum monohalide gas; a converting step, wherein the aluminum monohalide gas is converted to a solid by setting a temperature of the mixed gas equal to or higher than a temperature to which a solid aluminum trihalide deposit, and lower by 50° C. or more than a temperature to which halogenated gas and aluminum contact in the reaction step; a separation step, wherein the aluminum trihalide gas is removed; and a crystal growth step, wherein the aluminum trihalide gas is used for an aluminum based group III nitride single crystal raw material, keeping its temperature equal to or higher than a temperature of the converting step.
    Type: Application
    Filed: December 15, 2011
    Publication date: December 5, 2013
    Applicant: TOKUYAMA CORPORATION
    Inventors: Toru Nagashima, Keiichiro Hironaka
  • Patent number: 8585820
    Abstract: Methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment and methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: November 19, 2013
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20130247817
    Abstract: A metal chloride gas generator includes a reactor including a receiving section for receiving a metal on an upstream side and a growing section in which a growth substrate is placed on a downstream side, a raw material section heater and a growing section heater each of which heats an inside of the reactor, an upstream end comprising a gas inlet, and a gas inlet pipe arranged to extend from the upstream end via the receiving section to the growing section, for introducing a chloride gas from the upstream end to supply the chloride gas to the receiving section and supplying a metal chloride gas produced by a reaction between the chloride gas and the metal in the receiving section to the growing section. The gas inlet pipe includes a suppressing section for suppressing an optical waveguiding phenomenon which waveguides a radiant heat from the growing section heater or the growing section.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 26, 2013
    Applicant: Hitachi Cable, Ltd.
    Inventors: Taichiroo KONNO, Hajime Fujikura
  • Publication number: 20130177492
    Abstract: The method comprises at least three steps of a hydrogenation step (101) and/or a chlorination step (102), an impurity conversion step (103), and a purification step (104). In the impurity conversion step (103), an aldehyde compound represented by the general formula Ar—R—CHO (Ar; denotes a substituted or unsubstituted aryl group, R; denotes an organic group having two or more carbon atoms) is added to convert donor impurities and acceptor impurities contained in a chlorosilane distillate to a high-boiling substance. The chlorosilane distillate after the donor impurities and acceptor impurities have been converted to a high-boiling substance is sent to the purification step (104). In the purification step (104), high purity chlorosilanes from which the donor impurities and acceptor impurities have been thoroughly removed are obtained by using a distillation column or the like, where the high purity chlorosilanes are recovered outside the system from the top of the column.
    Type: Application
    Filed: September 2, 2011
    Publication date: July 11, 2013
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Masayuki Hasegawa, Yoichi Tonomura, Tohru Kubota, Takeshi Aoyama, Shuji Tanaka
  • Patent number: 8470090
    Abstract: Affords large-diametric-span AlN crystals, applicable to various types of semiconductor devices, with superior crystallinity, a method of growing the AlN crystals, and AlN crystal substrates. The AlN crystal growth method is a method in which an AlN crystal (4) is grown by vapor-phase epitaxy onto a seed crystal substrate (2) placed inside a crystal-growth compartment (24) within a crystal-growth vessel (12) provided within a reaction chamber, and is characterized in that during growth of the crystal, carbon-containing gas is supplied to the inside of the crystal-growth compartment (24).
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: June 25, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Michimasa Miyanaga, Tomohiro Kawase, Shinsuke Fujiwara
  • Patent number: 8465588
    Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 18, 2013
    Assignee: SORAA, Inc.
    Inventors: Christiane Poblenz, James S. Speck, Derrick S. Kamber
  • Patent number: 8425681
    Abstract: A method for growing low-dislocation-density material atop a layer of the material with an initially higher dislocation density using a monolayer of spheroidal particles to bend and redirect or directly block vertically propagating threading dislocations, thereby enabling growth and coalescence to form a very-low-dislocation-density surface of the material, and the structures made by this method.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: April 23, 2013
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li
  • Patent number: 8419853
    Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
  • Patent number: 8415546
    Abstract: Disclosed is a fabrication method of a metal nanoplate using metal, metal halide or a mixture thereof as a precursor. The single crystalline metal nanoplate is fabricated on a single crystalline substrate by performing heat treatment on a precursor including metal, metal halide or a mixture thereof and placed at a front portion of a reactor and the single crystalline substrate placed at a rear portion of the reactor under an inert gas flowing condition. A noble metal nanoplate of several micrometers in size can be fabricated using a vapor-phase transport process without any catalyst. The fabricated nanoplate is a single crystalline metal nanoplate having high crystallinity, high purity and not having a two-dimensional defect. Morphology and orientation of the metal nanoplate with respect to the substrate can be controlled by controlling a surface direction of the single crystalline substrate. The metal nanoplate of several micrometer size is mass-producible.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: April 9, 2013
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Bongsoo Kim, Youngdong Yoo
  • Patent number: 8394197
    Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 12, 2013
    Assignee: Sub-One Technology, Inc.
    Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
  • Patent number: 8382898
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: February 26, 2013
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8382897
    Abstract: Methods for gas delivery to a process chamber are provided herein. In some embodiments, a method may include flowing a process gas through one or more gas conduits, each gas conduit having an inlet and an outlet for facilitating the flow of gas through the gas conduits and into a gas inlet funnel having a second volume, wherein each gas conduit has a first volume less than the second volume, and wherein each gas conduit has a cross-section that increases from a first cross-section proximate the inlet to a second cross-section proximate the outlet but excluding any intersection points between the gas inlet funnel and the gas conduit, and wherein the second cross-section is non-circular; and delivering the process gas to the substrate via the gas inlet funnel.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 26, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kedarnath Sangam, Anh N. Nguyen
  • Patent number: 8349076
    Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 8, 2013
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: In-Jae Song, Jai-yong Han
  • Patent number: 8328936
    Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 11, 2012
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
  • Publication number: 20120291698
    Abstract: Methods are disclosed for growing group III-nitride semiconductor compounds with advanced buffer layer technique. In an embodiment, a method includes providing a suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. The method includes forming an AlN buffer layer by flowing an ammonia gas into a growth zone of the processing chamber, flowing an aluminum halide containing precursor to the growth zone and at the same time flowing additional hydrogen halide or halogen gas into the growth zone of the processing chamber. The additional hydrogen halide or halogen gas that is flowed into the growth zone during buffer layer deposition suppresses homogeneous AlN particle formation. The hydrogen halide or halogen gas may continue flowing for a time period while the flow of the aluminum halide containing precursor is turned off.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 22, 2012
    Inventors: Yuriy Melnik, Lu Chen, Hidehiro Kojiri
  • Publication number: 20120247386
    Abstract: A method and apparatus for forming heterojunction stressor layers is described. A germanium precursor and a metal precursor are provided to a chamber, and an epitaxial layer of germanium-metal alloy formed on the substrate. The metal precursor is typically a metal halide, which may be provided by subliming a solid metal halide or by contacting a pure metal with a halogen gas. The precursors may be provided through a showerhead or through a side entry point, and an exhaust system coupled to the chamber may be separately heated to manage condensation of exhaust components.
    Type: Application
    Filed: July 28, 2011
    Publication date: October 4, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Errol Antonio C. Sanchez, David K. Carlson
  • Patent number: 8262796
    Abstract: A thin-film single crystal growing method includes preparing a substrate, irradiating an excitation beam on a metallic target made of a pure metal or an alloy in a predetermined atmosphere, and combining chemical species including any of atoms, molecules, and ions released from the metallic target by irradiation of the excitation beam with atoms contained in the predetermined atmosphere to form a thin film on the substrate.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: September 11, 2012
    Assignee: Waseda University
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Patent number: 8252112
    Abstract: A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH3.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: August 28, 2012
    Assignee: Ovshinsky Innovation, LLC
    Inventor: Stanford R. Ovshinsky
  • Patent number: 8216367
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 10, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8137460
    Abstract: Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH3 (ammonia) gas which is hydroxide gas on a substrate, the manufacturing method comprising supplying the NH3 gas in a vicinity of the substrate (for example, at a position which is separated from the substrate by a distance of 0.7-4.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 20, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Satoru Morioka, Misao Takakusaki, Takayuki Shimizu
  • Publication number: 20120048182
    Abstract: The invention relates to a method and system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The method includes reacting an amount of a gaseous Group III precursor having one or more gaseous gallium precursors as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber; and supplying sufficient energy to the gaseous gallium precursor(s) prior to their reacting so that substantially all such precursors are in their monomer forms. The system includes sources of the reactants, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their component monomers.
    Type: Application
    Filed: November 3, 2011
    Publication date: March 1, 2012
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8092596
    Abstract: Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 10, 2012
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Yuri V. Melnik, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A Dmitriev
  • Patent number: 8092597
    Abstract: Method for producing a III-N (AlN, GaN, AlxGa(1-x)N) crystal by Vapor Phase Epitaxy (VPE), the method comprising: providing a reactor having: a growth zone for growing a III-N crystal; a substrate holder located in the growth zone that supports at least one substrate on which to grow the III-N crystal; a gas supply system that delivers growth material for growing the III-N crystal to the growth zone from an outlet of the gas supply system; and a heating element that controls temperature in the reactor; determining three growth sub-zones in the growth zone for which a crystal grown in the growth sub-zones has respectively a concave, flat or convex curvature; growing the III-N crystal on a substrate in a growth region for which the crystal has a by desired curvature.
    Type: Grant
    Filed: January 22, 2011
    Date of Patent: January 10, 2012
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Vladimir A. Dmitriev, Yuri V. Melnik
  • Patent number: 8048225
    Abstract: The present invention includes a high-quality, large-area bulk GaN seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal is of ultra-low defect density, has flat surfaces free of bowing, and is free of foreign substrate material. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 1, 2011
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, Mathew C. Schmidt, Derrick S. Kamber
  • Patent number: 8038795
    Abstract: A precursor chiral nanotube with a specified chirality is grown using an epitaxial process and then cloned. A substrate is provided of crystal material having sheet lattice properties complementary to the lattice properties of the selected material for the nanotube. A cylindrical surface(s) having a diameter of 1 to 100 nanometers are formed as a void in the substrate or as crystal material projecting from the substrate with an orientation with respect to the axes of the crystal substrate corresponding to the selected chirality. A monocrystalline film of the selected material is epitaxially grown on the cylindrical surface that takes on the sheet lattice properties and orientation of the crystal substrate to form a precursor chiral nanotube. A catalytic particle is placed on the precursor chiral nanotube and atoms of the selected material are dissolved into the catalytic particle to clone a chiral nanotube from the precursor chiral nanotube.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: October 18, 2011
    Assignee: Raytheon Company
    Inventors: Delmar L. Barker, William R. Owens
  • Patent number: 8002892
    Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: August 23, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno
  • Publication number: 20110155049
    Abstract: Hydride vapor-phase deposition (HVPE) systems are disclosed. An HVPE hydride vapor-phase deposition system may include a reactant source chamber and a growth chamber containing a susceptor coupled to the reactant source chamber. The reactant source chamber may be configured to create a reactant gas through a chemical reaction between a solid or liquid precursor and a different precursor gas. The reactant source chamber can be configured to operate at a temperature T(M) significantly above room temperature. The reactant gas can be chemically unstable at or near room temperature. The susceptor is configured to receive a substrate and maintain the substrate at a substrate temperature T(S). The growth chamber includes walls can be configured to operate at a temperature T(C) such that T(M), T(S) are greater than T(C).
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: CBL Technologies, Inc.
    Inventors: Glenn S. Solomon, David J. Miller
  • Patent number: 7857907
    Abstract: The present invention relates to a method for forming a layered structure with silicon nanocrystals. In one embodiment, the method comprises the steps of: (i) forming a first conductive layer on a substrate, (ii) forming a silicon-rich dielectric layer on the first conductive layer, and (iii) laser-annealing at least the silicon-rich dielectric layer to induce silicon-rich aggregation to form a plurality of silicon nanocrystals in the silicon-rich dielectric layer. The silicon-rich dielectric layer is one of a silicon-rich oxide film having a refractive index in the range of about 1.4 to 2.3, or a silicon-rich nitride film having a refractive index in the range of about 1.7 to 2.3. The layered structure with silicon nanocrystals in a silicon-rich dielectric layer is usable in a solar cell, a photodetector, a touch panel, a non-volatile memory device as storage node, and a liquid crystal display.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: December 28, 2010
    Assignee: AU Optronics Corporation
    Inventors: An-Thung Cho, Chih-Wei Chao, Chia-Tien Peng, Wan-Yi Liu, Ming-Wei Sun
  • Publication number: 20100158785
    Abstract: A method of growing high-quality, group-III nitride, bulk single crystals. The group III-nitride bulk crystal is grown in an autoclave in supercritical ammonia using a source material or nutrient that is a group III-nitride polycrystals or group-III metal having a grain size of at least 10 microns or more and a seed crystal that is a group-III nitride single crystal. The group III-nitride polycrystals may be recycled from previous ammonothermal process after annealing in reducing gas at more then 600° C. The autoclave may include an internal chamber that is filled with ammonia, wherein the ammonia is released from the internal chamber into the autoclave when the ammonia attains a supercritical state after the heating of the autoclave, such that convection of the supercritical ammonia transfers source materials and deposits the transferred source materials onto seed crystals, but undissolved particles of the source materials are prevented from being transferred and deposited on the seed crystals.
    Type: Application
    Filed: July 8, 2005
    Publication date: June 24, 2010
    Inventor: Kenji Fujito
  • Publication number: 20100006023
    Abstract: Nitride semiconductor films, such as for use in solid state light emitting devices and electronic devices, are fabricated in an environment of relatively high nitrogen potential such that nitrogen vacancies in the growing film are reduced. A reactor design, and method for its use, provide high nitrogen precursor partial pressure, precracking of the precursor using a catalytic metal surface, prepyrolyzing the precursor, using catalytically-cracked molecular nitrogen as a nitrogen precursor, and/or exposing the surface to an ambient which is extremely rich in active nitrogen species. Improved efficiency for light emitting devices, particularly in the blue and green wavelengths and improve transport properties in nitride electronic devices, i.e., improved performance from nitride-based devices such as InGaAlN laser diodes, transistors, and light emitting diodes is thereby provided.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 14, 2010
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: David P. Bour, Peter Kiesel, Christopher L. Chua, Noble M. Johnson, Zhihong Yang, John E. Northrup
  • Patent number: 7645340
    Abstract: A method for growing a crystal of an Al-containing III-V group compound semiconductor by the conventional HVPE method, characterized in that it comprises a step of reacting Al with hydrogen halide at a temperature of 700° C. or lower to form a halide of Al. The method has allowed the suppression of the formation of aluminum chloride (AlCl) or aluminum bromide (AlBr) reacting violently with quartz, which is the material of a reaction vessel for the growth, resulting in the achievement of the vapor phase growth of an Al-containing III-V group compound semiconductor at a rate of 100 microns/hr or more, which has lead to the mass-production of a substrate and a semiconductor element having satisfactory resistance to adverse environment.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: January 12, 2010
    Assignee: Tokyo University Agriculture and Technology TLO Co., Ltd.
    Inventors: Akinori Koukitu, Yoshinao Kumagai, Tomohiro Marui
  • Publication number: 20090294774
    Abstract: Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH3 (ammonia) gas which is hydroxide gas on a substrate, the manufacturing method comprising supplying the NH3 gas in a vicinity of the substrate (for example, at a position which is separated from the substrate by a distance of 0.7-4.
    Type: Application
    Filed: September 14, 2007
    Publication date: December 3, 2009
    Inventors: Satoru Morioka, Misao Takakusaki, Takayuki Shimizu
  • Patent number: 7608539
    Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 27, 2009
    Assignee: Sundew Technologies, LLC
    Inventor: Ofer Sneh
  • Publication number: 20090223442
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.
    Type: Application
    Filed: November 15, 2007
    Publication date: September 10, 2009
    Inventors: Chantal Arena, Christiaan Werkhoven