Abstract: The invention provides a doped semiconductor powder comprising nanocrystals of a group IV semiconductor and a rare earth element, the rare earth element being dispersed on the surface of the group IV semiconductor nanocrystals. The invention also provides processes for the preparation of the above doped semiconductor powder, and a composite material comprising a matrix in which is dispersed a doped semiconductor powder.

Abstract: A wide bandgap semiconductor material is heavily doped to a degenerate level. Impurity densities approaching 1% of the volume of the semiconductor crystal are obtained to greatly increase conductivity. In one embodiment, a layer of AlGaN is formed on a wafer by first removing contaminants from a MBE machine. Wafers are then outgassed in the machine at very low pressures. A nitride is then formed on the wafer and an AlN layer is grown. The highly doped GaAlN layer is then formed having electron densities beyond 1×1020 cm−3 at Al mole fractions up to 65% are obtained.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.

Abstract: A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a first mask that includes a first array of openings therein and growing the underlying gallium nitride layer through the first array of openings and onto the first mask, to thereby form a first overgrown gallium nitride semiconductor layer. The first overgrown layer is then masked with the second mask that includes a second array of openings therein. The second array of openings is laterally offset from the first array of openings. The first overgrown gallium nitride layer is then grown through the second array of openings and onto the second mask, to thereby form a second overgrown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second overgrown gallium nitride semiconductor layer.

Abstract: A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.

Abstract: A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Abstract: There is provided a film, which is excellent in thermal resistance, has low dielectric constant, and is applicable to a semiconductor device or electric appliances. The low dielectric constant film having thermal resistance comprises molecules comprising boron, nitrogen, and hydrogen, wherein the number of the nitrogen atom is 0.7 to 1.3 and the number of the hydrogen atom is 1.0 to 2.2 based on one boron atom, and of which dielectric constant is at most 3 2.4.

Abstract: The present invention provides a silicon wafer free of vacancy agglomerates and interstitial agglomerate; wherein the silicon wafer has a defect density of an oxide film of 0.1 piece/cm2 or less, when the oxide film having a thickness of 5 to 25 nm is formed on the surface of the wafer and a DC voltage of 10 MV/cm is applied via the oxide film for 100 seconds, and wherein the silicon wafer has an in-plane dispersion of 20% or less of a p-n junction leakage current in a p-n junction area of 1 mm2 or more of a p-n junction portion when the p-n junction portion is formed on the surface of the wafer. The present silicon wafer is capable of achieving a higher performance, higher yield and uniformity of characteristics of semiconductor devices comparable to a wafer provided with a pure epitaxial layer, without deteriorating the gettering ability of the silicon wafer.

Abstract: Quality of epitaxial semiconductor substrates treated by carbon gettering is evaluated precisely and quickly to use only good-quality ones for manufacturing good-property semiconductor devices, such as solid-state imaging devices. After carbon implanted regions and carbon non-implanted regions are made along the surface of a Si substrate by selectively ion-implanting carbon, a Si epitaxial layer is grown on the surface of the Si substrate to obtain a Si epitaxial substrate. Recombination lifetime or surface photo voltage is measured at a portion of the Si epitaxial layer located above the carbon non-implanted region, and the result is used to evaluate acceptability of the Si epitaxial substrate. Thus, strictly selected good-quality Si epitaxial substrates alone are used to manufacture solid-state imaging devices or other semiconductor devices.

Abstract: There is disclosed a method of fabricating an SOI wafer in which a bond wafer to form a SOI layer and a base wafer to be a supporting substrate are prepared; an oxide film is formed on at least the bond wafer; hydrogen ions or rare gas ions are implanted in the bond wafer via the oxide film in order to form a fine bubble layer (enclosed layer) within the bond wafer; the ion-implanted surface is brought into close contact with the surface of the base wafer; and then heat treatment is performed to separate a thin film from the bond wafer with using the fine bubble layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and wherein deviation in the thickness of the oxide film formed on the bond wafer is controlled to be smaller than the deviation in the ion implantation depth, and the SOI wafer fabricated thereby. There is provided an SOI wafer which has an SOI layer having improved thickness uniformity.

Abstract: An improved chemical vapor deposition method is disclosed that increases the uniformity of silicon carbide epitaxial layers and that is particularly useful for obtaining thicker epitaxial layers. The method comprises heating a reactor to a temperature at which silicon carbide source gases will form an epitaxial layer of silicon carbide on a substrate in the reactor; and then directing a flow of source and carrier gases through the heated reactor to form an epitaxial layer of silicon carbide on the substrate with the carrier gases comprising a blend of hydrogen and a second gas in which the second gas has a thermal conductivity that is less than the thermal conductivity of hydrogen so that the source gases deplete less as they pass through the reactor than they would if hydrogen is used as the sole carrier gas.

Abstract: A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a first mask that includes a first array of openings therein and growing the underlying gallium nitride layer through the first array of openings and onto the first mask, to thereby form a first overgrown gallium nitride semiconductor layer. The first overgrown layer is then masked with the second mask that includes a second array of openings therein. The second array of openings is laterally offset from the first array of openings. The first overgrown gallium nitride layer is then grown through the second array of openings and onto the second mask, to thereby form a second overgrown gallium nitride semiconductor layer. Microelectronic devices may then be formed in the second overgrown gallium nitride semiconductor layer.

Abstract: A method for producing a micro- or nanostructure on a substrate. In a first step, one surface of a first wafer in crystalline material is placed in contact with one surface of a second wafer in crystalline material, such that crystalline lattices presented by the surfaces offer at least one mismatch parameter able to allow the formation of a lattice of crystalline defects and/or of a lattice of strains within a crystalline zone extending on either side of the interface of the two wafers, at least one of the lattices determining the micro- or nanostructure. Then, one of the two wafers is thinned to expose the lattice defects and/or the lattice strains on a substrate formed by the other wafer.

Abstract: There are provided a method of producing an SOI wafer of high quality with excellent controllability, productivity and economy and a wafer produced by such a method. In the method of producing a substrate utilizing wafer bonding, a first substrate member and a second substrate member are mutually bonded, and then the second substrate member is separated from the first substrate member at the interface of a first layer and a second layer formed on the main surface of the first substrate member, whereby the second layer is transferred onto the second substrate member. In the separation, the separation position at the interface of the first and the second layers is ensured by varying the porosity of a porous Si layer, forming an easily separable plane by the coagulation of pores in porous Si, effecting ion implantation to the interface or utilizing a heteroepitaxial interface.

Abstract: A process for growing a metal oxide thin film upon a semiconductor surface with a physical vapor deposition technique in a high-vacuum environment and a structure formed with the process involves the steps of heating the semiconductor surface and introducing hydrogen gas into the high-vacuum environment to develop conditions at the semiconductor surface which are favorable for growing the desired metal oxide upon the semiconductor surface yet is unfavorable for the formation of any native oxides upon the semiconductor. More specifically, the temperature of the semiconductor surface and the ratio of hydrogen partial pressure to water pressure within the vacuum environment are high enough to render the formation of native oxides on the semiconductor surface thermodynamically unstable yet are not so high that the formation of the desired metal oxide on the semiconductor surface is thermodynamically unstable.

Abstract: An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.

Abstract: A method of processing a substrate, such as a semiconductor wafer, in a vacuum processing chamber includes the steps of depositing a material on a surface of the substrate using a gas mixture, and purging the chamber of residual gases by flowing SiH4 into the chamber. Preferably, WSix is deposited on a semiconductor wafer using a mixture comprising WF6, dichlorosilane and a noble gas, and the chamber is subsequently purged of residual WF6 and dichlorosilane by flowing SiH4 into the chamber. A further method of processing a substrate in a vacuum processing chamber includes the step of conditioning the chamber by flowing SiH4 into the chamber prior to depositing a material on the surface of the substrate. Semiconductor wafers processed according to the inventive method are characterized by more uniform sheet resistance values and reduced film stress.

Abstract: In a method for producing a silicon single crystal wafer, a silicon single crystal ingot in which nitrogen is doped is grown by a Czochralski method, sliced to provide a silicon single crystal wafer, and then subjected to heat treatment to out-diffuse nitrogen on the surface of the wafer. According to a further method, a silicon single crystal ingot is grown in which nitrogen is doped by a Czochralski method, with controlling nitrogen concentration, oxygen concentration and cooling rate, and then the silicon single crystal ingot is sliced to provide a wafer. A silicon single crystal wafer is obtained by slicing a silicon single crystal ingot grown by a Czochralski method with doping nitrogen, wherein the depth of a denuded zone after gettering heat treatment or device fabricating heat treatment is 2 to 12 &mgr;m, and the bulk micro-defect density after gettering heat treatment or device fabricating heat treatment is 1×108 to 2×1010 number/cm3.

Abstract: There is disclosed a method for producing an epitaxial silicon single crystal wafer comprising the steps of growing a silicon single crystal ingot wherein nitrogen is doped by Czochralski method, slicing the silicon single crystal ingot to provide a silicon single crystal wafer, and forming an epitaxial layer in the surface layer portion of the silicon single crystal wafer. There can be manufactured easily and in high productivity an epitaxial silicon monocrystal wafer which has high gettering capability when a substrate having a low boron concentration is used, a low concentration of heavy metal impurity, and an excellent crystallinity.

Abstract: A method for producing a pattern of regularly spaced-apart nucleation sites and corresponding devices are disclosed. The method enables formation of a device having an amorphous or otherwise non-single crystal surface from which single crystal layers of a desired orientation may be grown using the regularly spaced nucleation sites as a growth template. The method can be used to produce a single crystal semiconductor layer of a desired orientation (e.g., <100> or <111>) on an amorphous insulating layer (e.g. of SiO.sub.2 or Si.sub.3 N.sub.4). For example, single crystal Si of a <100> orientation may be grown on an SiO.sub.2 layer. Monocrystalline semiconductor films may be similarly grown on amorphous glass substrates or the like for producing solar cells of high efficiency and low cost.

Abstract: A substrate structure includes a single crystal Si substrate and a surface layer, with a buffer layer interleaved therebetween. The buffer layer includes at least one of an R--Zr family oxide thin film composed mainly of a rare earth oxide and/or zirconium oxide, an AMnO.sub.3 thin film composed mainly of rare earth element A, Mn and O and having a hexagonal YMnO.sub.3 type structure, an AlO.sub.x thin film composed mainly of Al and O, and a NaCl type nitride thin film composed mainly of titanium nitride, niobium nitride, tantalum nitride or zirconium nitride. The surface layer is an epitaxial film containing a wurtzite type oxide and/or nitride. The surface layer can serve as a functional film such as a semiconductor film or an underlying film therefor, and the substrate structure is useful for the manufacture of electronic devices.

Abstract: The invention provides a method for treating devices based on semiconductor and dielectric materials for improving their electrical, photoelectric, optical, luminescent and noise characteristics, for decreasing internal residual stresses in heterostructures and for increasing the device lifetime and the stability of its parameters. The method comprises subjecting the device to acoustic vibrations in the frequency range of 0.01 to 100 MHz, at an amplitude of relative acoustic strain in the range of 0.2.multidot.10.sup.-5 to 8.multidot.10.sup.-5, for a period of at least 0.25 hour.

Abstract: Compliant universal (CU) substrates and techniques for forming the same facilitate growth of epitaxial layers comprised of materials which are highly lattice mismatched with the substrate material. The CU substrates employ very thin (e.g., 1-20 nm or less) substrate layers which are loosely bonded to a thick bulk material base layer. Because of the loose bonding, the bonding energy of the atoms in the thin substrate layer is reduced, thus greatly increasing the flexibility of the thin substrate layer. This enables the substrate layer to absorb strain or stress imparted during the growth of lattice mismatched epitaxial layers, thus avoiding the formation of defects in the epitaxial layers. The "loose" bonding of the thin substrate layer to the base layer can be achieved in any of a number of ways. First, the thin substrate layer can be bonded at an angle relative to the base layer so that screw dislocations form which provide the desired reduction in bonding energy and increase in flexibility.

Abstract: An apparatus for and a method of determining the epitaxial layer thickness and transition width in epitaxial single crystal silicon wafers are provided. The apparatus provides an epitaxial single crystal silicon wafer comprising an isotopically enriched doped substrate. The method involves a process of applying Second Ion Mass Spectrometry (SIMS) to the isotopically enriched doped wafer for determining its epitaxial layer thickness and transition width.

Abstract: A semiconductor wafer polishing agent contains mainly a silica containing polishing agent and is added with a polyolefin type fine particle material. The novel semiconductor wafer polishing agent is capable of low brightness polishing to the back face of the wafer, sensor detection of the front and back faces of the wafer, and suppression of dust to be generated by chipping of the back face of the wafer, thereby to increase the yield of semiconductor devices. A polishing method using the polishing agent and a novel semiconductor wafer having a back face with an unconventional surface shape are also disclosed.

Abstract: A substrate for a photovoltaic device wherein the substrate is the base upon which photosensitive material is to be grown and the substrate comprises an alloy having boron in a range from 0.1 atomic % of the alloy to 1.3 atomic % of the alloy and the substrate has a resistivity less than 3.times.10.sup.-3 ohm-cm.

Abstract: Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-X) Ge.sub.X is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.

Abstract: A precursor for manufacturing a semiconductor thin film in which an oxide thin film comprising at least one element as a dopant, selected from a group which consists of Groups IA, IIA, IIB, VA, and VB elements, and Groups IB and IIIA elements which are main components of the semiconductor thin film are deposited on a substrate, or a precursor for manufacturing a semiconductor thin film which is formed by depositing a thin film of oxide comprising the Groups IB and IIIA elements on the substrate wherein the content of at least one of the Groups IB and IIIA elements is varied in the direction of film thickness, and a method for manufacturing a semiconductor thin film comprising the step of heat treating the precursor for manufacturing the semiconductor thin film in an atmosphere containing a Group VIA element.

Abstract: A semiconductor heterojunction material includes a heterojunction configured by successively overlaying first, middle and third layers of semiconductor, some or all of the constituent elements of the first and third layers being different and the middle layer containing all elements contained in the first and third layers.

Abstract: Nonpolar substrates comprising off-axis growth regions for the growth of polar semiconductors, and a method for making such substrates, are disclosed. According to the invention, an erodible material, such as a photoresist, is applied to a substrate at a site and is exposed to radiation at that site which has an linear variation in energy at the surface of the erodible material. Due to this variation in exposure energy, a taper results in the erodible material after development. The tapered region is then etched in a manner which etches both the erodible layer and the underlying substrate. The taper in the erodible layer provides a varying attenuation during the etching process such that the taper of the erodible layer is transferred to the substrate.

Abstract: An n-type thermoelectric material composed mainly of an iron-silicite compound represented by a chemical formula of FeSi.sub.2+z in which -0.1<z<0.1. The thermoelectric material further comprising Co as an n-type dopant and Ge as an additive. The iron-silicon compound is composed substantially of a low temperature phase (.beta.-phase).

Abstract: A substrate for use in semiconductor devices, fabricated of silicon carbide and having a resistivity of greater than 1500 Ohm-cm. The substrate being characterized as having deep level impurities incorporated therein, wherein the deep level elemental impurity comprises one of a selected heavy metal, hydrogen, chlorine and fluorine. The selected heavy metal being a metal found in periodic groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB.

Abstract: A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.

Abstract: A method of improving the dielectric properties of a thin dielectric disposed on a polycrystalline material, a method of forming a capacitor therewith and the capacitor. An electrode (17) having a polycrystalline material surface having voids (23) extending to the surface, preferably silicon, is provided. A layer of an amorphous form of the material (19) having a thickness of from about 20 .ANG. to about 500 .ANG. is formed over the surface with the amorphous layer disposed within the voids. A thin layer of a dielectric (21) is formed over the amorphous layer and, in the fabrication of a capacitor, a layer of electrical conductor (25) is provided which is spaced from the material over the dielectric. A microcontaminant can be disposed between the polycrystalline material surface and the amorphous layer.

Abstract: A CVD process for producing a rare earth-doped, epitaxial semiconductor layer on a substrate is disclosed. The process utilizes a silane or germane and a rare earth compound in the gas phase. By this method single phase, rare earth-doped semiconductor layers, supersaturated in the rare earth, are produced. The preferred rare earth is erbium and the preferred precursors for depositing erbium by CVD are erbium hexafluoroacetylacetonate, acetylacetonate, tetramethylheptanedionate and flurooctanedionate. The process may be used to produce optoelectronic devices comprising a silicon substrate and an erbium-doped epitaxial silicon film.

Abstract: A process and structure involving a silicon substrate utilize molecular beam epitaxy (MBE) and/or electron beam evaporation methods and an ultra-high vacuum facility to grow a layup of epitaxial alkaline earth oxide films upon the substrate surface. By selecting metal constituents for the oxides and in the appropriate proportions so that the lattice parameter of each oxide grown closely approximates that of the substrate or base layer upon which oxide is grown, lattice strain at the film/film or film/substrate interface of adjacent films is appreciably reduced or relieved.

Abstract: A semiconductor device, which can easily form hyper abrupt junction type junction having a desired depletion layer width or transition region width, is disclosed. A silicon oxide film is formed on the mirror polished side surface of a P-type semiconductor substrate. Then, a P-type diffusion layer is formed by means of heat treatment. In this process, impurity concentration distribution is formed in such a way that the impurity concentration distribution can abruptly decrease from the mirror polished side surface of the substrate. Following this, the oxide film is removed by etching, and hyper abrupt type PN junction is obtained by sticking the mirror polished side surface of a high impurity concentration N-type semiconductor substrate and the high impurity concentration diffusion side of the above P-type semiconductor substrate to each other in the same surface direction as that of the above P-type semiconductor substrate.

Abstract: A mixed crystal ratio difference is introduced in a gallium arsenide phosphide mixed crystal layer having a desired constant mixed crystal ratio, thereby reducing the amount of stress remaining within the resulting epitaxial wafer. This is less likely or unlikely to crack, and so can be well used for LED fabrication.

Abstract: The invention provides a method and apparatus for depositing alloy films useful in manufacturing photovoltaic solar cells. In the preferred embodiment an alloy comprising copper, indium, and selenium is deposited on a substrate. Sputtering is utilized to provide the copper and indium, with the selenium being provided by evaporization. Other alloys may also be formed using the disclosed apparatus and techniques.

Abstract: In the manufacture of a single crystal film by epitaxial growth method, defects such as cracking are avoided by increasing the deviation of the lattice constant of the resulting film in the direction of growth from the substrate. Preferably, the deviation is increased at the rate of (0.4.about.9).times.10.sup.-4 %/.mu.m.

Abstract: A silicon wafer containing oxygen precipitate nucleation centers (or oxygen precipitates) and having a first face, a second face, and a central plane equidistant between the first and second faces. The nucleation centers (or oxygen precipitates) have a non-uniform distribution between the first and second faces with a maximum density of the nucleation centers (or oxygen precipitates) being in a region which is between the first face and the central plane and nearer to the first face than the central plane. The density of the nucleation centers (or oxygen precipitates) increases from the first face to the region of maximum density and decreasing from the region of maximum density to the central plane.

Abstract: Ternary II-VI semiconductor films (16) are formed on a silicon substrate (12) by first depositing a monolayer of arsenic (14) or other Group V metal on a cleaned surface of the substrate. The ternary II-VI semiconductor film is then formed over the arsenic monolayer, either directly thereon or on top of an intermediate II-VI semiconductor buffer layer (18). The use of an arsenic passivating layer facilitates the epitaxial deposition of technologically important II-VI semiconductors such as ZnTe, CdTe, and HgCdTe on silicon substrates of arbitrary crystallographic orientation.

Abstract: A low energy (10 to 300 eV), mass-selected ion beam is used to deposit thin films on atomically clean substrate surfaces. For example, a C.sup.+ ion beam may be used to deposit a chemically bonded diamond or diamondlike film on a substrate at room temperature. For thin carbon films, the initial monolayer of the deposited film is in the form of a carbide layer which is chemically bonded to the substrate atoms. The film evolves gradually over the next several layers deposited, through intermediate structures, into a diamond structure. The optimum C.sup.+ energy range for formation of the diamond structure is about 30 to 175 eV. Below 10 eV the final diamond structure has not been attained and above 180 eV there is a sharp increase in the dose required to attain this final structure. Multiple ion beams may be used to deposit multicomponent films including films doped with very low concentrations of foreign atoms. The diamond films produced by this process are found to be free of impurities, inert to O.sub.

Abstract: A process for producing silicon wafers which have a storage-stable surface and which can be thermally oxidized directly, that is to say, without a prior HF immersion bath, and without the addition of halogen-containing gases, it being possible to achieve an equal or better oxidation result than that achieved by including these measures.

Abstract: The present invention relates to a solid low temperature phosphorus diffusion source that is an R.sub.2 O.sub.3 /P.sub.2 O.sub.5 compound in which the ratio of R.sub.2 O.sub.3 to P.sub.2 O.sub.5 is 1 to 5 and R is Nd, Eu, Pr, Sm, Ho, Tb, Er, Yb, Tm or Dy. The invention also relates to a method of making the diffusion source, a method of using the diffusion source to evolve P.sub.2 O.sub.5 to dope a silicon wafer, and the doped silicon wafer.

Abstract: The present invention relates to a solid high temperature phosphorus diffusion source that is an R.sub.2 O.sub.3 /P.sub.2 O.sub.5 compound in which the ratio of R.sub.2 O.sub.3 to P.sub.2 O.sub.5 is 1 to 3 and R is La, Y, Ce, Nd, Eu, Pt, Sm, Ho, Tb, Er, Yb, Tm or Dy. The invention also relates to a method of making the diffusion source, a method of using the diffusion source to evolve P.sub.2 O.sub.5 to dope a silicon wafer, and to the doped silicon wafer.

Abstract: A composite target used in alignment of layers on a wafer uses alignment marks placed in a target area. First alignment marks are composed of material from a first layer placed on the wafer. As subsequent layers are placed on the wafer, alignment marks composed of material from the subsequent layers are placed within the target area. For example, alignment marks composed of material from a second layer are each placed adjacent to one of the alignment marks composed of material from the first layer. Alignment marks composed of material from a third layer are each placed adjacent to one of the alignment marks composed of material from the second layer. Alignment marks composed of material from a fourth layer are each placed adjacent to the alignment marks composed of material from the third layer. And so on. The alignment marks are, for example, each rectangular in shape.

Abstract: An IC chemical mechanical planarization (cmp) process incorporating slurry temperature control. Specifically, there is a VCMP process which requires small holders 18. The VCMP process incorporates small quantities of chemicals in the holder, and utilizes a system of closely regulating the heating and cooling of the chemical component of the VCMP process to increase and decrease the chemical reaction, and therefore the speed of the chemical removal of tungsten material.

Abstract: A silicon starting material for fabricating integrated circuits is desrcibed that comprises a silicon wafer substrate material and a first epitaxial layer grown on the wafer substrate which eliminates stacking faults in the subsequent fabrication of a semiconductor device.