With Mechanical Mask, Shield Or Shutter For Shielding Workpiece Patents (Class 156/345.3)
  • Patent number: 6652713
    Abstract: Generally, a substrate support member for supporting a substrate is provided. In one embodiment, a substrate support member for supporting a substrate includes a body coupled to a lower shield. The body has an upper surface adapted to support the substrate and a lower surface. The lower shield has a center portion and a lip. The lip is disposed radially outward of the body and projects towards a plane defined by the first surface. The lip is disposed in a spaced-apart relation from the body. The lower shield is adapted to interface with an upper shield disposed in a processing chamber to define a labyrinth gap that substantially prevents plasma from migrating below the member. The lower shield, in another embodiment, provides the plasma with a short RF ground return path.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: November 25, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Karl Brown, Vineet Mehta, See-Eng Phan, Semyon Sherstinsky, Allen Lau
  • Patent number: 6645585
    Abstract: There is provided a treatment container which enables to prolong a period of time taken for reaction products, such as a halide generated through reaction with corrosive halide gas, to exfoliate and fall down as particles, and decreases the frequency of periodic maintenance operation, thereby implementing increase of operating time. The treatment container constituting a chamber or a bell jar has a portion of the inner surface to be exposed to corrosive halide gas plasma and is formed with a sintered body mainly composed of a compound of yttrium and aluminum with oxygen, and the portion has a roughened surface of a mean roughness Ra of 1.5 to 10 &mgr;m.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: November 11, 2003
    Assignee: Kyocera Corporation
    Inventor: Shunichi Ozono
  • Publication number: 20030196760
    Abstract: A plasma treatment system for treating a workpiece with a downstream-type plasma. The processing chamber of the plasma treatment system includes a chamber lid having a plasma cavity disposed generally between a powered electrode and a grounded plate, a processing space separated from the plasma cavity by the grounded plate, and a substrate support in the processing space for holding the workpiece. A direct plasma is generated in the plasma cavity. The grounded plate is adapted with openings that remove electrons and ions from the plasma admitted from the plasma cavity into the processing space to provide a downstream-type plasma of free radicals. The openings may also eliminate line-of-sight paths for light between the plasma cavity and processing space. In another aspect, the volume of the processing chamber may be adjusted by removing or inserting at least one removable sidewall section from the chamber lid.
    Type: Application
    Filed: December 20, 2002
    Publication date: October 23, 2003
    Applicant: Nordson Corporation
    Inventors: James Scott Tyler, James D. Getty, Thomas V. Bolden, Robert Sergei Condrashoff
  • Patent number: 6620736
    Abstract: Deposition of ionized material at a beveled or non-flat edge of a semiconductor wafer and the etching by the ionized material at such edge is controlled in a high density plasma processing machine by surrounding the wafer with a conducting ring to affect sheath potential and deflecting the ions of the material in such a way that the deposition and etching rate changes in a controlled way over the region immediately adjacent the wafer edge. The ring may be biased in several ways to control the ion flux to the wafer edge.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: September 16, 2003
    Assignee: Tokyo Electron Limited
    Inventor: John Drewery
  • Publication number: 20030168168
    Abstract: An apparatus for replacing consumables of a vacuum chamber. A unitary removable shield assembly is provided to quickly replace consumables such as a shield. The shield assembly can include an upper adapter assembly, at least one shield member, a cover ring and an insulator member. The shield assembly is designed so that the consumables can be replaced in one step and allows the chamber to continue with its maintenance cycle.
    Type: Application
    Filed: March 6, 2002
    Publication date: September 11, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Alan B. Liu, Ilya Lavitsky, Michael Rosenstein
  • Publication number: 20030159778
    Abstract: The following plasma processing apparatus can suppress the production of contaminants from the plasma processing chamber of the apparatus and an article in the plasma processing chamber which are allowed to act as ground electrodes: a plasma processing apparatus in which a workpiece is processed by creating a plasma in the processing chamber, and one or more surfaces made of a grounded metal electric conductor which come into contact with the plasma in the plasma processing chamber are coated with a plasma-resistant polymeric material having a relationship between relative dielectric constant k&egr; and thickness t (&mgr;m) of t/k&egr;<300, or a protecting layer formed of a plasma-resistant and water-absorbing resin material is adhered and fixed to the outer surface of an article in the processing chamber by its swelling and then shrinkage.
    Type: Application
    Filed: February 27, 2002
    Publication date: August 28, 2003
    Inventors: Kunihiko Koroyasu, Muneo Furuse, Tomoyuki Tamura
  • Publication number: 20030141018
    Abstract: An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer.
    Type: Application
    Filed: January 28, 2002
    Publication date: July 31, 2003
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Joseph J. Stevens, Dmitry Lubomirsky, Ian Pancham, Donald J. K. Olgado, Howard E. Grunes, Yeuk-Fai Edwin Mok
  • Patent number: 6589352
    Abstract: The invention provides a removable first edge ring configured for pin and recess/slot coupling with a second edge ring disposed on the substrate support. In one embodiment, a first edge ring includes a plurality of pins, and a second edge ring includes one or more alignment recesses and one or more alignment slots for mating engagement with the pins. Each of the alignment recesses and alignment slots are at least as wide as the corresponding pins, and each of the alignment slots extends in the radial direction a length that is sufficient to compensate for the difference in thermal expansion between the first edge ring and the second edge ring.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: July 8, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Joseph Yudovsky, Lawrence C. Lei, Salvador Umotoy, Tom Madar, Girish Dixit, Gwo-Chuan Tzu
  • Patent number: 6589385
    Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: July 8, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akiyuki Minami, Satoshi Machida
  • Patent number: 6558505
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling, thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 6, 2003
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetaka Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi
  • Patent number: 6547921
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: April 15, 2003
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetaka Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi
  • Patent number: 6521081
    Abstract: A rotary transformer includes a resonant circuit and a coil drive circuit. The resonant circuit includes a resonating capacitor connected to a power MOS transistor, coupled across the primary coil of the transformer. The coil drive circuit includes a diode connected to a power MOS transistor coupled across the primary coil of the transformer. A microprocessor detects changes in the voltage across the primary coil. The resonant circuit is connected and disconnected from the transformer during a power transfer mode and a data transfer mode, respectively. During the power transfer mode, stored energy in the leakage inductance of the primary coil is used for power coupling, via the resonant circuit, instead of being dissipated as heat. The resonant circuit is disconnected from the rotary transformer during the data transfer mode to maximize bandwidth for two-way data transfer between the primary and secondary sides of the transformer.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: February 18, 2003
    Assignee: Tegal Corporation
    Inventors: Stephen P. DeOrnellas, Robert A. Ditizio
  • Publication number: 20030029565
    Abstract: Apparatus and methods for producing semiconductor devices are disclosed. A processing chamber includes an interior component having a stepped region including a plurality of raised sections and recessed sections divided by steps. With this apparatus, it is possible to prevent a film of deposited material formed on the stepped region from peeling, thereby decreasing the number of particles in the chamber and increasing the operation rate.
    Type: Application
    Filed: May 13, 2002
    Publication date: February 13, 2003
    Applicant: Kawasaki Microelectronics, Inc.
    Inventors: Katsunori Suzuki, Hidetada Horiuchi, Yasushi Kikuchi, Jin Yokogawa, Ryouichi Kubo, Koji Wakabayashi
  • Patent number: 6514378
    Abstract: An apparatus and method for consecutively processing a series of semiconductor substrates with minimal plasma etch rate variation following cleaning with fluorine-containing gas and/or seasoning of the plasma etch chamber. The method includes steps of (a) placing a semiconductor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by minimizing a recombination rate of H and Br on a silicon carbide edge ring surrounding the substrate at a rate sufficient to offset a rate at which Br is consumed across the substrate. The method can be carried out using pure HBr or combination of HBr with other gases.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: February 4, 2003
    Assignee: Lam Research Corporation
    Inventors: Tuqiang Ni, Kenji Takeshita, Tom Choi, Frank Y. Lin, Wenli Collison
  • Publication number: 20020179246
    Abstract: A reactor for applying reactive ion etching to a component, wherein a substrate holder (3) and clamping means (10) are provided for respectively supporting and securing components (8) to be exposed to reactive ion flux, that includes a separate shield arrangement (20) fixed in a detachable way on said substrate holder (3), above said clamping means (10) to mask said clamping means with respect to said reactive ion flux. Said shield arrangement (20), made up of a single ring can be mounted on said substrate holder (3) directly upon said clamping means or can also be mounted just above it and separated by a small distance from said clamping means (10). The shield arrangement (20) can also made up of at least two rings (22) which are stacked with a small mutual separation, above said clamping means (10). The material of said shield arrangement (20) can be covered with a film of dielectric material and electrically connected to ground (23) through said substrate holder (3).
    Type: Application
    Filed: May 30, 2002
    Publication date: December 5, 2002
    Applicant: ALCATEL
    Inventors: Patick Garabedian, Philippe Pagnod-Rossiaux, Michel Puech
  • Patent number: 6489249
    Abstract: In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate “black silicon” comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of t
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: December 3, 2002
    Assignee: Infineon Technologies AG
    Inventors: Gangadhara S. Mathad, Rajiv Ranade
  • Patent number: 6485655
    Abstract: An internal coating on an internal passage wall exposed at a passage opening through an article external surface is protected from removal during repair of the article, including removal of at least a portion of an external coating, by a masking assembly disposed about the passage opening. The masking assembly comprises a masking member and a substantially flexible seal, substantially inert to a coating removal medium for the external coating. The masking member is shaped for disposition about the passage opening across a gap between the external surface and the masking member. The substantially flexible seal is disposed across the gap substantially to seal the gap.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: November 26, 2002
    Assignee: General Electric Company
    Inventors: Nripendra Nath Das, Stephen Joseph Ferrigno, Jim Dean Reeves, Michael Glenn Gordon
  • Publication number: 20020139768
    Abstract: An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, a sheet coupled to the etch head, a rubber gasket disposed between the etch head and the sheet, and an integrated spacer and protection plate for securing the device without damaging the backside of the device during decapsulation. In one embodiment of the present invention, the integrated spacer and protection plate is adjustable to accommodate devices of varying sizes.
    Type: Application
    Filed: March 27, 2001
    Publication date: October 3, 2002
    Inventors: Xia Li, Jose Hulog, Mohammad Massoodi
  • Patent number: 6402886
    Abstract: A method and apparatus for improving etch uniformity in reticle etching by eliminating local effects at the edge of the reticle is disclosed. The present invention relates to a reticle frame which surrounds the reticle. The reticle frames are patterned with a pattern profile similar to that of the reticle to prevent edge uniformities of the reticle by allowing uniform plasma etching of the entire reticle surface. The reticle frames may also be used to move the reticle in and out of etch chambers without damaging them.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: June 11, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Richard Stocks, Kevin Donohoe
  • Publication number: 20020032940
    Abstract: In a method for polishing leads of a semiconductor package, a plurality of semiconductor packages is arranged in a certain manner. Then, the leads are automatically polished. The semiconductor packages may be masked to expose at least a part of the leads to be polished.
    Type: Application
    Filed: November 28, 2001
    Publication date: March 21, 2002
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Takeyuki Sato