With Particular Substrate Or Support Structure Patents (Class 174/255)
  • Patent number: 12036776
    Abstract: A resin multilayer substrate includes a laminate including resin layers including a first resin layer and a second resin layer that are laminated, a via conductor in the first resin layer, and a joint portion that includes at least a portion in the second resin layer and is joined to the via conductor. The joint portion is more brittle than the via conductor. A linear expansion coefficient of the second resin layer is larger than a linear expansion coefficient of the via conductor and a linear expansion coefficient of the joint portion, and is smaller than a linear expansion coefficient of the first resin layer.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: July 16, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yusuke Kamitsubo, Tsuyoshi Katsube, Ryosuke Takada
  • Patent number: 12016114
    Abstract: A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: June 18, 2024
    Assignee: Super Micro Computer, Inc.
    Inventors: Manhtien V. Phan, Mau-Lin Chou, Chih-Hao Lee
  • Patent number: 11984375
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 11937377
    Abstract: The main technical problem solved by the present disclosure is to provide a circuit board preparation method. The method includes: obtaining a to-be-processed plate comprising an insulating layer, a first copper layer, a second copper layer opposite to the first copper layer, a blind metalized hole, and a first tab facing the blind metalized hole; obtaining a white insulating material; laminating the white insulating material to a surface of the insulating layer, a surface of the first copper layer, a surface of the first tab, and a surface of the second copper layer to form a first white insulating medium layer and a second white insulating medium layer opposite to the first while insulating medium layer; and performing surface polishing for the first white insulating medium layer and grinding the first white insulating medium layer until the first tab is exposed to form a first white reflective layer.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: March 19, 2024
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventor: Changsheng Tang
  • Patent number: 11929315
    Abstract: A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Junghoon Kang
  • Patent number: 11916297
    Abstract: A liquid crystal antenna and a method for forming a liquid crystal antenna are provided. The liquid crystal antenna includes a first substrate; a second substrate opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. A first conductive layer is disposed on a side of the first substrate facing toward the second substrate; a second conductive layer is disposed on a side of the second substrate facing toward the first substrate; the second conductive layer at least includes a plurality of radiation electrodes; an external metal layer is disposed on a side of the first substrate facing away from the liquid crystal layer; and the external metal layer is connected to a fixed potential.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: February 27, 2024
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Zhenyu Jia, Kerui Xi, Baiquan Lin, Xiaonan Han, Zuocai Yang, Donghua Wang, Yukun Huang, Feng Qin
  • Patent number: 11894289
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 11882648
    Abstract: A dielectric layer for manufacturing a component carrier is described. The dielectric layer includes a first section including a first material having a first material property; and a second section including a second material having a second material property. The second material property is different from the first material property. A method for manufacturing such a component carrier and a component carrier including such a dielectric layer is further described.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 23, 2024
    Assignee: AT&SAustria Technologie & Systemtechnik AG
    Inventors: Thomas Kristl, Dominik Wilding
  • Patent number: 11866536
    Abstract: A copper-clad laminate includes an insulating layer formed of a cured product of a resin composition and a surface treated copper foil in contact with the insulating layer, in which the resin composition contains a compound having at least one group specified in the present application and a crosslinking type curing agent; and the surface treated copper foil is a surface treated copper foil including a finely roughened particle treatment layer of copper on at least one surface side of copper foil.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuki Kitai, Masashi Koda, Yasunori Hoshino, Atsushi Wada, Mikio Sato
  • Patent number: 11864319
    Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure and a through hole. An interposer is located in the through hole and has a higher density of connection elements than the stack. A first component is mounted on a first main surface of the interposer and a second component is mounted on a second main surface of the interposer. The first component and the second component are connected via the interposer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 2, 2024
    Assignee: AT&SAustria Technologie &Systemtechnik AG
    Inventors: Mario Schober, Markus Leitgeb
  • Patent number: 11856693
    Abstract: A resin multilayer substrate includes a stacked body provided by stacking and thermocompression bonding resin layers, a first conductor pattern inside the stacked body, and a first protective coating covering at least a first surface and a side surface of the first conductor pattern. The resin layers are made of a first thermoplastic resin, and the first protective coating is made of a second thermoplastic resin. Both of the first and second thermoplastic resins soften at a predetermined press temperature or less. The second thermoplastic resin has a storage modulus lower than a storage modulus of the first thermoplastic resin at a temperature equal to or less than the predetermined press temperature and equal to or more than room temperature.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: December 26, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yusuke Kamitsubo
  • Patent number: 11834748
    Abstract: Through the plasma spraying technology and the cold spraying high-speed deposition technology, an evenly distributed protective coating is formed on the surface of a plasma etching chamber. The protective coating, having a double-layer composite structure, includes a metal+Y2O3 coating as a metal+Y2O3 transition layer deposited by plasma spraying as a lower layer of the double-layer composite structure, and a high-purity Y2O3 ceramic coating coated on the metal+Y2O3 transition layer as an upper layer of the double-layer composite structure, the metal+Y2O3 transition layer is configured to reduce the difference in expansion coefficient between the Y2O3 ceramic coating and the metal substrate, and enhance the bonding force between the Y2O3 ceramic coating and the metal substrate; the high-purity Y2O3 ceramic coating is formed by depositing Y2O3 ceramic powders on the metal+Y2O3 transition layer at high speed through cold spraying high-speed deposition.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 5, 2023
    Assignee: SHENYANG FORTUNE PRECISION EQUIPMENT CO., LTD
    Inventors: Guangwen Zheng, Tianying Xiong, Yanfang Shen, Xinyu Cui, Jiqiang Wang, Junrong Tang, Ning Li, Jianzhong Qi, Yongshan Tao
  • Patent number: 11833782
    Abstract: An object of the present invention is to provide a polymer film to which a metal-containing layer is stuck to produce a laminate having an excellent peel strength. Another object of the present invention is to provide a laminate and a substrate for high-speed communication. The polymer film of an embodiment of the present invention is a polymer film including a liquid crystal polymer, in which a difference between a melting start temperature and a melting end temperature in differential scanning calorimetry in a depth region up to 10 ?m of the polymer film from one surface toward the other surface of the polymer film is 5.0° C. to 50° C.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: December 5, 2023
    Assignee: FUJIFILM Corporation
    Inventors: Takeaki Sawaya, Akira Yamada
  • Patent number: 11826983
    Abstract: An object of the present invention is to provide a polymer film having a low dielectric loss tangent and a small difference in a linear expansion coefficient from that of a copper foil; and a laminate.
    Type: Grant
    Filed: August 28, 2022
    Date of Patent: November 28, 2023
    Assignee: FUJIFILM Corporation
    Inventor: Akira Yamada
  • Patent number: 11798863
    Abstract: The problem to be solved by the invention is to provide a laminate capable of effectively enhancing thermal conductivity and adhesiveness, in spite of the relatively large thickness of a patterned metal layer. The laminate (1) according to the present invention includes a metal substrate (4), an insulating layer (2) laminated on one surface of the metal substrate (4), and a patterned metal layer (3) laminated on the surface of the insulating layer (2) on the side opposite to the metal substrate (4), the metal layer (3) is 300 ?m or more in thickness, and the insulating layer (2) includes boron nitride (12) and an inorganic filler (13) other than boron nitride.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 24, 2023
    Assignee: SEKISUI CHEMICAL CO., LTD.
    Inventors: Kouji Ashiba, Keigo Oowashi, Aki Koukami, Rui Zhang
  • Patent number: 11792914
    Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and first shielding columns. The core layer includes an accommodating space, and the accommodating space has an inner side wall. The first shielding ring wall is disposed in the accommodating space and covers the inner side wall, in which the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding columns are disposed in the first insulating layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 17, 2023
    Assignees: AVARY HOLDING (SHENZHEN) CO., LTD., HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO., LTD., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Zhi-Hong Yang, Mao-Feng Hsu
  • Patent number: 11792929
    Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor penetrating through the second insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer such that the coating film is adhering the first conductor layer and the second insulating layer. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is in contact with the connection conductor and the wiring pattern is covered by the coating film, the conductor pad of the first conductor layer has a surface facing the second insulating layer and having a first surface roughness higher than a surface roughness of a surface of the wiring pattern, and the coating film has opening such that the opening is exposing the conductor pad entirely.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 17, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Daisuke Minoura
  • Patent number: 11764138
    Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: September 19, 2023
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Osamu Koga, Yasuyuki Hitsuoka, Yoshito Akutagawa
  • Patent number: 11762238
    Abstract: Embodiments of the present disclosure relate to a printed circuit, a backlight unit, and a display device. The printed circuit on which a light source is mounted can be easily manufactured in a single form, by depositing and arranging a wiring layer on a substrate and mounting the light source on the wiring layer. Further, the printed circuit is arranged so that the wiring layer includes a plurality of bonding metal layers and a plurality of wiring metal layers, and a part of the bonding metal layer positioned between the plurality of wiring metal layers and disposed in an area overlapping a pad portion of the light source is removed. Therefore, even though the main metal layer of the wiring layer is removed during reworking, it is possible to provide the printed circuit capable of electrically connecting to the light source by the sub-metal layer of the wiring layer.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: September 19, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Kyuhwan Lee, SangChul Ryu, DongSeok Lee
  • Patent number: 11744024
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: August 29, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Yung I Yeh, Chang-Lin Yeh, Sheng-Yu Chen
  • Patent number: 11737208
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
  • Patent number: 11728249
    Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 11721481
    Abstract: An electronic component includes: a body; first and second external electrodes including first and second head portions disposed on opposite end surfaces of the body; and first and second metal frames, the first metal frame including a first support portion bonded to the first head portion, and a first mounted portion extending from the first support portion, and the second metal frame including a second support portion bonded to the second head portion, and a second mounted portion extending from the second support portion. 0.2A?B?0.8A, in which an area of each of the first and second head portions is A, and an area of each of a region in which the first head portion and the first support portion are bonded to each other, and a region in which the second head portion and the second support portion are bonded to each other is B.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Yeop Kim, Beom Joon Cho, Gyeong Ju Song
  • Patent number: 11710884
    Abstract: Waveguides and methods for manufacturing a waveguide that include forming a first channel in a first layer of dielectric material, the first channel comprising one or more walls; forming a second channel in a second layer of dielectric material, the second channel comprising one or more walls; depositing electrically conductive material on the one or more walls of the first channel; depositing electrically conductive material on the one or more walls of the second channel; arranging the first layer adjacent to the second layer to form a stack with the first channel axially aligned with and facing the second channel; and heating the stack so that the conductive material on the one or more walls of the first channel and the conductive material on the one or more walls of the second channel connect to form the waveguide.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: July 25, 2023
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventor: Daniel Scott Krueger
  • Patent number: 11711890
    Abstract: The present application provides an asymmetric board, which includes the first master board, the second master board, and the insulating dielectric layer sandwiched between the first master board and the second master board, and the depth control grooves are disposed in the connection position between the units on the asymmetric board, and located on the surface of the second master board and extending a toward the side of the first master board, the depth control grooves provide space for the expansion of the second master board, reduce the stress of the units, and reduce the warping of the second master board. When the number of the depth control grooves in the first direction and/or the second direction is greater than 0, the depths of the depth control grooves increase by X from a center to an edge of the asymmetric board, and the X is greater than or equal to 0.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: July 25, 2023
    Inventors: Jun Wang, Xiaoqing Chen, Qian Chen
  • Patent number: 11705392
    Abstract: The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: July 18, 2023
    Assignee: InnoLux Corporation
    Inventors: Mei-Chi Hsu, Yu-Chin Lin, Yu-Ting Liu
  • Patent number: 11706870
    Abstract: A structure includes a first copper layer and a first carbon layer applied directly to a surface of the first copper layer, a second copper layer and a second carbon layer applied directly to a surface of the second copper layer, and an insulating core disposed between the first and second copper layers. Each of the first carbon layer and the second carbon layer faces toward and directly contacts the insulating core. The structure provides electrical power to a component of an electronic device.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: July 18, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Joel Goergen, Jessica Kiefer, Alpesh Umakant Bhobe, Kameron Rose Hurst, D. Brice Achkir, Amendra Koul, Scott Hinaga, David Nozadze
  • Patent number: 11683884
    Abstract: A component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and having a cavity delimited at least partially by a first polymer, and a component embedded in the cavity of the stack and being at least partially covered by a second polymer, wherein an anchoring interface is formed at an interface between the first polymer and the second polymer at which the first polymer and the second polymer are mechanically anchored with each other.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: June 20, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Imane Souli, Erich Preiner, Martin Schrei, Vanesa López Blanco
  • Patent number: 11682527
    Abstract: A multilayer capacitor includes a body including a stack structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes are stacked with the dielectric layers interposed therebetween, external electrodes formed on an external surface of the body to be connected to the internal electrodes, and including a first electrode layer covering a first surface of the body to which the internal electrodes are exposed, and a second electrode layer covering the first electrode layer, a first metal oxide layer disposed between the first and second electrode layers and having a discontinuous region, and a second metal oxide layer covering at least a portion of a surface of the body on which the external electrodes are not disposed and having a multilayer structure.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jang Yeol Lee, Hye Min Bang, Tae Joon Park, Hai Joon Lee
  • Patent number: 11672079
    Abstract: A component carrier, wherein the component carrier includes: i) a layer stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, ii) a bendable portion which forms at least a part of the layer stack, and iii) a metal layer which forms at least a part of the bendable portion. Hereby, the metal layer extends over at least 75% of the area of the bendable portion.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: June 6, 2023
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Nick Xin, Mikael Tuominen
  • Patent number: 11665832
    Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: May 30, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Chia-Yu Peng, Shao-Chien Lee, Tzyy-Jang Tseng
  • Patent number: 11659656
    Abstract: A stretchable wiring board that includes a stretchable substrate having a first main surface with a first region, a second region adjacent the first region, and a third region adjacent the second region; a first stretchable wiring line on the first main surface and extending over the first region; an insulating layer extending over the first region and the second region; and a second stretchable wiring line extending over the first region, the second region, and the third region. When a thickness of the insulating layer is defined as Z2, and when a minimum value of a length of the second region in an extending direction of the second stretchable wiring line in a plan view of the stretchable wiring board is defined as Y, Y>Z2.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: May 23, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takahito Tomoda
  • Patent number: 11658104
    Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 23, 2023
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping Hsu, Chu-Chin Hu, Pao-Hung Chou
  • Patent number: 11658085
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 11640873
    Abstract: A method of forming a self-aligned electrical winding includes forming a first conductive turn in a first conductive layer around a planned leg hole and forming a second conductive turn in a second conductive layer around the planned leg hole. The method includes stacking a plurality of conductive layers aligned with each other, and separated from each other by at least one intervening insulation layer into a multilayer PCB stack. The method includes forming the planned leg hole through the multilayer PCB by removing the respective conductive portions of the first conductive turn and second conductive turn that extend into the planned leg hole. Forming the leg hole defines a first inner circumference for the first conductive turn and a second inner circumference for the second conductive turns, wherein the first inner circumference is aligned with the second inner circumference through forming the leg hole.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 2, 2023
    Assignee: VICOR CORPORATION
    Inventor: Patrizio Vinciarelli
  • Patent number: 11621173
    Abstract: Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: April 4, 2023
    Assignee: Lumileds LLC
    Inventors: Tze Yang Hin, Anantharaman Vaidyanathan, Srini Banna, Ronald Johannes Bonne
  • Patent number: 11617262
    Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor, and a coating film. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is formed in contact with the connection conductor and that the wiring pattern is covered by the coating film, the conductor pad has a surface facing the second insulating layer and having first surface roughness higher than surface roughness of a surface of the wiring pattern, and the coating film has opening exposing a portion of the surface of the conductor pad from the coating film and having area larger than area of interface between the conductor pad and the connection conductor and that the connection conductor is formed on the portion of the surface of the conductor pad and is separated from the coating film.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: March 28, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Takema Adachi, Daisuke Minoura
  • Patent number: 11596063
    Abstract: A composite substrate that includes: an upper ceramic layer; a lower ceramic layer; a middle resin layer between the upper ceramic layer and the lower ceramic layer; and a side surface resin layer on all side surfaces of the composite substrate, wherein the middle resin layer and the side surface resin layer are integral resin layers.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 28, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tsuyoshi Katsube
  • Patent number: 11594366
    Abstract: A multilayer coil component 1 includes an element body 2, a pair of terminal electrodes 3, and a glass layer G provided on the terminal electrode 3. Each of the pair of terminal electrodes 3 is provided with a plurality of first projecting portions 33 tapered toward the other facing terminal electrode 3 side in an end portion 31b facing the side in the facing direction of a pair of end surfaces 2a and 2b. The glass layer G is provided along the edge of the terminal electrode 3 including at least the first projecting portion 33 in the end portion 31b of the terminal electrode 3.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 28, 2023
    Assignee: TDK CORPORATION
    Inventors: Youichi Kazuta, Yuichi Takubo, Yuto Shiga, Junichiro Urabe, Noriaki Hamachi, Kazuya Tobita, Toshinori Matsuura
  • Patent number: 11551833
    Abstract: A manufacturing method of an embedded metal mesh flexible transparent electrode and application thereof; the method includes: directly printing a metal mesh transparent electrode on a rigid substrate by using an electric-field-driven jet deposition micro-nano 3D printing technology; performing conductive treatment on a printed metal mesh structure through a sintering process to realize conductivity of the metal mesh; respectively heating a flexible transparent substrate and the rigid substrate to set temperatures; completely embedding the metal mesh structure on the rigid substrate into the flexible transparent substrate through a thermal imprinting process; and separating the metal mesh completely embedded into the flexible transparent substrate from the rigid substrate to obtain the embedded metal mesh flexible transparent electrode.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 10, 2023
    Assignees: QINGDAO UNIVERSITY OF TECHNOLOGY, QINGDAO 5D INTELLIGENT ADDITIVE MANUFACTURING TECHNOLOGY CO., LTD.
    Inventors: Hongbo Lan, Xiaoyang Zhu, Quan Xu, Jiawei Zhao, Mingyang Liu
  • Patent number: 11546985
    Abstract: The present application discloses a differential signal routing line of a circuit board and a circuit board, which comprises a circuit board, and the circuit board is provided with differential signal routing lines including a first differential signal routing line and a second differential signal routing line that are disposed at different layers of the circuit board.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: January 3, 2023
    Assignee: HKC CORPORATION LIMITED
    Inventor: Shuixiu Hu
  • Patent number: 11528803
    Abstract: A wiring circuit board assembly sheet includes a support sheet having two end edges parallel with each other and a plurality of wiring circuit boards disposed at spaced intervals to each other in the support sheet. The wiring circuit board includes a metal-based portion having a generally rectangular frame shape. The metal-based portion includes a first piece along a first direction perpendicular to a thickness direction of the support sheet, and a second piece along a second direction perpendicular to the thickness direction and the first direction. Both the first piece and the second piece are inclined with respect to the end edge of the support sheet.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: December 13, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Takuya Taniuchi, Naoki Shibata, Ryosuke Sasaoka, Yasunari Oyabu
  • Patent number: 11515096
    Abstract: An electronic component includes a capacitor component including a body and an external electrode disposed outside the body; a metal frame connected to the external electrode; and an encapsulant at least partially covering regions of the capacitor component and the metal frame. The metal frame may include a surface unevenness portion disposed on at least a portion of an interface with the encapsulant.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Min Ahn, Beom Joon Cho, Ki Young Kim
  • Patent number: 11512023
    Abstract: In a silicon nitride substrate including a silicon nitride sintered body including silicon nitride crystal grains and a grain boundary phase, a plate thickness of the silicon nitride substrate is 0.4 mm or les, and a percentage of a number of the silicon nitride crystal grains including dislocation defect portions inside the silicon nitride crystal grains in a 50 ?m×50 ?m observation region of any cross section or surface of the silicon nitride sintered body is not less than 0% and not more than 20%. Etching resistance can be increased when forming the circuit board.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MATERIALS CO., LTD.
    Inventors: Katsuyuki Aoki, Takayuki Fukasawa, Jun Momma, Kentaro Iwai
  • Patent number: 11500503
    Abstract: An electronic device includes a first conductive layer including a first metal mesh including a first metal line segment, a second metal line segment and a first compensating line segment. The first metal line segment extends along a first direction and has a first end, and the second metal line segment extends along the first direction and has a second end, wherein a first breakpoint exists between the first end and the second end. The first compensating line segment is separated from and electrically insulated from the first metal line segment and the second metal line segment, the first compensating line segment does not completely overlap the first breakpoint, and a minimum distance between the first breakpoint and each first segment end of the first compensating line segment is less than or equal to 50 ?m.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 15, 2022
    Assignee: HENGHAO TECHNOLOGY CO., LTD.
    Inventors: Chun-Jung Chen, Su-Hsuan Chang
  • Patent number: 11497115
    Abstract: Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 8, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yi Lin, Hsiao-Han Huang, Yu-Hsin Pan
  • Patent number: 11490513
    Abstract: According to one embodiment, a metal base circuit board includes a metal base substrate, a first circuit pattern, and a first insulating layer between the metal base substrate and the first circuit pattern. The first insulating layer covers a lower surface of the first circuit pattern and at least part of a side surface of the first circuit pattern, the lower surface facing the metal base substrate, the at least part of the side surface being adjacent to the lower surface.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 1, 2022
    Assignee: NHK SPRING CO., LTD.
    Inventors: Katsumi Mizuno, Daiki Ikeda
  • Patent number: 11487129
    Abstract: An optical integration device includes a first circuit layer comprising a first surface adjacent a first diffractive layer, the first diffractive layer arranged on a side of the first circuit layer along a first direction, and a first connecting pad electrically connected with the first circuit layer through a first conductive member. The optical integration device includes a side surface extending along the first direction. The side surface defines a first concavity extending through the first diffractive layer along the first direction. The first connecting pad includes a first mounting member connected with the side surface, and a first convex member extending from the first mounting member and received in the first concavity. The first conductive member includes a first conductive part arranged between the side surface and the first mounting member, and a second conductive part arranged between the first surface and the first convex member.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 1, 2022
    Assignee: TRIPLE WIN TECHNOLOGY (SHENZHEN) CO. LTD.
    Inventors: Jia-Liang Wu, Yi-Yin Chen
  • Patent number: 11488901
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11476022
    Abstract: In an aspect, a composition comprises a plurality of magnetic particles. The magnetic particles each independently comprise a nickel ferrite core having the formula Ni1?xMxPe2+yO4, wherein M is at least one of Zn, Mg, Co, Cu, Al, Mn, or Cr; x is 0 to 0.95, and y=?0.5 to 0.5; and an iron nickel shell at least partially surrounding the core, wherein the iron nickel shell comprises iron, nickel, and optionally M. In another aspect, a method of forming the magnetic particles comprises heat treating a plurality of nickel ferrite particles in a hydrogen atmosphere to form the plurality of magnetic particles having the iron nickel shell on the nickel ferrite core. In yet another aspect, a composite can comprise the magnetic particles and a polymer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 18, 2022
    Assignee: ROGERS CORPORATION
    Inventors: Li Zhang, Yajie Chen