Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.

Abstract: Techniques are described herein that are capable of providing a modularized acoustic probe that includes multiple acoustic transducers that have discrete substrates. A first acoustic transducer is configured to generate an acoustic signal and to transmit the acoustic signal toward an object. The second acoustic transducer is configured to detect a reflected acoustic signal, which results from the acoustic signal reflecting from the object, and to convert the reflected acoustic signal to an electrical signal. The first and second acoustic transducers have respective discrete substrates. In an example, the second acoustic transducer may not be configured to generate acoustic signals. In another example, the first and second acoustic transducers may be in respective first and second rows of a two-row transducer array. In accordance with this example, the first and second acoustic transducers may be designed to have an acoustic parameter having respective first and second parameter values.

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Abstract: Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Abstract: A terminal device comprises a component and a circuit board. The circuit board comprises a circuit substrate and a solder mask layer, and wherein the circuit substrate comprises a medium layer and a circuit layer stacked with the medium layer. Openings with different depths are provided in the circuit board, and at least part of the component is accommodated in or arranged corresponding to the opening. This lowers an installation height between the component and the circuit board without affecting their performance.

Abstract: A wiring substrate includes a first conductor pattern, a second conductor pattern, an insulating layer interposed between the first and second patterns and having a through hole, and a plating conductor integrally formed with the second pattern and filling the through hole in the insulating layer such that the plating conductor is in contact with the first pattern. The through hole has an expansion part such that an opening width of the through hole on the first pattern side is widened, and the plating conductor includes a first plating film directly formed on inner wall of the through hole and a second plating film formed on the first plating film such that the minimum thickness of the first plating film in the expansion part is in the range of 55% to 95% of the minimum thickness of the first plating film in the through hole other than the expansion part.

Abstract: A laminated glass assembly, an electrical assembly for a laminated glass assembly and a method of forming a laminated glass assembly. The laminated glass assembly includes at least an outer glass plate having a first major surface and a second major surface, an inner ultra-thin glass plate having a first major surface and a second major surface and an intermediate film layer situated between the outer glass plate and the inner ultra-thin glass plate. The electrical assembly is positioned between the outer glass plate and the inner ultra-thin glass plate along with a conductive medium to provide a signal path between the laminated glass assembly and vehicular electrical circuitry.

Abstract: A multilayer substrate includes a resin multilayer body including, in a lamination direction, first and second laminate portions respectively including first and second thermoplastic resin layers, and a first interlayer connection conductor extending through the first thermoplastic resin layer. A storage elastic modulus of the first thermoplastic resin layer is lower than that of the second thermoplastic resin layer at a measurement temperature equal to or higher than a minimum melting point among melting points of metallic elements included in the first interlayer connection conductors and equal to or lower than melting points of the first thermoplastic resin layer and the second thermoplastic resin layer.

Abstract: A multilayer electronic component includes a body and first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction; a first external electrode including a first connection portion disposed on the third surface, and a first band portion extending from the first connection portion to a portion of the first surface; a second external electrode including a second connection portion disposed on the fourth surface, and a second band portion extending from the second connection portion to a portion of the first surface; an insulating layer disposed on the second surface and extending to the first and second connection portions; a first plating layer disposed on the first band portion; and a second plating layer disposed on the second band portion, wherein the insulating layer includes an oxide including silicon (Si).

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

Abstract: A power storage device having high capacitance is provided. A power storage device with excellent cycle characteristics is provided. A power storage device with high charge and discharge efficiency is provided. A power storage device including a negative electrode with low resistance is provided. A negative electrode for a power storage device includes a number of composites in particulate forms. The composites include a negative electrode active material, a first functional material, and a compound. The compound includes a constituent element of the negative electrode active material and a constituent element of the first functional material. The negative electrode active material includes a region in contact with at least one of the first functional material or the compound.

Abstract: A motherboard with shockproof, shakeproof and waterproof functions is installed in a cabinet of an electronic device, the motherboard includes a PCB board, wherein front surface of the PCB board is provided with a plurality of structural members, a camera seat unit, an audio seat unit, a functional seat unit, a holder seat and a battery seat with shockproof and shakeproof functions; wherein each of the structural members is dispersedly fixed on a side of the PCB board, wherein the structural member screws and fixes the PCB board inside the cabinet, and wherein each of the seats and the PCB board are coated with waterproof coating.

Abstract: A resin multilayer substrate includes a laminate including resin layers including a first resin layer and a second resin layer that are laminated, a via conductor in the first resin layer, and a joint portion that includes at least a portion in the second resin layer and is joined to the via conductor. The joint portion is more brittle than the via conductor. A linear expansion coefficient of the second resin layer is larger than a linear expansion coefficient of the via conductor and a linear expansion coefficient of the joint portion, and is smaller than a linear expansion coefficient of the first resin layer.

Abstract: A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: The main technical problem solved by the present disclosure is to provide a circuit board preparation method. The method includes: obtaining a to-be-processed plate comprising an insulating layer, a first copper layer, a second copper layer opposite to the first copper layer, a blind metalized hole, and a first tab facing the blind metalized hole; obtaining a white insulating material; laminating the white insulating material to a surface of the insulating layer, a surface of the first copper layer, a surface of the first tab, and a surface of the second copper layer to form a first white insulating medium layer and a second white insulating medium layer opposite to the first while insulating medium layer; and performing surface polishing for the first white insulating medium layer and grinding the first white insulating medium layer until the first tab is exposed to form a first white reflective layer.

Abstract: A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.

Abstract: A liquid crystal antenna and a method for forming a liquid crystal antenna are provided. The liquid crystal antenna includes a first substrate; a second substrate opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. A first conductive layer is disposed on a side of the first substrate facing toward the second substrate; a second conductive layer is disposed on a side of the second substrate facing toward the first substrate; the second conductive layer at least includes a plurality of radiation electrodes; an external metal layer is disposed on a side of the first substrate facing away from the liquid crystal layer; and the external metal layer is connected to a fixed potential.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Abstract: A dielectric layer for manufacturing a component carrier is described. The dielectric layer includes a first section including a first material having a first material property; and a second section including a second material having a second material property. The second material property is different from the first material property. A method for manufacturing such a component carrier and a component carrier including such a dielectric layer is further described.

Abstract: A copper-clad laminate includes an insulating layer formed of a cured product of a resin composition and a surface treated copper foil in contact with the insulating layer, in which the resin composition contains a compound having at least one group specified in the present application and a crosslinking type curing agent; and the surface treated copper foil is a surface treated copper foil including a finely roughened particle treatment layer of copper on at least one surface side of copper foil.

Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure and a through hole. An interposer is located in the through hole and has a higher density of connection elements than the stack. A first component is mounted on a first main surface of the interposer and a second component is mounted on a second main surface of the interposer. The first component and the second component are connected via the interposer.

Abstract: A resin multilayer substrate includes a stacked body provided by stacking and thermocompression bonding resin layers, a first conductor pattern inside the stacked body, and a first protective coating covering at least a first surface and a side surface of the first conductor pattern. The resin layers are made of a first thermoplastic resin, and the first protective coating is made of a second thermoplastic resin. Both of the first and second thermoplastic resins soften at a predetermined press temperature or less. The second thermoplastic resin has a storage modulus lower than a storage modulus of the first thermoplastic resin at a temperature equal to or less than the predetermined press temperature and equal to or more than room temperature.

Abstract: An object of the present invention is to provide a polymer film to which a metal-containing layer is stuck to produce a laminate having an excellent peel strength. Another object of the present invention is to provide a laminate and a substrate for high-speed communication. The polymer film of an embodiment of the present invention is a polymer film including a liquid crystal polymer, in which a difference between a melting start temperature and a melting end temperature in differential scanning calorimetry in a depth region up to 10 ?m of the polymer film from one surface toward the other surface of the polymer film is 5.0° C. to 50° C.

Abstract: Through the plasma spraying technology and the cold spraying high-speed deposition technology, an evenly distributed protective coating is formed on the surface of a plasma etching chamber. The protective coating, having a double-layer composite structure, includes a metal+Y2O3 coating as a metal+Y2O3 transition layer deposited by plasma spraying as a lower layer of the double-layer composite structure, and a high-purity Y2O3 ceramic coating coated on the metal+Y2O3 transition layer as an upper layer of the double-layer composite structure, the metal+Y2O3 transition layer is configured to reduce the difference in expansion coefficient between the Y2O3 ceramic coating and the metal substrate, and enhance the bonding force between the Y2O3 ceramic coating and the metal substrate; the high-purity Y2O3 ceramic coating is formed by depositing Y2O3 ceramic powders on the metal+Y2O3 transition layer at high speed through cold spraying high-speed deposition.

Abstract: An object of the present invention is to provide a polymer film having a low dielectric loss tangent and a small difference in a linear expansion coefficient from that of a copper foil; and a laminate.

Abstract: The problem to be solved by the invention is to provide a laminate capable of effectively enhancing thermal conductivity and adhesiveness, in spite of the relatively large thickness of a patterned metal layer. The laminate (1) according to the present invention includes a metal substrate (4), an insulating layer (2) laminated on one surface of the metal substrate (4), and a patterned metal layer (3) laminated on the surface of the insulating layer (2) on the side opposite to the metal substrate (4), the metal layer (3) is 300 ?m or more in thickness, and the insulating layer (2) includes boron nitride (12) and an inorganic filler (13) other than boron nitride.

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor penetrating through the second insulating layer and connecting the first and second conductor layers, and a coating film formed on a surface of the first conductor layer such that the coating film is adhering the first conductor layer and the second insulating layer. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is in contact with the connection conductor and the wiring pattern is covered by the coating film, the conductor pad of the first conductor layer has a surface facing the second insulating layer and having a first surface roughness higher than a surface roughness of a surface of the wiring pattern, and the coating film has opening such that the opening is exposing the conductor pad entirely.

Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and first shielding columns. The core layer includes an accommodating space, and the accommodating space has an inner side wall. The first shielding ring wall is disposed in the accommodating space and covers the inner side wall, in which the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding columns are disposed in the first insulating layer.

Abstract: Embodiments of the present disclosure relate to a printed circuit, a backlight unit, and a display device. The printed circuit on which a light source is mounted can be easily manufactured in a single form, by depositing and arranging a wiring layer on a substrate and mounting the light source on the wiring layer. Further, the printed circuit is arranged so that the wiring layer includes a plurality of bonding metal layers and a plurality of wiring metal layers, and a part of the bonding metal layer positioned between the plurality of wiring metal layers and disposed in an area overlapping a pad portion of the light source is removed. Therefore, even though the main metal layer of the wiring layer is removed during reworking, it is possible to provide the printed circuit capable of electrically connecting to the light source by the sub-metal layer of the wiring layer.

Abstract: A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.

Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: An electronic component includes: a body; first and second external electrodes including first and second head portions disposed on opposite end surfaces of the body; and first and second metal frames, the first metal frame including a first support portion bonded to the first head portion, and a first mounted portion extending from the first support portion, and the second metal frame including a second support portion bonded to the second head portion, and a second mounted portion extending from the second support portion. 0.2A?B?0.8A, in which an area of each of the first and second head portions is A, and an area of each of a region in which the first head portion and the first support portion are bonded to each other, and a region in which the second head portion and the second support portion are bonded to each other is B.

Abstract: The present application provides an asymmetric board, which includes the first master board, the second master board, and the insulating dielectric layer sandwiched between the first master board and the second master board, and the depth control grooves are disposed in the connection position between the units on the asymmetric board, and located on the surface of the second master board and extending a toward the side of the first master board, the depth control grooves provide space for the expansion of the second master board, reduce the stress of the units, and reduce the warping of the second master board. When the number of the depth control grooves in the first direction and/or the second direction is greater than 0, the depths of the depth control grooves increase by X from a center to an edge of the asymmetric board, and the X is greater than or equal to 0.

Abstract: Waveguides and methods for manufacturing a waveguide that include forming a first channel in a first layer of dielectric material, the first channel comprising one or more walls; forming a second channel in a second layer of dielectric material, the second channel comprising one or more walls; depositing electrically conductive material on the one or more walls of the first channel; depositing electrically conductive material on the one or more walls of the second channel; arranging the first layer adjacent to the second layer to form a stack with the first channel axially aligned with and facing the second channel; and heating the stack so that the conductive material on the one or more walls of the first channel and the conductive material on the one or more walls of the second channel connect to form the waveguide.

Abstract: A structure includes a first copper layer and a first carbon layer applied directly to a surface of the first copper layer, a second copper layer and a second carbon layer applied directly to a surface of the second copper layer, and an insulating core disposed between the first and second copper layers. Each of the first carbon layer and the second carbon layer faces toward and directly contacts the insulating core. The structure provides electrical power to a component of an electronic device.

Abstract: The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.

Abstract: A multilayer capacitor includes a body including a stack structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes are stacked with the dielectric layers interposed therebetween, external electrodes formed on an external surface of the body to be connected to the internal electrodes, and including a first electrode layer covering a first surface of the body to which the internal electrodes are exposed, and a second electrode layer covering the first electrode layer, a first metal oxide layer disposed between the first and second electrode layers and having a discontinuous region, and a second metal oxide layer covering at least a portion of a surface of the body on which the external electrodes are not disposed and having a multilayer structure.

Abstract: A component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and having a cavity delimited at least partially by a first polymer, and a component embedded in the cavity of the stack and being at least partially covered by a second polymer, wherein an anchoring interface is formed at an interface between the first polymer and the second polymer at which the first polymer and the second polymer are mechanically anchored with each other.

Abstract: A component carrier, wherein the component carrier includes: i) a layer stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, ii) a bendable portion which forms at least a part of the layer stack, and iii) a metal layer which forms at least a part of the bendable portion. Hereby, the metal layer extends over at least 75% of the area of the bendable portion.

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.

Abstract: A stretchable wiring board that includes a stretchable substrate having a first main surface with a first region, a second region adjacent the first region, and a third region adjacent the second region; a first stretchable wiring line on the first main surface and extending over the first region; an insulating layer extending over the first region and the second region; and a second stretchable wiring line extending over the first region, the second region, and the third region. When a thickness of the insulating layer is defined as Z2, and when a minimum value of a length of the second region in an extending direction of the second stretchable wiring line in a plan view of the stretchable wiring board is defined as Y, Y>Z2.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A method of forming a self-aligned electrical winding includes forming a first conductive turn in a first conductive layer around a planned leg hole and forming a second conductive turn in a second conductive layer around the planned leg hole. The method includes stacking a plurality of conductive layers aligned with each other, and separated from each other by at least one intervening insulation layer into a multilayer PCB stack. The method includes forming the planned leg hole through the multilayer PCB by removing the respective conductive portions of the first conductive turn and second conductive turn that extend into the planned leg hole. Forming the leg hole defines a first inner circumference for the first conductive turn and a second inner circumference for the second conductive turns, wherein the first inner circumference is aligned with the second inner circumference through forming the leg hole.

Abstract: Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor, and a coating film. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is formed in contact with the connection conductor and that the wiring pattern is covered by the coating film, the conductor pad has a surface facing the second insulating layer and having first surface roughness higher than surface roughness of a surface of the wiring pattern, and the coating film has opening exposing a portion of the surface of the conductor pad from the coating film and having area larger than area of interface between the conductor pad and the connection conductor and that the connection conductor is formed on the portion of the surface of the conductor pad and is separated from the coating film.