With Particular Substrate Or Support Structure Patents (Class 174/255)
  • Patent number: 10968519
    Abstract: A sheet material includes a resin layer containing a binder and catalyst particles, an electroless plating film on the side of one main surface of the resin layer and including first electroless plating films and a second electroless plating film, and a base material on the side of the other main surface of the resin layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 6, 2021
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Yuhei Horikawa, Yoshihiro Kanbayashi, Hisayuki Abe
  • Patent number: 10973140
    Abstract: A printed circuit board assembly (PCBA) controls an electrically-initiated device (EID) in an electric field. The PCBA includes a conductive layer, a dielectric layer, and a trans-conductive layer (TCL). The conductive layer of the PCBA designated protected areas. An electrical current with a predetermined current density is impressed in the conductive layer when the PCBA is in the electric field. The TCL is a nickel-metal composite metamaterial positioned between the conductive and dielectric layers and configured to change in shape or thickness in the electric field such that the impressed current is steered away from the conductive layer and into the dielectric layer to prevent premature activation of the EID. A system includes an outer housing, power supply, an EID such as a sonobuoy or medical device, and the PCBA, all of which are encapsulated in the housing. A method is also disclosed for manufacturing the PCBA.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 6, 2021
    Assignee: Sparton Corporation
    Inventors: Lendon L. Bendix, Derek Turner
  • Patent number: 10965004
    Abstract: A chip antenna module includes a substrate having layers; a chip antenna mounted on one surface of the substrate to radiate a radio signal, the chip antenna having a body portion formed of a dielectric substance, and a ground portion and a radiating portion disposed on opposite surfaces of the body portion; and an auxiliary patch disposed below the radiating portion on at least one layer of the substrate.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 30, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ju Hyoung Park, Myeong Woo Han, Jeong Ki Ryoo, Dae Ki Lim, Nam Ki Kim
  • Patent number: 10952320
    Abstract: A printed wiring board in the present disclosure includes a core layer, a first buildup layer, a second buildup layer, and a through hole. The core layer has a conductor circuit located on a surface of an insulator. The first buildup layer containing a first resin is laminated on a surface of the core layer. The second buildup layer containing a second resin is laminated on a surface of the first buildup layer. The through hole extends through the core layer, the first buildup layer, and the second buildup layer. The first resin and the second resin are different from each other. The second buildup layer includes a plurality of filled vias filled with a conductor which are located around a circumference of an opening of the through hole.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 16, 2021
    Assignee: Kyocera Corporation
    Inventors: Tadashi Watanabe, Masakazu Nakamura, Hiroshi Omodera, Tomoko Oyama
  • Patent number: 10944143
    Abstract: In a non-reciprocal circuit element, a permanent magnet is connected to one main surface of a magnetic plate, and a circuit board is connected to the other main surface of the magnetic plate, with a solder bump lying between the circuit board and the other main surface. The permanent magnet can control the transmission of electrical signal from each of a plurality of signal conductors of circuit board to a corresponding one of a plurality of input/output terminals of the magnetic plate. The non-reciprocal circuit element further includes an underfill material arranged between the magnetic plate and the circuit board. The magnetic plate has a through hole formed therein, the through hole extending from one main surface to the other main surface. The through hole has an empty space in which at least a part of a conductive film arranged in the through hole is exposed.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tetsuya Ueda, Hironobu Shibata, Yukinobu Tarui, Hidenori Ishibashi
  • Patent number: 10943874
    Abstract: The stiffening brace may include a set of borders dimensioned to substantially surround an integrated circuit, wherein each border includes (1) a portion of material that is positioned atop a perimeter of the integrated circuit and (2) an additional portion of material that extends beyond the perimeter of the integrated circuit such that the additional portion of material overhangs a circuit board to which the integrated circuit is soldered. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Juniper Networks, Inc
    Inventors: Peng Su, Valery Kugel, Jimmy Chun-Chuen Leung
  • Patent number: 10939556
    Abstract: An electronic component embedded substrate includes first insulating layer having a first through portion; a first electronic component disposed in the first through portion; a second insulating layer disposed on the first insulating layer and having a second through portion; a second electronic component disposed in the second through portion; and an insulating material covering at least a portion of each of the first electronic component and the second electronic component. The first through portion and the second through portion intersect, such that a portion of the first through portion and a portion of the second through portion overlap each other, on a plane.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Sung Sim, Ho Hyung Ham, Won Seok Lee
  • Patent number: 10939548
    Abstract: A component carrier is provided, which includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component on the stack; and stress propagation suppressing particles in at least part of the stack suppressing propagation of stress through the component carrier.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 2, 2021
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Artan Baftiri, Mikael Tuominen
  • Patent number: 10939563
    Abstract: A method of manufacturing a constituent for a component carrier is disclosed. The method includes providing an electrically conductive structure, forming a highly thermally conductive and electrically insulating or semiconductive structure on the electrically conductive structure, and subsequently, attaching a thermally conductive and electrically insulating structure, having a lower thermal conductivity than the highly thermally conductive and electrically insulating or semiconductive structure, on an exposed surface of the highly thermally conductive and electrically insulating or semiconductive structure.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 2, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Jonathan Silvano De Sousa, Markus Leitgeb
  • Patent number: 10925175
    Abstract: An electronic assembly and a method of forming an electronic assembly. The electronic assembly including a printed circuit board including a perimeter; a compression gasket extending around at least a portion of the perimeter of the printed circuit board; and a housing including a first wall and a housing side wall extending from the first wall, the first wall and housing side wall form a cavity, wherein the printed circuit board and the compression gasket are located within the cavity with the compression gasket positioned between the perimeter and the housing side wall.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 16, 2021
    Inventor: Ron G. Gipson
  • Patent number: 10925162
    Abstract: A printed circuit board is provided. The printed circuit board includes N power layers and a first via group. The N power layers are arranged in parallel and spaced from each other. The first via group includes M rows of vias which are disposed through the N power layers, where N and M are positive integers greater than 0. Each row of the M rows of vias is electrically connected to the first layer of the N power layers. A Pth row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively, where Q is a smallest positive integer greater than or equal to P((N?1)/M), and P is a positive integer less than or equal to M.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 16, 2021
    Assignee: Wiwynn Corporation
    Inventors: Cheng Fu Hsu, Cheng Wei Lin, Ting-Kai Wang
  • Patent number: 10925171
    Abstract: The present invention provides a surface treated copper foil in which a dropping of the roughening particles from a roughening treatment layer on the surface of the copper foil is suppressed and an occurrence of wrinkles or stripes when bonding with an insulating substrate is suppressed. The surface of the roughening treatment layer satisfies one or more of the following: a roughness Ra is 0.08 to 0.20 ?m, a roughness Rz is 1.00 to 2.00 ?m, a roughness Sq is 0.16 to 0.30 ?m, a roughness Ssk is ?0.6 to ?0.35, a roughness Sa is 0.12 to 0.23 ?m, a roughness Sz is 2.20 to 3.50 ?m, a roughness Sku is 3.75 to 4.50, and a roughness Spk is 0.13 to 0.27 ?m, a glossiness of a TD of the surface of the side of the roughening treatment layer of the surface treated copper foil is 70% or less.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: February 16, 2021
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Yuki Ori, Hideta Arai, Atsushi Miki, Ryo Fukuchi
  • Patent number: 10917966
    Abstract: An article includes a wafer having a body which defines a first surface and a second surface. The wafer defines a via having a via surface extending between the first and second surfaces through the body. An adhesion layer is positioned on the via surface. At least a portion of the via surface is free of the adhesion layer. A metallic component is positioned within the via and extends from the first surface to the second surface.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 9, 2021
    Assignee: Corning Incorporated
    Inventor: Shrisudersan Jayaraman
  • Patent number: 10916360
    Abstract: There is provided a method for manufacturing an electrical wire. The electrical wire includes a rod-like conductor having a shape corresponding to a predetermined wiring route and also having rigidity to enable the rod-like conductor to maintain the shape, and an insulation sheath covering the rod-like conductor. The method includes: preparing a plurality of rod-like preliminary conductors having the rigidity so as to correspond to a plurality of sub routes into which the wiring route is divided; processing at least one of the plurality of preliminary conductors into a shape conforming to the corresponding sub routes; connecting the plurality of preliminary conductors together to form the rod-like conductor; and forming the insulation sheath to cover the rod-like conductor.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Yazaki Corporation
    Inventors: Yuto Ito, Yoshio Shionome, Takashi Oguri, Jin Omori
  • Patent number: 10910157
    Abstract: An electronic component includes a multilayer capacitor, including a capacitor body, and a pair of external electrodes disposed on both ends of the capacitor body, respectively, and an interposer, including an interposer body, and a pair of external terminals disposed on both ends of the interposer body, respectively. The external terminals include bonding portions, mounting portions, and connection portions disposed to connect the bonding portions and the mounting portions to each other. Adhesives are provided between the external electrodes and the bonding portion. A height at which the adhesives fall along the connection portions of the external terminals is defined as t and a height of the interposer is defined as T, t/T satisfies 0.04?t/T?0.80.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Yoon Kim, Sang Soo Park, Woo Chul Shin
  • Patent number: 10912200
    Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive contact sheet group positioned on the surface of the substrate, where a part of the substrate is overlaid with solder resist, and there is a gap between the solder resist and the electro-conductive contact sheet group.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 2, 2021
    Assignees: Hisense Broadband Multimedia Technologies Co., Ltd., Hisense USA Corporation, Hisense International Co., Ltd.
    Inventors: Wei Zhao, Wei Cui, Lin Yu
  • Patent number: 10901544
    Abstract: A display substrate includes a substrate, a plurality of electrode leads disposed on the substrate, and a plurality of electrodes electrically disconnected with each other disposed on the substrate. Each electrode is in direct contact with one or more of the plurality of electrode leads, and a thickness of each electrode lead is greater than a thickness of a corresponding electrode. At least one of the plurality of electrode leads is respectively provided with at least one gap, and each gap is configured to electrically disconnect one of the plurality of electrodes that is in direct contact with a corresponding electrode lead from another one of the plurality of electrodes that is adjacent to the corresponding electrode lead.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: January 26, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Wang, Shengji Yang, Minghua Xuan, Li Xiao, Pengcheng Lu, Dongni Liu
  • Patent number: 10897074
    Abstract: A method for manufacturing a housing is described. The methods includes: providing a cover body defining a slot; filling a first material into the slot; and filling a second material into the slot to fill up the slot. A housing and a mobile terminal including the housing are further provided.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: January 19, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Cong Wang
  • Patent number: 10892227
    Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Doo Hwan Lee
  • Patent number: 10893618
    Abstract: A multilayer substrate includes a lamination body including a first resin substrate, a second resin substrate, and a bonding layer that are hot-pressed. A first conductor pattern including a surface defined by a plated film is disposed on a first surface of the first resin substrate. A second conductor pattern including a surface defined by a plated film is disposed on a second surface of the first resin substrate. A third conductor pattern including a surface defined by a plated film is disposed on a third surface of the second resin substrate. A fourth conductor pattern including a surface defined by a plated film is disposed on a fourth surface of the second resin substrate. The first conductor pattern is located closer to one outermost layer than the second conductor pattern is. The second conductor pattern is thinner than the first conductor pattern.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Naoki Gouchi, Shingo Ito
  • Patent number: 10887977
    Abstract: A method for manufacturing of a hybrid component carrier includes providing a first layer structure having at least one electrically insulating layer and at least one electrically conductive layer and forming a second layer structure on the first layer structure wherein the second layer structure has at least a first layer and a second layer. The first layer structure has a first density of electrically conductive elements. The second layer structure has a second density of electrically conductive elements. The second density of electrically conductive elements is greater than the first density of electrically conductive elements. The forming of the second layer structure on the first layer structure includes forming the first layer of the second layer structure on the first layer structure and subsequently forming the second layer of the second layer structure on the first layer of the second layer structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 5, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Leitgeb, Heinz Moitzi
  • Patent number: 10887987
    Abstract: An article includes a wafer having a body which defines a first surface and a second surface. The wafer defines a via having a via surface extending between the first and second surfaces through the body. An adhesion layer is positioned on the via surface. At least a portion of the via surface is free of the adhesion layer. A metallic component is positioned within the via and extends from the first surface to the second surface.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Corning Incorporated
    Inventor: Shrisudersan Jayaraman
  • Patent number: 10886171
    Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Kemal Aygun
  • Patent number: 10879159
    Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: December 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee
  • Patent number: 10867747
    Abstract: An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Noboru Kato, Yuki Wakabayashi, Bunta Okamoto, Naoto Ikeda, Takeshi Kurihara
  • Patent number: 10868112
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Patent number: 10869385
    Abstract: A circuit board structure includes a first core layer, a first build-up layer and a second build-up layer. The first core layer has a first surface and a second surface opposite to the first surface, wherein the first core layer includes a core dielectric material layer and at least one patterned conductive plate embedded within the core dielectric material layer, the core dielectric material layer includes a first sub-dielectric material and a second sub-dielectric material, and at least one interface exists in between the first sub-dielectric material and the second sub-dielectric material. The first build-up layer is disposed on the first surface of the first core layer, and the second build-up layer is disposed on the second surface of the first core layer.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 10856421
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 1, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ching-Hao Huang, Ho-Shing Lee, Yu-Cheng Lin
  • Patent number: 10847444
    Abstract: A through electrode substrate includes a substrate having a through hole extending through between a first face and a second face, a diameter of the through hole not having a minimum value inside the through hole; and a conductor arranged inside the through hole, wherein the through hole has a shape having a value obtained by summing a first to an eighth inclination angle at a first to an eighth position, respectively, of an inner face of the through hole of 8.0° or more, each of the first to the eighth inclination angle is an angle of the inner face with respect to a center axis of the through hole, and the first to the eighth position correspond to positions at distances of 6.25%, 18.75%, 31.25%, 43.75%, 56.25%, 68.75%, 81.25%, and 93.75%, respectively, from the first face in a section from the first face to the second face.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 24, 2020
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Satoru Kuramochi
  • Patent number: 10839122
    Abstract: A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen Thomas Quay, Yaoguang Wei, Bijian Chen, Ying Zhou
  • Patent number: 10834831
    Abstract: A component carrier includes a plurality of low density layer structures, and a plurality of high density layer structures having a higher density of electrically conductive structures than the plurality of low density layer structures, where the low density layer structures and the high density layer structures are alternatingly vertically stacked.
    Type: Grant
    Filed: October 29, 2016
    Date of Patent: November 10, 2020
    Assignee: AT&S (China) Co. Ltd.
    Inventor: Mikael Tuominen
  • Patent number: 10833023
    Abstract: A circuit module (100) includes an electronic component (30), a plurality of conductor posts (40), a mold layer (50) that seals a plurality of the electronic components (30) and the plurality of conductor posts (40), and a shield layer (60) on the mold layer (50). The electronic components (30) include a first electronic component (31) and second electronic components (32, 36). The plurality of conductor posts (40) includes a group of conductor posts (400) traversing between the first electronic component (31) and the second electronic components (32, 36). The shield layer (60) includes a slit (600) that, with respect to each conductor post (40) included in the group (400) of conductor posts, in a plan view, passes and extends between the conductor post (40) and the first electronic component (31), or between the conductor post (40) and the second electronic components (32, 36).
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 10, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Reiji Nakajima
  • Patent number: 10834816
    Abstract: A printed circuit board structure and a wiring method therefor are disclosed. The printed circuit board structure comprises a first wiring channel formed inside the printed circuit board for transmitting a circuit signal; a pin, connected to the first wiring channel for connecting a chip to the printed circuit board; the pin comprising an unused pin and a used pin, the used pin comprising a peripheral pin and an internal pin; wherein the printed circuit board further comprises a second wiring channel, the second wiring channel leads out the internal pin by means of covering at least a portion of the unused pin. By means of using a printed circuit board structure and a wiring method to configure pins of the printed circuit board, the number of printed circuit board layers is reduced, and the current carrying capacity is enhanced.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 10, 2020
    Assignee: CANAAN CREATIVE CO., LTD.
    Inventors: Xuguang Liu, Nangeng Zhang
  • Patent number: 10827617
    Abstract: An electronic device includes a printed circuit board (PCB) defining a cavity, a first component pad of the PCB positioned outside the cavity, and a second component pad of the PCB positioned on a bottom surface of the cavity. The first component pad has a first thickness, and the second component pad has a second thickness that is less than the first thickness of the first component pad. An electronic component, such as a surface mounted technology (SMT) component, is mounted to the second component pad within the cavity.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 3, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Dingyou Zhang, Nitesh Kumbhat, Li Sun, Sarah Haney, Chang Kyu Choi
  • Patent number: 10827283
    Abstract: A hearing aid circuit includes a plurality of sub-circuits implemented as a plurality of flexible circuit boards. In various embodiments, the plurality of flexible circuit boards includes a motherboard that can be used with multiple hearing aid models and different peripheral boards that can provide different hearing aid models with their unique styles and/or functional features. In various embodiments, the hearing aid circuit is assembled in an automated process that connects the motherboard to one or more peripheral circuit boards using surface mount technology (SMT).
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 3, 2020
    Assignee: Starkey Laboratories, Inc.
    Inventors: Mark Lyon, Susie Johansson
  • Patent number: 10819107
    Abstract: The disclosure relates to an electronic unit with a circuit board having at least one component arranged on a main surface of the circuit board and a casing element, which incorporates the at least one component, as well as with an ESD protection arrangement for the circuit board. According to the disclosure, open areas on the circuit board, which are not covered by the casing element, are covered with a gold layer directly mounted on a copper surface of the circuit board.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 27, 2020
    Assignee: ZF Freidrichshafen AG
    Inventors: Thomas Maier, Mike Vogel, Josef Loibl
  • Patent number: 10820408
    Abstract: A multi-layer circuit board comprising a carrier plate with an upper surface and a lower surface, and at least one electrically conductive upper inner layer located on the upper surface of the carrier plate and an electrically insulating upper intermediate layer located thereon, and an electrically conductive upper outer layer located thereon, forming the outermost layer of the upper surface. At least one electrically conductive lower inner layer is located on the lower surface of the carrier plate and an electrically insulating lower intermediate layer located thereon, and an electrically conductive lower outer layer located thereon, forming the outermost layer of the lower surface. The upper and/or lower outer layers are populated with components, and conductor paths in one of the inner layers are oriented in different directions from conductor paths in the other inner layer, and the region between the conductor paths is flooded with a voltage.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 27, 2020
    Assignee: ZF Friedrichshafen AG
    Inventor: Michael Sperber
  • Patent number: 10811329
    Abstract: The present invention relates to a ceramic substrate (100) comprising: a front side (100-1), which comprises: i) a power semiconductor (102-1, . . . , 102-n); and ii) a first metallic layer (104) comprising at least one first metallic plane contact (104-1, . . . , 104-n), which is configured to connect the power semiconductor (102-1, . . . , 102-n) to a first terminal (105-1, . . . , 105-n) on an edge (100-3) of the ceramic substrate (100); a back side (100-2), which comprises: i) a capacitor (103) which is attached to a ii) second metallic layer (108) comprising at least one second metallic plane contact (108-1, . . . , 108-n), which is configured to connect the capacitor (103) to a second terminal (107-1, . . . , 107-n) on the edge (100-3) of the ceramic substrate (100); and a metallic frame (110), which is configured to connect the first metallic layer (104) to the second metallic layer (108).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: October 20, 2020
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Peter Luerkens, Albert Garcia Tormo, Ulf Mueter
  • Patent number: 10804207
    Abstract: Embodiments relate to the fabrication of an interposer with nanofibers by an additive process to electrically connect two or more electronic components. The nanofibers are grown on a substrate away from a surface of the substrate. The nanofibers are plated with a conductive material such that the nanofibers are encompassed in a column of the conductive material. An insulative material fills at least the volume between the columns of conductive material. The substrate and the interposer is the remaining device. The interposer can be combined with a redistribution layer to connect electronic components of dissimilar pitch.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 13, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: John Michael Goward
  • Patent number: 10798821
    Abstract: A circuit board is provided that includes a plurality of insulating layers provided in a stack to have a first surface and a second surface. A via may extend from the first surface of the stack to the second surface of the stack. A passive device may be provided in the via.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventor: Carlos Gomez
  • Patent number: 10795242
    Abstract: A power consuming electronics device that dissipates internal device heat via a heat sink is disclosed. The power consuming electronics device includes first and second complementary housing parts. The first housing part includes a first surface ending at a first peripheral edge, and the second housing part including a second surface ending at a second peripheral edge. The power consuming electronics device also includes a heat sink having an air exposed surface that is interposed between the first and second peripheral edges. Surface edges of the air exposed surface abut the first and second peripheral edges of the housing parts and are respectively matched therewith in shape and dimension so that an overall composite surface formed by the first and second surfaces of the housing parts and the air exposed surface of the heat sink is substantially continuous and uniform.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: October 6, 2020
    Assignee: AVIGILON CORPORATION
    Inventors: Winson Chan, Thomas W. Holbrook, Colin Paul Janssen
  • Patent number: 10791625
    Abstract: A method for manufacturing a flexible printed circuit board, comprising: providing a flexible printed circuit substrate; defining first through holes and second through holes through the flexible printed circuit substrate; and forming first conductive pillars and second conductive pillars; and defining first grooves by removing a portion of each first conductive pillar and defining second grooves by removing a portion of each second conductive pillar; the first grooves and the second grooves are defined from an outer surface of the flexible printed circuit board on the second conductive pattern layer side to a surface of the second conductive pattern layer away from the first conductive pattern layer; each of the first grooves is aligned with and corresponds to one first conductive pillar, and each of the second grooves is aligned with and corresponds to one second conductive pillar.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 29, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited, HongQiSheng Precision Electronics (QinHuangDao) Co.,Ltd.
    Inventors: Xian-Qin Hu, Ming-Jaan Ho
  • Patent number: 10791623
    Abstract: An electronic device includes a first wiring substrate having a first corner part, a first ground pattern formed on a lower surface of the first wiring substrate with avoiding the first corner part, a second ground pattern formed on an upper surface of the first wiring substrate with avoiding the first corner part, a second wiring substrate provided above the first wiring substrate and including a second corner part above the first corner part, a third ground pattern formed on a lower surface of the second wiring substrate with avoiding the second corner part, a fourth ground pattern formed on an upper surface of the second wiring substrate with avoiding the second corner part, a plurality of terminals electrically connected to each of the first, second, third and fourth ground patterns, and an antenna fixed to the upper surface of the second wiring substrate at the second corner part.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 29, 2020
    Assignee: SHINKO ELECTRONIC INDUSTRIES CO., LTD.
    Inventor: Tomoharu Fujii
  • Patent number: 10785876
    Abstract: An intermediate printed board has a plurality of unit regions that are to be cut out and separated to become a plurality of individual printed circuit boards, respectively. The intermediate printed board includes a metal core substrate including: a metal layer; and a plating layer formed on each of a top surface and a bottom surface of the metal layer, the plating layer being absent in each of cutting regions, the cutting regions being regions on the intermediate printed board where the plurality of unit regions are separated so as to produce the plurality of individual printed circuit boards; an insulating layer formed so as to cover a surface of the metal core substrate; and a conductive pattern formed on the insulating layer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki
  • Patent number: 10779402
    Abstract: A printed circuit board (PCB) includes a dielectric plane and a ground plane parallel to and spaced apart from the dielectric plane. The dielectric plane includes a pair of signal traces and a 3-dimensional (3D) grounded (GND) fence located between the pair of signal traces. The 3D GND fence is electrically connected to the ground plane, and protrudes perpendicularly from the dielectric plane. The 3D GND fence is located equidistant from each of the pair of signal traces, and the 3D GND fence is configured to block electromagnetic interference (EMI) from a first of the pair of signal traces to a second of the pair of the signal traces. The pair of signal traces is configured to form part of a noise-sensitive electronic circuit. The 3D GND fence may have a rectangular configuration.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Kai Chong Ng, Natasya Athirah Abdul Khalid, Florence Su Sin Phun, Yee Hung See Tau, Asmah Truky, Ying Ern Ho
  • Patent number: 10776553
    Abstract: The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: September 15, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Lin Shen, Yongming Xiong, Shahbaz Mahmood, Maurilio De Nicolo
  • Patent number: 10779409
    Abstract: A printed circuit board including: an insulating material; a metal layer stacked on a surface of the insulating material; and a via hole passing through the metal layer and the insulating material. The metal layer decreases in thickness in a region adjacent to the via hole, and an interface between the insulating material and the metal layer includes a region that is directed toward the via hole.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byung-Duk Na, Hye-Won Jung, Jae-Sung Sim, Mi-Sun Hwang, Hee-Joon Chun, Deok-Man Kang, Sun-A Kim
  • Patent number: 10779404
    Abstract: A circuit board pad resonance control system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. A first connector pad receives the signal transmission line adjacent a first end of that connector pad. The first connector pad includes a mounting surface that mounts directly to a coupling element that is configured to couple a subsystem to the board, and reduces a resonance that is produced by an open portion of a signal transmission path that is created when the coupling element is directly mounted to the mounting surface of the first connector pad in a first orientation. In a specific example, the mounting surface may include a plurality of protrusions, a plated surface, and/or a mask that reduces the conductivity of the connector pad which reduces signal integrity issues due to resonance.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 15, 2020
    Assignee: Dell Products L.P.
    Inventors: Vasa Mallikarjun Goud, Chun-Lin Liao, Bhyrav M. Mutnury
  • Patent number: 10767085
    Abstract: There is provided a semiconductor-bonding resin composition having excellent thermally conductive property and electrically conductive property and suitable for joining a power semiconductor element and an element support member. There are provided: a semiconductor-bonding resin composition containing (A) a bismaleimide resin including an aliphatic hydrocarbon group on a main chain, (B) a curing agent, (C) a filler containing electrically conductive particles having a specific gravity of 1.1 to 5.0, and (D) silver microparticles having an average particle size of 10 to 300 nm; a semiconductor-bonding sheet obtained using the semiconductor-bonding resin composition; and a semiconductor device including a semiconductor joined by the semiconductor-bonding sheet.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 8, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Masakazu Fujiwara, Hiroshi Fukukawa
  • Patent number: 10770385
    Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Brian W. Quinlan, Krishna R. Tunga