With Particular Substrate Or Support Structure Patents (Class 174/255)
  • Patent number: 11325828
    Abstract: A method for manufacturing a millimeter scale electromechanical device includes coupling a stainless steel ply to a polymer carrier ply, coating the stainless steel ply in a photo resist material, masking the photoresist material, exposing the photoresist material to cure a portion of the photoresist material, developing the photoresist material to remove uncured photoresist material from the stainless steel ply, chemically etching the stainless steel ply to remove a patterned portion of the stainless steel ply, dissolving the polymer carrier ply to release unwanted chips of the stainless steel ply, and adhering the patterned stainless steel ply to a flexible material ply to form a sub-laminate.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: May 10, 2022
    Assignee: Vibrant Composites Inc.
    Inventors: Pratheev S. Sreetharan, Andrew Baisch, Alina Visco, Michael Karpelson
  • Patent number: 11324119
    Abstract: Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Achronix Semiconductor Corporation
    Inventors: Hansel Desmond Dsilva, Sasikala J, Abhishek Jain, Amit Kumar
  • Patent number: 11316240
    Abstract: A transition structure for millimeter wave is provided. The transition structure includes a first layer signal element coupled to an end of a first transmission line and a plurality of first layer ground elements surrounding the end of the first transmission line equidistantly from the end of the first transmission line and disposed along two opposite sides of a strip body of the first transmission line equidistantly from the strip body of the first transmission line. The transition structure further includes an intermediate layer signal element coupled to the first layer signal element and a plurality of intermediate layer ground elements surrounding the intermediate layer signal element quasi-coaxially. A multilayer transition structure including a multilayer structure and the transition structure is also provided. Therefore, the problem of operating frequency caused by the thickness of the multilayer structure can be overcome, thereby increasing the resonance frequency of the multilayer structure.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: April 26, 2022
    Assignee: TMY Technology Inc.
    Inventors: Su-Wei Chang, Chueh-Jen Lin, Wen-Tsai Tsai, Tzu-Chieh Hung, Yang Tai, Chien-Tse Fang, Po-Chia Huang, Tzu-Wen Chiang, Shao-Chun Hsu, Yu-Cheng Lin, Wei-Yang Chen
  • Patent number: 11309300
    Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kil-soo Kim
  • Patent number: 11309271
    Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 19, 2022
    Assignee: XINTEC INC.
    Inventors: Jiun-Yen Lai, Chia-Hsiang Chen
  • Patent number: 11306126
    Abstract: A film of the present invention contains a polypeptide derived from spider silk proteins. The decomposition temperature of the film is 240 to 260° C. The film absorbs ultraviolet light having a wavelength of 200 to 300 nm and has a light transmittance of 85% or more at a wavelength of 400 to 780 nm. The film is transparent and colorless in a visible light region. A method for producing a film of the present invention includes: dissolving a polypeptide derived from spider silk proteins in a dimethyl sulfoxide solvent to prepare a dope; and cast-molding the dope on a surface of a base. Thus, the present invention provides a spider silk protein film that can be formed easily and has favorable stretchability, and a method for producing the same.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: April 19, 2022
    Assignee: SPIBER INC.
    Inventors: Kaori Sekiyama, Mizuki Ishikawa, Shinya Murata
  • Patent number: 11310904
    Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 19, 2022
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Po-Han Lee, Wei-Ming Chien
  • Patent number: 11302538
    Abstract: A semiconductor device manufacturing method includes processes of: applying a protective film precursor solution over an end of each of a plurality of semiconductor element structures and a side surface and a bottom surface of a groove; roughly drying a solvent in the protective film precursor solution to form a protective film; and performing full-curing to evaporate a solvent in the protective film after a process of cutting between the plurality of semiconductor element structures or a process of peeling a plurality of semiconductor elements from a dicing tape.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yosuke Nakata
  • Patent number: 11302643
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 12, 2022
    Inventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
  • Patent number: 11296270
    Abstract: Optoelectronic modules exhibiting relatively small thickness and methods for their manufacture are disclosed. The optoelectronic modules include substrates and transparent covers. Each optoelectronic module includes a transparent substrate on which an optoelectronic component is mounted. The optoelectronic component can be sensitive to and/or operable to generate a particular wavelength of electromagnetic radiation. The transparent substrate is transmissive to the particular wavelength of electromagnetic radiation. In some instances, the transparent substrate is composed, at least partially of glass.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 5, 2022
    Assignee: ams Sensors Singapore Pte. Ltd.
    Inventors: Bojan Tesanovic, Nicola Spring
  • Patent number: 11291125
    Abstract: A multilayer substrate includes a laminate, first and second signal lines, first and second ground conductors, and interlayer connection conductors. The first and second signal lines extend along a transmission direction and include parallel extending portions that extend in parallel or substantially in parallel with each other. The first and second ground conductors sandwich the first and second signal lines in a laminating direction. The first and second ground conductors respectively include a first opening and a third opening between the signal lines when viewed from the laminating direction, and respectively include second openings and fourth openings disposed outside in a width direction orthogonal or substantially orthogonal to the transmission direction in the parallel extending portions when viewed from the laminating direction. The interlayer connection conductors are disposed in the transmission direction and at least between the signal lines.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: March 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomohiro Nagai, Shigeru Tago, Kazuhiro Yamaji
  • Patent number: 11282777
    Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 11270934
    Abstract: A semiconductor device includes a redistribution layer, a bump bonded to a first surface of the redistribution layer, and a chip bonded to a second surface of the redistribution layer. The redistribution layer includes an insulating layer, a conductive member connecting the bump to the chip and being provided inside the insulating layer, a bonding electrode connected between the conductive member and the bump, and a conductive layer provided between the insulating layer and the conductive member and between the bonding electrode and the conductive member. A resistivity of the conductive member is lower than a resistivity of the conductive layer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: March 8, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, KIOXIA CORPORATION
    Inventors: Takayuki Tajima, Kazuo Shimokawa
  • Patent number: 11272621
    Abstract: A method for fabricating a flexible electronic device, including the steps of: providing channels on a rigid substrate; adhering a flexible substrate to the rigid substrate with an adhesive; fabricating an electronic device on the flexible substrate; injecting a chemical substance into the channels; and reacting the chemical substance with the adhesive and peeling the flexible substrate from the rigid substrate. The rigid substrate comprises a first surface, a second surface opposite the first surface, and a side wall extending between the first surface and the second surface. The channels are provided on the first surface of the rigid substrate. The channels are in communication with an injection port, the injection port is located on the side wall of the rigid substrate, and a portion of the side wall is located between the injection port and the first surface.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 8, 2022
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO., LTD.
    Inventors: Zihong Liu, Xiaojun Yu, Peng Wei
  • Patent number: 11266020
    Abstract: Circuit assemblies can be electrically interconnected by providing a circuit assembly having a top surface, a bottom surface, and a perimeter edge connecting the top and bottom surfaces, the perimeter edge being formed of insulative material and having a plurality of conductive features embedded in and exposed on the surface of the edge. The conductive features are arranged in contact sets, and each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features. Each contact set includes conductive features that together form a distributed electrical connection to a single node. The insulative material is selectively removed to form recesses adjacent the conductive features exposing additional surface contact areas along lateral portions of the conductive features in the recesses.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: March 1, 2022
    Assignee: Vicor Corporation
    Inventors: Patrizio Vinciarelli, Robert Joseph Balcius, Steven P. Sadler, Mark Andrew Thompson
  • Patent number: 11262880
    Abstract: A high performance touch sensor according to the present invention comprises: a substrate; a first detection electrode formed on the substrate; an insulation layer formed on the first detection electrode; a second detection electrode formed on the insulation layer; and a protection layer formed on the second detection electrode, wherein one of the first detection electrode and the second detection electrode has a triple-film structure including a metal oxide and a thin film metal laminated on each other, and the other one includes a metal pattern. Therefore, the present invention can implement touch sensor having a high resolution and a large area while simultaneously satisfying a low resistance characteristic and an optical characteristic, facilitate progress of a high-temperature process, and diversify the substrate.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 1, 2022
    Assignee: Dongwoo Fine-Chem Co., Ltd.
    Inventors: Jae Hyun Lee, Ju In Yoon, Keon Kim, Byung Jin Choi
  • Patent number: 11257746
    Abstract: A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: February 22, 2022
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Boris Vaisband, Subramanian S. Iyer, Adeel A. Bajwa
  • Patent number: 11247265
    Abstract: An iron powder and method of making an iron powder. The method includes a step of neutralizing an acidic aqueous solution containing a trivalent iron ion and a phosphorus-containing ion, with an alkali aqueous solution, so as to provide a slurry of a precipitate of a hydrated oxide, or a step of adding a phosphorus-containing ion to a slurry containing a precipitate of a hydrated oxide obtained by neutralizing an acidic aqueous solution containing a trivalent iron ion with an alkali aqueous solution. A silane compound is added to the slurry so as to coat a hydrolysate of the silane compound on the precipitate of the hydrated oxide. The precipitate of the hydrated oxide after coating is recovered through solid-liquid separation, the recovered precipitate is heated to provide iron particles coated with a silicon oxide, and a part or the whole of the silicon oxide coating is dissolved and removed.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 15, 2022
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Hidenori Yamaji, Masahiro Gotoh
  • Patent number: 11252817
    Abstract: A printed wiring board includes first, second, and third wiring layers, first and second insulating members, and first and second vias. The first wiring layer includes a recognition mark and a first wiring on a first surface. The second wiring layer includes a first pad and a second wiring. The third wiring layer includes a third wiring. The first via penetrates the first insulating member and electrically connects the recognition mark to the first pad. The second via penetrates the second insulating member and electrically connects the first pad to the third wiring. The first pad and the first and second vias are in a region within an outer perimeter of the recognition mark when viewed from a direction orthogonal to the first surface.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 15, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Naoki Kimura, Hiroaki Komaki
  • Patent number: 11246224
    Abstract: A method for manufacturing a printed wiring board includes forming a conductor layer including first and second pads on an insulating layer, forming a dry film resist layer on the insulating and conductor layers, forming first and second openings exposing the first and second pads, applying first metal plating to form first and second base plating layers on the first and second pads, applying second metal plating to form a first top plating layer of a first post and portion of a second top plating layer of a second bump post, applying the second metal plating further to form second portion of the second top layer of the second post, removing the dry film resist layer, forming a solder resist layer to cover the first and second posts, and thinning the solder resist layer over entire surface to position the first and second top layers outside the solder resist layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 8, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoji Sawada, Shuto Iwata
  • Patent number: 11229116
    Abstract: A board assembly sheet includes a plurality of mounting boards each for mounting an electronic component. The mounting boards are defined in the board assembly sheet. The mounting board has a total thickness of 60 ?m or less. The board assembly sheet has a through hole passing through the board assembly sheet in a thickness direction. The through hole is formed to be along an end edge of the mounting board or along a phantom line extending along the end edge.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 18, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Hiromoto Haruta, Shuichi Wakaki
  • Patent number: 11225563
    Abstract: The disclosure provides a composite for forming an insulating substrate. The composite includes 100 parts by weight of a liquid crystal polymer and 0.5-85 parts by weight of a dielectric additive. The liquid crystal polymer has a repeating unit represented by in which Ar is 1,4-phenylene, 1,3-phenylene, 2,6-naphthalene, or 4,4?-biphenylene, Y is —O— or —NH—, and X is carboxamido, imido/imino, amidino, aminocarbonylamino, aminothiocarbonyl, aminocarbonyloxy, aminosulfonyl, aminosulfonyloxy, aminosulfonylamino, carboxyl ester, (carboxyl ester)amino, (alkoxycarbonyl)oxy, alkoxycarbonyl, hydroxyamino, alkoxyamino, cyanato, isocyanato, or a combination thereof.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 18, 2022
    Assignee: AZOTEK CO., LTD.
    Inventor: Hung-Jung Lee
  • Patent number: 11222850
    Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.
    Type: Grant
    Filed: April 12, 2020
    Date of Patent: January 11, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yao-Chun Su, Chih-Jung Hsu, Yi-Jou Lin, I-Hsuan Peng
  • Patent number: 11218031
    Abstract: A planar-type wireless power-receiving circuit module includes a planar ground conductor, a substrate, a power-receiving coil, and a magnetic sheet. The planar ground conductor has a cavity in the middle section thereof. The substrate is disposed on a first main surface of the planar ground conductor. The substrate includes dielectric layers stacked on top of each other in a manner so as to form electronic circuitry. The power-receiving coil is electrically connected to the electronic circuitry and is disposed in the cavity. The magnetic sheet overlaps the power-receiving coil when the planar ground conductor is viewed in plan. The magnetic sheet is part of a path of magnetic flux passing through the power-receiving coil and is disposed on a first main surface of the power-receiving coil.
    Type: Grant
    Filed: January 16, 2021
    Date of Patent: January 4, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koyo Kaiwa, Tatsuya Hosotani
  • Patent number: 11217497
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 11211359
    Abstract: A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 28, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Michael J. Seddon
  • Patent number: 11212912
    Abstract: Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Benito Joseph Rodriguez, Shu-Ming Chang, Dillip Kumar Dash, Po Chun Yang, Juan-Yi Wu
  • Patent number: 11211307
    Abstract: A semiconductor substrate includes a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer. The dielectric insulation layer includes a first material having a thermal conductivity of between 25 and 180 W/mK, and an insulation strength of between 15 and 50 kV/mm, and an electrically conducting or semiconducting second material evenly distributed within the first material.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies AG
    Inventors: Georg Troska, Hans Hartung, Marianna Nomann
  • Patent number: 11202368
    Abstract: A power plane structure for a printed circuit board includes a copper layer, and a carbon layer applied directly to a surface of the copper layer. The carbon layer can include graphite or graphene. In additional embodiments, a duplicate power plane structure for a printed circuit board includes two power planes separated by an insulating core, each power plane including a copper layer and a carbon layer applied directly to a surface of the copper layer.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: December 14, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Joel Goergen, Jessica Kiefer, Alpesh Umakant Bhobe, Kameron Rose Hurst, D. Brice Achkir, Amendra Koul, Scott Hinaga, David Nozadze
  • Patent number: 11166387
    Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 2, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin
  • Patent number: 11165127
    Abstract: The filter unit has a center frequency and comprises a first dielectric substrate, a first conducting plane, and at least one transmission arrangement. The at least one transmission arrangement comprises a shunt node which has a shunt connection to the conducting plane. The electrical length of the shunt connection defines the center frequency of the filter unit. The transmission arrangement further comprises a plurality of transmission lines connected in series between an input port and an output port, wherein each port is connectable to auxiliary systems with a system impedance. Moreover, each transmission line has a characteristic impedance and wherein the characteristic impedance of each transmission line is less than the system impedance.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 2, 2021
    Assignee: SAAB AB
    Inventor: Hans-Olof Vickes
  • Patent number: 11152557
    Abstract: A thermoelectric module assembly for thermally conditioning a component is includes first and second heat spreaders spaced apart from one another and at least one thermoelectric sub-assembly between and in thermal communication with the first and second heat spreaders. The at least one thermoelectric sub-assembly includes a plurality of thermoelectric devices and a printed circuit board having a plurality of electrical conduits. Each of the thermoelectric devices has a first end portion and a second end portion, the second end portion opposite from the first end portion, the first end portion mechanically coupled to the printed circuit board and in electrical communication with the plurality of electrical conduits, and the second end portion spaced from the printed circuit board.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: October 19, 2021
    Assignee: GENTHERM INCORPORATED
    Inventors: Vladimir Jovovic, Eric Poliquin, Ellen M. Heian
  • Patent number: 11140769
    Abstract: A flexible circuit board capable of transmitting high frequency signals with reduced attenuation includes two outer wiring boards enclosing an inner wiring board. The inner wiring board includes a first conductive wiring layer and a first substrate layer. The first conductive wiring layer includes a signal line and two ground lines on both sides of the signal line. The first substrate layer covers a side of the first conductive wiring layer and defines first through holes which expose the signal line. Each of the two outer wiring boards includes a second substrate layer and a second conductive wiring layer. The second substrate layer abuts the inner wiring board and defines second through holes aligning with the first through holes, to partially surround the signal line with air of very low dielectric constant. A method for manufacturing the flexible circuit board is also disclosed.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 5, 2021
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Bao-Jun Li, Yang Li, Yan-Lu Li, Li-Kun Liu
  • Patent number: 11139234
    Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 5, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Yu-Hua Chen
  • Patent number: 11133484
    Abstract: Disclosed herein is an OLED lighting apparatus which can compensate for high sheet resistance of a first electrode formed of a transparent conductive material while improving light extraction efficiency through enhancement in aperture ratio. For this purpose, the OLED lighting apparatus omits auxiliary wires and, instead of the auxiliary wires, includes a first auxiliary wire and a second auxiliary wire to secure low resistance. As a result, the OLED lighting apparatus can compensate for high sheet resistance of the first electrode, thereby achieving normal light emission without reduction in luminance due to current drop when implemented as a large-area high-resolution lighting apparatus.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 28, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Shin-Bok Lee
  • Patent number: 11119538
    Abstract: A flexible display panel and a flexible display device are provided. The flexible display panel includes: a first insulating layer; a plurality of leads disposed above the first insulating layer, the plurality of leads passing through a predetermined bending region of the flexible display panel; a second insulating layer above respective one of the leads; where at least one of the leads is provided with at least one first hollow portion in the predetermined bending region, and the first insulating layer and the second insulating layer are connected via the at least one first hollow portion. In this way, product performance can be improved.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 14, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Yongda Ma, Xueguang Hao, Yong Qiao
  • Patent number: 11116115
    Abstract: A high power density power supply includes at least one power module and a cooling fan in a casing. A first filter circuit board facing upward is provided below the cooling fan. A second filter circuit board facing downward is provided above the cooling fan. The back of the second filter circuit board is provided with a plurality of buffer pads. An insulating plate is disposed on the buffer pads to completely cover the top of the second filter circuit board. Thereby, the insulating plate provided an insulating effect between an upper cover of the casing and the second filter circuit board to prevent the second filter circuit board from directly contacting the upper cover to form a short circuit, so as to improve the safety of the power supply.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 7, 2021
    Assignee: CHYNG HONG ELECTRONIC CO., LTD.
    Inventor: Mu-Chun Lin
  • Patent number: 11114388
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
  • Patent number: 11109492
    Abstract: Provided is a structure that has highly reliable electroconductive pattern regions, that offers an extremely simple manufacturing process, and that has excellent electrical insulation between the electroconductive pattern regions. This structure (10) having electroconductive pattern regions is provided with a support (11), and, on a surface configured by the support, a layer (14) in which insulation regions (12) containing a copper oxide- and phosphorus-containing organic substance and electroconductive pattern regions (13) containing copper are disposed next to one another. This stack is provided with: a support, a coating layer containing copper oxide and phosphorus and disposed on a surface configured by the support; and a resin layer disposed so as to cover the coating layer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 31, 2021
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Masato Saito, Toru Yumoto, Masanori Tsuruta
  • Patent number: 11102880
    Abstract: A high-frequency board includes an insulating substrate, a first line conductor, a second line conductor, a capacitor, a first bond, and a second bond. The insulating substrate has a recess on its upper surface. The first line conductor extends from an edge of the recess on the upper surface of the insulating substrate. The second line conductor faces the first line conductor across the recess on the upper surface of the insulating substrate. The capacitor overlaps the recess. The first bond joins the capacitor to the first line conductor. The second bond joins the capacitor to the second line conductor, and is spaced from the first bond.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: August 24, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Yoshiki Kawazu
  • Patent number: 11098195
    Abstract: A resin composition according to the present invention contains a cyanate compound (A). Further, the resin composition according to the present invention contains a maleimide compound (B) and/or an epoxy resin (C); and primary hexagonal boron nitride particles (D) having an average aspect ratio of 4 to 10.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 24, 2021
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Yoshihiro Nakazumi, Kentaro Takano
  • Patent number: 11096271
    Abstract: A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 17, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Brian K. Atwood, Thang D. Nguyen, Sankerlingam Rajendran, Douglas R. Gentry, Walter B. Aschenbeck, Jr.
  • Patent number: 11088052
    Abstract: A surface mount electronic device providing an electrical connection between an integrated circuit (IC) and a printed circuit board (PCB) is provided and includes a die and a dielectric material formed to cover portions of the die. Pillar contacts are electrically coupled to electronic components in the die and the pillar contacts extend from the die beyond an outer surface of the die. A conductive ink is printed on portions of a contact surface of the electronic device package and forms electrical terminations on portions of the dielectric material and electrical connector elements that connect an exposed end surface of the pillar contacts to the electrical terminations.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abram M. Castro
  • Patent number: 11088064
    Abstract: An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 10, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Robert Francis Darveaux, David McCann, John McCormick, Louis W. Nicholls
  • Patent number: 11075175
    Abstract: A semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, and an inductance sensing part having a coil form and electrically connected to the semiconductor chip.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoo Rim Cha, Joo Hwan Jung, Jung Chul Gong, Yong Ho Baek, Young Sik Hur
  • Patent number: 11069838
    Abstract: A light-emitting device includes a light-emitting element having an element front surface and an element back surface spaced apart from each other in a first direction, a supporting member on which the light-emitting element is mounted, and a light-transmitting resin formed on the supporting member to cover the light-emitting element. The supporting member includes a base having a base front surface and a base back surface opposite to the base front surface, and first and second wirings each disposed on the base and electrically connected to the light-emitting element. The light-emitting element is mounted on the support member with the element back surface facing the base front surface.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 20, 2021
    Assignee: ROHM CO, LTD.
    Inventor: Sosuke Murata
  • Patent number: 11063017
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 13, 2021
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 11064603
    Abstract: Provided is an electronic apparatus capable of improving time margin. The electronic apparatus includes: a base substrate including a substrate base including a plurality of layers and a plurality of wiring layers between the layers; a controller chip and at least one memory semiconductor chip mounted on the base substrate; a signal line disposed in one of the wiring layers and connecting the controller chip to the at least one memory semiconductor chip; and a pair of open stubs disposed in another wiring layer, connected to both ends of the signal line, and extending to face each other with a gap.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-woon Park, Jin-an Lee
  • Patent number: 11052422
    Abstract: An electronic component manufacturing method includes a blotting process of bringing a conductive paste applied to an end portion of each electronic component body held by a jig into contact with a surface of a surface plate. The blotting process includes simultaneous performance of a distance changing process of changing the distance between an end face of each electronic component body and the surface of the surface plate and a position changing process of changing a two-dimensional position where the end face of the electronic component body is projected on the surface of the surface plate in such a manner that the direction of the movement of two-dimensional position in parallel to the surface of the surface plate successively varies (e.g., along a circular path).
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 6, 2021
    Assignee: Creative Coatings Co., Ltd.
    Inventors: Eiji Sato, Hitoshi Sakamoto
  • Patent number: 11057984
    Abstract: A circuit includes a printed circuit board including a first portion defining a window formed as a first void on a first side of the printed circuit board and a second portion defining a cavity formed as a second void opposite the first void on a second side of the printed circuit board. The circuit further includes a heat sink inserted in the second void, the heat sink having a first side forming a bottom of the first void and the bottom of the first void within the printed circuit board. The circuit yet further includes at least one electronic circuit die mounted to the first side of the heat sink and electrically coupled to the first side of the printed circuit board.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 6, 2021
    Assignee: II-VI DELAWARE, INC.
    Inventors: Steven C. Bird, Henry Meyer Daghighian