Abstract: A multilayer capacitor includes a body including a stack structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes are stacked with the dielectric layers interposed therebetween, external electrodes formed on an external surface of the body to be connected to the internal electrodes, and including a first electrode layer covering a first surface of the body to which the internal electrodes are exposed, and a second electrode layer covering the first electrode layer, a first metal oxide layer disposed between the first and second electrode layers and having a discontinuous region, and a second metal oxide layer covering at least a portion of a surface of the body on which the external electrodes are not disposed and having a multilayer structure.

Abstract: A component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and having a cavity delimited at least partially by a first polymer, and a component embedded in the cavity of the stack and being at least partially covered by a second polymer, wherein an anchoring interface is formed at an interface between the first polymer and the second polymer at which the first polymer and the second polymer are mechanically anchored with each other.

Abstract: A component carrier, wherein the component carrier includes: i) a layer stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, ii) a bendable portion which forms at least a part of the layer stack, and iii) a metal layer which forms at least a part of the bendable portion. Hereby, the metal layer extends over at least 75% of the area of the bendable portion.

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

Abstract: A stretchable wiring board that includes a stretchable substrate having a first main surface with a first region, a second region adjacent the first region, and a third region adjacent the second region; a first stretchable wiring line on the first main surface and extending over the first region; an insulating layer extending over the first region and the second region; and a second stretchable wiring line extending over the first region, the second region, and the third region. When a thickness of the insulating layer is defined as Z2, and when a minimum value of a length of the second region in an extending direction of the second stretchable wiring line in a plan view of the stretchable wiring board is defined as Y, Y>Z2.

Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: A method of forming a self-aligned electrical winding includes forming a first conductive turn in a first conductive layer around a planned leg hole and forming a second conductive turn in a second conductive layer around the planned leg hole. The method includes stacking a plurality of conductive layers aligned with each other, and separated from each other by at least one intervening insulation layer into a multilayer PCB stack. The method includes forming the planned leg hole through the multilayer PCB by removing the respective conductive portions of the first conductive turn and second conductive turn that extend into the planned leg hole. Forming the leg hole defines a first inner circumference for the first conductive turn and a second inner circumference for the second conductive turns, wherein the first inner circumference is aligned with the second inner circumference through forming the leg hole.

Abstract: Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a connection conductor, and a coating film. The first conductor layer includes a conductor pad and a wiring pattern such that the conductor pad is formed in contact with the connection conductor and that the wiring pattern is covered by the coating film, the conductor pad has a surface facing the second insulating layer and having first surface roughness higher than surface roughness of a surface of the wiring pattern, and the coating film has opening exposing a portion of the surface of the conductor pad from the coating film and having area larger than area of interface between the conductor pad and the connection conductor and that the connection conductor is formed on the portion of the surface of the conductor pad and is separated from the coating film.

Abstract: A multilayer coil component 1 includes an element body 2, a pair of terminal electrodes 3, and a glass layer G provided on the terminal electrode 3. Each of the pair of terminal electrodes 3 is provided with a plurality of first projecting portions 33 tapered toward the other facing terminal electrode 3 side in an end portion 31b facing the side in the facing direction of a pair of end surfaces 2a and 2b. The glass layer G is provided along the edge of the terminal electrode 3 including at least the first projecting portion 33 in the end portion 31b of the terminal electrode 3.

Abstract: A composite substrate that includes: an upper ceramic layer; a lower ceramic layer; a middle resin layer between the upper ceramic layer and the lower ceramic layer; and a side surface resin layer on all side surfaces of the composite substrate, wherein the middle resin layer and the side surface resin layer are integral resin layers.

Abstract: A manufacturing method of an embedded metal mesh flexible transparent electrode and application thereof; the method includes: directly printing a metal mesh transparent electrode on a rigid substrate by using an electric-field-driven jet deposition micro-nano 3D printing technology; performing conductive treatment on a printed metal mesh structure through a sintering process to realize conductivity of the metal mesh; respectively heating a flexible transparent substrate and the rigid substrate to set temperatures; completely embedding the metal mesh structure on the rigid substrate into the flexible transparent substrate through a thermal imprinting process; and separating the metal mesh completely embedded into the flexible transparent substrate from the rigid substrate to obtain the embedded metal mesh flexible transparent electrode.

Abstract: The present application discloses a differential signal routing line of a circuit board and a circuit board, which comprises a circuit board, and the circuit board is provided with differential signal routing lines including a first differential signal routing line and a second differential signal routing line that are disposed at different layers of the circuit board.

Abstract: A wiring circuit board assembly sheet includes a support sheet having two end edges parallel with each other and a plurality of wiring circuit boards disposed at spaced intervals to each other in the support sheet. The wiring circuit board includes a metal-based portion having a generally rectangular frame shape. The metal-based portion includes a first piece along a first direction perpendicular to a thickness direction of the support sheet, and a second piece along a second direction perpendicular to the thickness direction and the first direction. Both the first piece and the second piece are inclined with respect to the end edge of the support sheet.

Abstract: In a silicon nitride substrate including a silicon nitride sintered body including silicon nitride crystal grains and a grain boundary phase, a plate thickness of the silicon nitride substrate is 0.4 mm or les, and a percentage of a number of the silicon nitride crystal grains including dislocation defect portions inside the silicon nitride crystal grains in a 50 ?m×50 ?m observation region of any cross section or surface of the silicon nitride sintered body is not less than 0% and not more than 20%. Etching resistance can be increased when forming the circuit board.

Abstract: An electronic component includes a capacitor component including a body and an external electrode disposed outside the body; a metal frame connected to the external electrode; and an encapsulant at least partially covering regions of the capacitor component and the metal frame. The metal frame may include a surface unevenness portion disposed on at least a portion of an interface with the encapsulant.

Abstract: An electronic device includes a first conductive layer including a first metal mesh including a first metal line segment, a second metal line segment and a first compensating line segment. The first metal line segment extends along a first direction and has a first end, and the second metal line segment extends along the first direction and has a second end, wherein a first breakpoint exists between the first end and the second end. The first compensating line segment is separated from and electrically insulated from the first metal line segment and the second metal line segment, the first compensating line segment does not completely overlap the first breakpoint, and a minimum distance between the first breakpoint and each first segment end of the first compensating line segment is less than or equal to 50 ?m.

Abstract: Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.

Abstract: According to one embodiment, a metal base circuit board includes a metal base substrate, a first circuit pattern, and a first insulating layer between the metal base substrate and the first circuit pattern. The first insulating layer covers a lower surface of the first circuit pattern and at least part of a side surface of the first circuit pattern, the lower surface facing the metal base substrate, the at least part of the side surface being adjacent to the lower surface.

Abstract: An optical integration device includes a first circuit layer comprising a first surface adjacent a first diffractive layer, the first diffractive layer arranged on a side of the first circuit layer along a first direction, and a first connecting pad electrically connected with the first circuit layer through a first conductive member. The optical integration device includes a side surface extending along the first direction. The side surface defines a first concavity extending through the first diffractive layer along the first direction. The first connecting pad includes a first mounting member connected with the side surface, and a first convex member extending from the first mounting member and received in the first concavity. The first conductive member includes a first conductive part arranged between the side surface and the first mounting member, and a second conductive part arranged between the first surface and the first convex member.

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

Abstract: In an aspect, a composition comprises a plurality of magnetic particles. The magnetic particles each independently comprise a nickel ferrite core having the formula Ni1?xMxPe2+yO4, wherein M is at least one of Zn, Mg, Co, Cu, Al, Mn, or Cr; x is 0 to 0.95, and y=?0.5 to 0.5; and an iron nickel shell at least partially surrounding the core, wherein the iron nickel shell comprises iron, nickel, and optionally M. In another aspect, a method of forming the magnetic particles comprises heat treating a plurality of nickel ferrite particles in a hydrogen atmosphere to form the plurality of magnetic particles having the iron nickel shell on the nickel ferrite core. In yet another aspect, a composite can comprise the magnetic particles and a polymer.

Abstract: A capacity touch fabric sensor (10) comprising a fabric layer (30) and layer (20) of a highly resistive material coating, the resistive coating layer (20) coating the fabric layer (30), wherein the fabric sensor (10) further comprises a plurality of electrodes (40) superimposed to the fabric layer (30), the plurality of electrodes (40) being electrically coupled with the first layer (20) of resistive material coating, each electrode (40) being electrically connected to an electronic control unit (450), the electronic control unit (450) being configured to evaluate the capacitance variation of the resistive layer that is indicative of a touch event on the capacity touch fabric sensor (10). [FIG.

Abstract: A method of manufacturing a glass article comprises: (A) forming a first layer of catalyst metal on a glass substrate; (B) heating the glass substrate; (C) forming a second layer of an alloy of a first metal and a second metal on the first layer; (D) heating the glass substrate, thereby forming a glass article comprising: (i) the glass substrate; (ii) an oxide of the first metal covalently bonded thereto; and (iii) a metallic region bonded to the oxide, the metallic region comprising the catalyst, first, and second metals. In embodiments, the method further comprises (E) forming a third layer of a primary metal on the metallic region; and (F) heating the glass article thereby forming the glass article comprising: (i) the oxide of the first metal covalently bonded the glass substrate; and (ii) a new metallic region bonded to the oxide comprising the catalyst, first, second, and primary metals.

Abstract: An electronic device including a first component carrier, a second component carrier connected with the first component carrier so that a thermal decoupling gap is formed between the first component carrier and the second component carrier, a first component on and/or in the second component carrier, and a second component having a first main surface mounted in the thermal decoupling gap so that at least part of an opposing second main surface and an entire sidewall of the second component is exposed with respect to material of the first component carrier and with respect to material of the second component carrier.

Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

Abstract: An electronic component-embedded substrate includes a wiring structure including a plurality of insulating layers and a plurality of wiring layers and having a cavity penetrating through at least one of the plurality of insulating layers, a first electronic component disposed in the cavity, a dam structure disposed on the wiring structure and having a through-portion, a first insulating material disposed in at least a portion of each of the cavity and the through-portion, and covering at least a portion of each of the wiring structure and the first electronic component, and a first circuit layer disposed on the first insulating material.

Abstract: The semiconductor device includes an insulating circuit substrate mounted with a semiconductor element; an external terminal; a base including a support portion; an adhesive sheet; and a sealing portion covering the semiconductor element. The support portion has a first surface, a second surface on the side opposite to the first surface, and a first opening opened at the first surface and the second surface. The insulating circuit substrate is disposed in the first opening. The adhesive sheet is disposed on the second surface of the support portion and has a second opening in which the semiconductor element is disposed in plan view. The adhesive sheet is projected into the first opening in plan view and adhered to a circuit block. The external terminal is adhered on the adhesive sheet and has a connecting surface to which a bonding wire is connected.

Abstract: A disclosed apparatus may be a circuit board that includes (1) a first unique sublaminate that includes a plurality of ground layers and a plurality of signal layers, (2) a second unique sublaminate that includes a plurality of power layers and another plurality of signal layers, and (3) a symmetry axis that bisects the circuit board between the first unique sublaminate and the second unique sublaminate, wherein the first unique sublaminate and the second unique sublaminate are distinct from one another. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A stretchable wiring board that includes a stretchable substrate having a first main surface with a first region, a second region adjacent the first region, and a third region adjacent the second region; a first stretchable wiring line on the first main surface and extending over the first region; an insulating layer extending over the first region and the second region; and a second stretchable wiring line extending over the first region, the second region, and the third region. At a position in the first region where the total thickness of the first stretchable wiring line, the insulating layer, and the second stretchable wiring line is the largest, the thicknesses of the first stretchable wiring line, the insulating layer, and the second stretchable wiring line satisfy a predetermined relationship with the thickness of the second stretchable wiring line at a boundary between the second region and the third region.

Abstract: A wiring substrate includes a core layer, first conductor layers including a first inner conductor layer, a first outer conductor layer and a first intermediate conductor layer, second conductor layers including a second inner conductor layer, a second outer conductor layer and a second intermediate conductor layer, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, and the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer and includes a conductor pattern formed such that an upper surface of the conductor pattern has an edge portion forming an inclined portion inclined toward the core layer.

Abstract: A printed circuit board of a camera module according to various embodiments of the disclosure includes: a ground portion constructed on the printed circuit board; a conductive member which is disposed to cover the ground portion and includes a first opening at a location corresponding to the ground portion; and an adhesive layer which is interposed between the printed circuit board and the conductive member and includes a second opening at a location corresponding to the ground portion, wherein the conductive member may be electrically coupled to the ground portion through a solder constructed on the first opening and the second opening. Other embodiments are also possible.

Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Abstract: A method of manufacturing a base plate includes the following steps: providing a first substrate, the first substrate including a first base layer, a first copper coating and a second copper coating covered on two sides of the first base layer; opening at least one first hole on the first substrate, the first hole penetrating the first base layer and the first copper; forming a first electroplated coating on the first copper coating, the first copper coating filling the first hole to form a first connecting portion; opening at least one second hole on the first connecting portion and the first electroplated coating to form a plurality of second connecting pins.

Abstract: A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.

Abstract: An electronic element mounting substrate includes a first substrate that has a first main surface, has a rectangular shape, and has a mounting portion for an electronic element on the first main surface, and a second substrate that is located on a second main surface opposite to the first main surface, is made of a carbon material, has a rectangular shape, has a third main surface facing the second main surface and a fourth main surface opposite to the third main surface, in which the third main surface or the fourth main surface has heat conduction in a longitudinal direction greater than heat conduction in a direction perpendicular to the longitudinal direction, and that has a recessed portion on the fourth main surface.

Abstract: A multi-layer ceramic capacitor includes: a ceramic body including ceramic layers laminated along one axial direction, first and second internal electrodes alternately disposed between the ceramic layers, first and second end surfaces to which the first and second internal electrodes are respectively drawn, a first end margin that forms an interval between the first end surface and the second internal electrodes, and a second end margin that forms an interval between the second end surface and the first internal electrodes; and first and second external electrodes that respectively cover the first and second end surfaces and are respectively connected to the first and second internal electrodes, the multi-layer ceramic capacitor satisfying the following relationship: SE?S/400+300, where S (?m) represents an area of the ceramic body and SE (?m) represents a total area of the first and second internal electrodes in cross sections of the first and second end margins.

Abstract: An electronic component module includes an electronic component, a structure body, a through wiring, and an insulator. The structure body covers at least a portion of the electronic component and has conductivity. The through wiring extends through the structure body. The insulator is disposed at least between the through wiring and the structure body.

Abstract: An electronic device and oscillator structure are provided. The electronic device includes a printed circuit board, an oscillator configured to oscillate at a frequency corresponding to an operation clock of the electronic device, and a connection member disposed between the oscillator and the printed circuit board such that the oscillator is spaced apart from a surface of the printed circuit board to electrically connect the oscillator to the printed circuit board. The connection member includes a first pad part electrically connected to a terminal of the oscillator, a second pad part electrically connected to a pad of the printed circuit board, and at least one conductive pattern electrically connecting the first pad part and the second pad part.

Abstract: A device and method of utilizing conductive thread interconnect cores. Substrates using conductive thread interconnect cores are shown. Methods of creating a conductive thread interconnect core are shown.

Abstract: Provided is a liquid crystal phase shifting device including: a first substrate and a second substrate that are opposite to each other, wherein first protrusions is provided on a surface of the first substrate facing towards the second substrate, second protrusions is provided on a surface of the second substrate facing towards the first substrate, and the first protrusions and the second protrusions are alternately arranged; a microstrip line provided on the surface of the first substrate facing towards the second substrate, the microstrip line covering at least part of the first protrusions; first support pads provided between the first substrate and the second substrate; a ground electrode provided on the surface of the second substrate facing towards the first substrate, the ground electrode overlapping at least part of the second protrusions; and liquid crystal molecules provided between the microstrip line and the ground electrode.

Abstract: A electronic device includes an embedded ball land substrate and a semiconductor die. The embedded ball land substrate includes a top surface, a bottom surface opposite the top surface, and one or more side surfaces adjacent the top surface and the bottom surface. The embedded ball land substrate further includes a mold layer on the bottom surface, contact pads on the top surface, and ball lands embedded in the mold layer and electrically connected to the contact pads. The semiconductor die includes a first surface, a second surface opposite the first surface, one or more side surfaces adjacent the first surface and the second surface, and attachment structures along the second surface. The semiconductor die is operatively coupled to the contact pads via the attachment structures.

Abstract: A method for manufacturing a millimeter scale electromechanical device includes coupling a stainless steel ply to a polymer carrier ply, coating the stainless steel ply in a photo resist material, masking the photoresist material, exposing the photoresist material to cure a portion of the photoresist material, developing the photoresist material to remove uncured photoresist material from the stainless steel ply, chemically etching the stainless steel ply to remove a patterned portion of the stainless steel ply, dissolving the polymer carrier ply to release unwanted chips of the stainless steel ply, and adhering the patterned stainless steel ply to a flexible material ply to form a sub-laminate.

Abstract: Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.

Abstract: A transition structure for millimeter wave is provided. The transition structure includes a first layer signal element coupled to an end of a first transmission line and a plurality of first layer ground elements surrounding the end of the first transmission line equidistantly from the end of the first transmission line and disposed along two opposite sides of a strip body of the first transmission line equidistantly from the strip body of the first transmission line. The transition structure further includes an intermediate layer signal element coupled to the first layer signal element and a plurality of intermediate layer ground elements surrounding the intermediate layer signal element quasi-coaxially. A multilayer transition structure including a multilayer structure and the transition structure is also provided. Therefore, the problem of operating frequency caused by the thickness of the multilayer structure can be overcome, thereby increasing the resonance frequency of the multilayer structure.

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Abstract: A film of the present invention contains a polypeptide derived from spider silk proteins. The decomposition temperature of the film is 240 to 260° C. The film absorbs ultraviolet light having a wavelength of 200 to 300 nm and has a light transmittance of 85% or more at a wavelength of 400 to 780 nm. The film is transparent and colorless in a visible light region. A method for producing a film of the present invention includes: dissolving a polypeptide derived from spider silk proteins in a dimethyl sulfoxide solvent to prepare a dope; and cast-molding the dope on a surface of a base. Thus, the present invention provides a spider silk protein film that can be formed easily and has favorable stretchability, and a method for producing the same.