Abstract: The stiffening brace may include a set of borders dimensioned to substantially surround an integrated circuit, wherein each border includes (1) a portion of material that is positioned atop a perimeter of the integrated circuit and (2) an additional portion of material that extends beyond the perimeter of the integrated circuit such that the additional portion of material overhangs a circuit board to which the integrated circuit is soldered. Various other apparatuses, systems, and methods are also disclosed.

Abstract: In a non-reciprocal circuit element, a permanent magnet is connected to one main surface of a magnetic plate, and a circuit board is connected to the other main surface of the magnetic plate, with a solder bump lying between the circuit board and the other main surface. The permanent magnet can control the transmission of electrical signal from each of a plurality of signal conductors of circuit board to a corresponding one of a plurality of input/output terminals of the magnetic plate. The non-reciprocal circuit element further includes an underfill material arranged between the magnetic plate and the circuit board. The magnetic plate has a through hole formed therein, the through hole extending from one main surface to the other main surface. The through hole has an empty space in which at least a part of a conductive film arranged in the through hole is exposed.

Abstract: An electronic component embedded substrate includes first insulating layer having a first through portion; a first electronic component disposed in the first through portion; a second insulating layer disposed on the first insulating layer and having a second through portion; a second electronic component disposed in the second through portion; and an insulating material covering at least a portion of each of the first electronic component and the second electronic component. The first through portion and the second through portion intersect, such that a portion of the first through portion and a portion of the second through portion overlap each other, on a plane.

Abstract: A component carrier is provided, which includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component on the stack; and stress propagation suppressing particles in at least part of the stack suppressing propagation of stress through the component carrier.

Abstract: A method of manufacturing a constituent for a component carrier is disclosed. The method includes providing an electrically conductive structure, forming a highly thermally conductive and electrically insulating or semiconductive structure on the electrically conductive structure, and subsequently, attaching a thermally conductive and electrically insulating structure, having a lower thermal conductivity than the highly thermally conductive and electrically insulating or semiconductive structure, on an exposed surface of the highly thermally conductive and electrically insulating or semiconductive structure.

Abstract: The present invention provides a surface treated copper foil in which a dropping of the roughening particles from a roughening treatment layer on the surface of the copper foil is suppressed and an occurrence of wrinkles or stripes when bonding with an insulating substrate is suppressed. The surface of the roughening treatment layer satisfies one or more of the following: a roughness Ra is 0.08 to 0.20 ?m, a roughness Rz is 1.00 to 2.00 ?m, a roughness Sq is 0.16 to 0.30 ?m, a roughness Ssk is ?0.6 to ?0.35, a roughness Sa is 0.12 to 0.23 ?m, a roughness Sz is 2.20 to 3.50 ?m, a roughness Sku is 3.75 to 4.50, and a roughness Spk is 0.13 to 0.27 ?m, a glossiness of a TD of the surface of the side of the roughening treatment layer of the surface treated copper foil is 70% or less.

Abstract: A printed circuit board is provided. The printed circuit board includes N power layers and a first via group. The N power layers are arranged in parallel and spaced from each other. The first via group includes M rows of vias which are disposed through the N power layers, where N and M are positive integers greater than 0. Each row of the M rows of vias is electrically connected to the first layer of the N power layers. A Pth row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively, where Q is a smallest positive integer greater than or equal to P((N?1)/M), and P is a positive integer less than or equal to M.

Abstract: An electronic assembly and a method of forming an electronic assembly. The electronic assembly including a printed circuit board including a perimeter; a compression gasket extending around at least a portion of the perimeter of the printed circuit board; and a housing including a first wall and a housing side wall extending from the first wall, the first wall and housing side wall form a cavity, wherein the printed circuit board and the compression gasket are located within the cavity with the compression gasket positioned between the perimeter and the housing side wall.

Abstract: An article includes a wafer having a body which defines a first surface and a second surface. The wafer defines a via having a via surface extending between the first and second surfaces through the body. An adhesion layer is positioned on the via surface. At least a portion of the via surface is free of the adhesion layer. A metallic component is positioned within the via and extends from the first surface to the second surface.

Abstract: There is provided a method for manufacturing an electrical wire. The electrical wire includes a rod-like conductor having a shape corresponding to a predetermined wiring route and also having rigidity to enable the rod-like conductor to maintain the shape, and an insulation sheath covering the rod-like conductor. The method includes: preparing a plurality of rod-like preliminary conductors having the rigidity so as to correspond to a plurality of sub routes into which the wiring route is divided; processing at least one of the plurality of preliminary conductors into a shape conforming to the corresponding sub routes; connecting the plurality of preliminary conductors together to form the rod-like conductor; and forming the insulation sheath to cover the rod-like conductor.

Abstract: An electronic component includes a multilayer capacitor, including a capacitor body, and a pair of external electrodes disposed on both ends of the capacitor body, respectively, and an interposer, including an interposer body, and a pair of external terminals disposed on both ends of the interposer body, respectively. The external terminals include bonding portions, mounting portions, and connection portions disposed to connect the bonding portions and the mounting portions to each other. Adhesives are provided between the external electrodes and the bonding portion. A height at which the adhesives fall along the connection portions of the external terminals is defined as t and a height of the interposer is defined as T, t/T satisfies 0.04?t/T?0.80.

Abstract: The application provides a printed circuit board and an optical module so as to alleviate poor contact between the electro-conductive contact sheet group and the clamping piece due to the solder resist. The printed circuit board includes a substrate, and electro-conductive contact sheet group positioned on the surface of the substrate, where a part of the substrate is overlaid with solder resist, and there is a gap between the solder resist and the electro-conductive contact sheet group.

Abstract: A display substrate includes a substrate, a plurality of electrode leads disposed on the substrate, and a plurality of electrodes electrically disconnected with each other disposed on the substrate. Each electrode is in direct contact with one or more of the plurality of electrode leads, and a thickness of each electrode lead is greater than a thickness of a corresponding electrode. At least one of the plurality of electrode leads is respectively provided with at least one gap, and each gap is configured to electrically disconnect one of the plurality of electrodes that is in direct contact with a corresponding electrode lead from another one of the plurality of electrodes that is adjacent to the corresponding electrode lead.

Abstract: A method for manufacturing a housing is described. The methods includes: providing a cover body defining a slot; filling a first material into the slot; and filling a second material into the slot to fill up the slot. A housing and a mobile terminal including the housing are further provided.

Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.

Abstract: A multilayer substrate includes a lamination body including a first resin substrate, a second resin substrate, and a bonding layer that are hot-pressed. A first conductor pattern including a surface defined by a plated film is disposed on a first surface of the first resin substrate. A second conductor pattern including a surface defined by a plated film is disposed on a second surface of the first resin substrate. A third conductor pattern including a surface defined by a plated film is disposed on a third surface of the second resin substrate. A fourth conductor pattern including a surface defined by a plated film is disposed on a fourth surface of the second resin substrate. The first conductor pattern is located closer to one outermost layer than the second conductor pattern is. The second conductor pattern is thinner than the first conductor pattern.

Abstract: A method for manufacturing of a hybrid component carrier includes providing a first layer structure having at least one electrically insulating layer and at least one electrically conductive layer and forming a second layer structure on the first layer structure wherein the second layer structure has at least a first layer and a second layer. The first layer structure has a first density of electrically conductive elements. The second layer structure has a second density of electrically conductive elements. The second density of electrically conductive elements is greater than the first density of electrically conductive elements. The forming of the second layer structure on the first layer structure includes forming the first layer of the second layer structure on the first layer structure and subsequently forming the second layer of the second layer structure on the first layer of the second layer structure.

Abstract: An article includes a wafer having a body which defines a first surface and a second surface. The wafer defines a via having a via surface extending between the first and second surfaces through the body. An adhesion layer is positioned on the via surface. At least a portion of the via surface is free of the adhesion layer. A metallic component is positioned within the via and extends from the first surface to the second surface.

Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.

Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.

Abstract: A circuit board structure includes a first core layer, a first build-up layer and a second build-up layer. The first core layer has a first surface and a second surface opposite to the first surface, wherein the first core layer includes a core dielectric material layer and at least one patterned conductive plate embedded within the core dielectric material layer, the core dielectric material layer includes a first sub-dielectric material and a second sub-dielectric material, and at least one interface exists in between the first sub-dielectric material and the second sub-dielectric material. The first build-up layer is disposed on the first surface of the first core layer, and the second build-up layer is disposed on the second surface of the first core layer.

Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.

Abstract: An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.

Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.

Abstract: A through electrode substrate includes a substrate having a through hole extending through between a first face and a second face, a diameter of the through hole not having a minimum value inside the through hole; and a conductor arranged inside the through hole, wherein the through hole has a shape having a value obtained by summing a first to an eighth inclination angle at a first to an eighth position, respectively, of an inner face of the through hole of 8.0° or more, each of the first to the eighth inclination angle is an angle of the inner face with respect to a center axis of the through hole, and the first to the eighth position correspond to positions at distances of 6.25%, 18.75%, 31.25%, 43.75%, 56.25%, 68.75%, 81.25%, and 93.75%, respectively, from the first face in a section from the first face to the second face.

Abstract: A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.

Abstract: A printed circuit board structure and a wiring method therefor are disclosed. The printed circuit board structure comprises a first wiring channel formed inside the printed circuit board for transmitting a circuit signal; a pin, connected to the first wiring channel for connecting a chip to the printed circuit board; the pin comprising an unused pin and a used pin, the used pin comprising a peripheral pin and an internal pin; wherein the printed circuit board further comprises a second wiring channel, the second wiring channel leads out the internal pin by means of covering at least a portion of the unused pin. By means of using a printed circuit board structure and a wiring method to configure pins of the printed circuit board, the number of printed circuit board layers is reduced, and the current carrying capacity is enhanced.

Abstract: A component carrier includes a plurality of low density layer structures, and a plurality of high density layer structures having a higher density of electrically conductive structures than the plurality of low density layer structures, where the low density layer structures and the high density layer structures are alternatingly vertically stacked.

Abstract: A circuit module (100) includes an electronic component (30), a plurality of conductor posts (40), a mold layer (50) that seals a plurality of the electronic components (30) and the plurality of conductor posts (40), and a shield layer (60) on the mold layer (50). The electronic components (30) include a first electronic component (31) and second electronic components (32, 36). The plurality of conductor posts (40) includes a group of conductor posts (400) traversing between the first electronic component (31) and the second electronic components (32, 36). The shield layer (60) includes a slit (600) that, with respect to each conductor post (40) included in the group (400) of conductor posts, in a plan view, passes and extends between the conductor post (40) and the first electronic component (31), or between the conductor post (40) and the second electronic components (32, 36).

Abstract: A hearing aid circuit includes a plurality of sub-circuits implemented as a plurality of flexible circuit boards. In various embodiments, the plurality of flexible circuit boards includes a motherboard that can be used with multiple hearing aid models and different peripheral boards that can provide different hearing aid models with their unique styles and/or functional features. In various embodiments, the hearing aid circuit is assembled in an automated process that connects the motherboard to one or more peripheral circuit boards using surface mount technology (SMT).

Abstract: An electronic device includes a printed circuit board (PCB) defining a cavity, a first component pad of the PCB positioned outside the cavity, and a second component pad of the PCB positioned on a bottom surface of the cavity. The first component pad has a first thickness, and the second component pad has a second thickness that is less than the first thickness of the first component pad. An electronic component, such as a surface mounted technology (SMT) component, is mounted to the second component pad within the cavity.

Abstract: A multi-layer circuit board comprising a carrier plate with an upper surface and a lower surface, and at least one electrically conductive upper inner layer located on the upper surface of the carrier plate and an electrically insulating upper intermediate layer located thereon, and an electrically conductive upper outer layer located thereon, forming the outermost layer of the upper surface. At least one electrically conductive lower inner layer is located on the lower surface of the carrier plate and an electrically insulating lower intermediate layer located thereon, and an electrically conductive lower outer layer located thereon, forming the outermost layer of the lower surface. The upper and/or lower outer layers are populated with components, and conductor paths in one of the inner layers are oriented in different directions from conductor paths in the other inner layer, and the region between the conductor paths is flooded with a voltage.

Abstract: The disclosure relates to an electronic unit with a circuit board having at least one component arranged on a main surface of the circuit board and a casing element, which incorporates the at least one component, as well as with an ESD protection arrangement for the circuit board. According to the disclosure, open areas on the circuit board, which are not covered by the casing element, are covered with a gold layer directly mounted on a copper surface of the circuit board.

Abstract: The present invention relates to a ceramic substrate (100) comprising: a front side (100-1), which comprises: i) a power semiconductor (102-1, . . . , 102-n); and ii) a first metallic layer (104) comprising at least one first metallic plane contact (104-1, . . . , 104-n), which is configured to connect the power semiconductor (102-1, . . . , 102-n) to a first terminal (105-1, . . . , 105-n) on an edge (100-3) of the ceramic substrate (100); a back side (100-2), which comprises: i) a capacitor (103) which is attached to a ii) second metallic layer (108) comprising at least one second metallic plane contact (108-1, . . . , 108-n), which is configured to connect the capacitor (103) to a second terminal (107-1, . . . , 107-n) on the edge (100-3) of the ceramic substrate (100); and a metallic frame (110), which is configured to connect the first metallic layer (104) to the second metallic layer (108).

Abstract: Embodiments relate to the fabrication of an interposer with nanofibers by an additive process to electrically connect two or more electronic components. The nanofibers are grown on a substrate away from a surface of the substrate. The nanofibers are plated with a conductive material such that the nanofibers are encompassed in a column of the conductive material. An insulative material fills at least the volume between the columns of conductive material. The substrate and the interposer is the remaining device. The interposer can be combined with a redistribution layer to connect electronic components of dissimilar pitch.

Abstract: A circuit board is provided that includes a plurality of insulating layers provided in a stack to have a first surface and a second surface. A via may extend from the first surface of the stack to the second surface of the stack. A passive device may be provided in the via.

Abstract: A power consuming electronics device that dissipates internal device heat via a heat sink is disclosed. The power consuming electronics device includes first and second complementary housing parts. The first housing part includes a first surface ending at a first peripheral edge, and the second housing part including a second surface ending at a second peripheral edge. The power consuming electronics device also includes a heat sink having an air exposed surface that is interposed between the first and second peripheral edges. Surface edges of the air exposed surface abut the first and second peripheral edges of the housing parts and are respectively matched therewith in shape and dimension so that an overall composite surface formed by the first and second surfaces of the housing parts and the air exposed surface of the heat sink is substantially continuous and uniform.

Abstract: An electronic device includes a first wiring substrate having a first corner part, a first ground pattern formed on a lower surface of the first wiring substrate with avoiding the first corner part, a second ground pattern formed on an upper surface of the first wiring substrate with avoiding the first corner part, a second wiring substrate provided above the first wiring substrate and including a second corner part above the first corner part, a third ground pattern formed on a lower surface of the second wiring substrate with avoiding the second corner part, a fourth ground pattern formed on an upper surface of the second wiring substrate with avoiding the second corner part, a plurality of terminals electrically connected to each of the first, second, third and fourth ground patterns, and an antenna fixed to the upper surface of the second wiring substrate at the second corner part.

Abstract: A method for manufacturing a flexible printed circuit board, comprising: providing a flexible printed circuit substrate; defining first through holes and second through holes through the flexible printed circuit substrate; and forming first conductive pillars and second conductive pillars; and defining first grooves by removing a portion of each first conductive pillar and defining second grooves by removing a portion of each second conductive pillar; the first grooves and the second grooves are defined from an outer surface of the flexible printed circuit board on the second conductive pattern layer side to a surface of the second conductive pattern layer away from the first conductive pattern layer; each of the first grooves is aligned with and corresponds to one first conductive pillar, and each of the second grooves is aligned with and corresponds to one second conductive pillar.

Abstract: An intermediate printed board has a plurality of unit regions that are to be cut out and separated to become a plurality of individual printed circuit boards, respectively. The intermediate printed board includes a metal core substrate including: a metal layer; and a plating layer formed on each of a top surface and a bottom surface of the metal layer, the plating layer being absent in each of cutting regions, the cutting regions being regions on the intermediate printed board where the plurality of unit regions are separated so as to produce the plurality of individual printed circuit boards; an insulating layer formed so as to cover a surface of the metal core substrate; and a conductive pattern formed on the insulating layer.

Abstract: The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace segments that deviate the signal trace away from the source of the routing restriction.

Abstract: A circuit board pad resonance control system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. A first connector pad receives the signal transmission line adjacent a first end of that connector pad. The first connector pad includes a mounting surface that mounts directly to a coupling element that is configured to couple a subsystem to the board, and reduces a resonance that is produced by an open portion of a signal transmission path that is created when the coupling element is directly mounted to the mounting surface of the first connector pad in a first orientation. In a specific example, the mounting surface may include a plurality of protrusions, a plated surface, and/or a mask that reduces the conductivity of the connector pad which reduces signal integrity issues due to resonance.

Abstract: A printed circuit board (PCB) includes a dielectric plane and a ground plane parallel to and spaced apart from the dielectric plane. The dielectric plane includes a pair of signal traces and a 3-dimensional (3D) grounded (GND) fence located between the pair of signal traces. The 3D GND fence is electrically connected to the ground plane, and protrudes perpendicularly from the dielectric plane. The 3D GND fence is located equidistant from each of the pair of signal traces, and the 3D GND fence is configured to block electromagnetic interference (EMI) from a first of the pair of signal traces to a second of the pair of the signal traces. The pair of signal traces is configured to form part of a noise-sensitive electronic circuit. The 3D GND fence may have a rectangular configuration.

Abstract: A printed circuit board including: an insulating material; a metal layer stacked on a surface of the insulating material; and a via hole passing through the metal layer and the insulating material. The metal layer decreases in thickness in a region adjacent to the via hole, and an interface between the insulating material and the metal layer includes a region that is directed toward the via hole.

Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

Abstract: A method of manufacturing a multilayer substrate includes preparing a plurality of substrates, stacking the substrates with bonding sheets interposed, and a first bonding process of bonding the substrates to each other by partially heating the stacked substrates by a heater and partially melting the bonding sheet. Each of the substrates is provided with a through-hole and a metal film covering an inner peripheral surface of the through-hole. In the first bonding process, the metal film is heated by the heater and heat is transferred from the heater to the bonding sheet via the metal film.

Abstract: Apparatus, comprising fabric (62) formed from fibers (74); and an electrical component (20) having first and second perpendicular fiber guiding structures, wherein a first of the fibers is soldered in the first fiber guiding structure and a second of the fibers is soldered in the second fiber guiding structure.

Abstract: There is provided a semiconductor-bonding resin composition having excellent thermally conductive property and electrically conductive property and suitable for joining a power semiconductor element and an element support member. There are provided: a semiconductor-bonding resin composition containing (A) a bismaleimide resin including an aliphatic hydrocarbon group on a main chain, (B) a curing agent, (C) a filler containing electrically conductive particles having a specific gravity of 1.1 to 5.0, and (D) silver microparticles having an average particle size of 10 to 300 nm; a semiconductor-bonding sheet obtained using the semiconductor-bonding resin composition; and a semiconductor device including a semiconductor joined by the semiconductor-bonding sheet.

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive via structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer over a second surface of the first substrate. The method includes forming a first insulating layer over the barrier layer. The method includes forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad continuously extends from the conductive via structure into the third opening. The method includes forming a conductive bump over the conductive pad in the third opening.

Abstract: A multilayer wiring board having a high degree of freedom of wiring design and realizing high-density wiring, and a method to simply manufacture the multilayer wiring board is provided. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically connected to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 ?m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.