Abstract: Embodiments of the present disclosure provide methods, apparatuses, devices and systems related to the implementation of a multi-layer printed circuit board (PCB) radio-frequency antenna featuring, a printed radiating element coupled to an absorbing element embedded in the PCB. The embedded element is configured within the PCB layers to prevent out-of-phase reflections to the bore-sight direction.

Abstract: An electronic component mounting board includes a substrate and a metal layer. The substrate includes a first layer, and a second layer located at a lower surface of the first layer. The metal layer is located between the first layer and the second layer, and includes a first conductor layer, and a second conductor layer located with a space from the first conductor layer. The space extends from a first end of the metal layer to a second end of the metal layer different from the first end as viewed from above. The metal layer overlaps a first imaginary line that is parallel to one side of the substrate and passes through a center of the substrate, and a second imaginary line that is perpendicular to the first imaginary line and passes through the center of the substrate as viewed from above.

Abstract: A printed wiring board includes a multilayer body, a first wiring layer formed on first surface of the body and including first pads, a second wiring layer embedded into second surface of the body and including second and third pads, conductor posts formed on the third pads, and via conductors formed in the body and having diameter reducing toward the second surface of the body. Each third pad has metal foil formed thereon such that each post is formed on the foil, the second wiring layer is formed such that the second pads are positioned to connect an electronic component in central portion of the second surface of the body and the third pads are positioned to connect another board in outer edge portion of the second surface of the body, and the second pads are formed such that each second pad has exposed surface recessed from the second surface.

Abstract: A printed circuit board (PCB) reducing a thickness of a semiconductor package and improving reliability of the semiconductor package, a semiconductor package including the PCB, and a method of manufacturing the PCB may be provided. The PCB may include a substrate base having at least one base layer, and a plurality of wiring layers disposed on a top surface and a bottom surface of the at least one base layer, the plurality of wiring layers defining a plurality of wiring patterns, respectively may be provided. An elastic modulus of a conductive material of one wiring pattern of at least one wiring layer from among the plurality of wiring layers may be less than a conductive material of another wiring pattern.

Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

Abstract: The present invention offers a device requiring a reduced number of manufacturing processes and providing high electrical reliability, and a method for manufacturing the device. The method for manufacturing the device forms through holes in a substrate, fills the through holes with a conductive material through electroplating from a first surface side of the substrate, polishes the conductive material to form through wirings, and forms an element portion on the first surface side. Then, the method processes the substrate so that the positions of the end faces of the through wirings measured from the substrate surface on the first surface side are made smaller in depth than the positions of the end faces of the through wirings measured from the substrate surface on the second surface side.

Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.

Abstract: A wireless power transmitting device transmits wireless power signals to a wireless power receiving device. The wireless power receiving device has a rectifier and a wireless power receiving coil that receives wireless power signals. The wireless power transmitting device uses a layer of coils to transmit the wireless power signals. A dielectric layer in the wireless power transmitting device defines a charging surface that receives the wireless power receiving device. A layer of temperature sensors is interposed between the layer of coils and the dielectric layer. Control circuitry in the wireless power transmitting device uses temperature information from the temperature sensors to determine whether a foreign object such as a coin is present on the charging surface.

Abstract: A method for manufacturing an electromechanical structure includes producing conductors and/or graphics on a substantially flat film, attaching electronic elements on the film in relation to a desired three-dimensional shape of the film, forming the film into the substantially three-dimensional shape, and using the substantially three-dimensional film as an insert in an injection molding process by molding substantially on said film.

Abstract: A sensor device may detect pressure. The sensor device may comprise: an elastic dielectric; a first wiring formed on one surface of the elastic dielectric; a second wiring formed on another surface of the elastic dielectric facing the surface on which the first wiring is formed; and a flexible printed circuit board, which is connected to the first wiring and the second wiring, for receiving signals transferred from the first wiring and the second wiring.

Abstract: A component carrier is provided, which includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component on the stack; and stress propagation suppressing particles in at least part of the stack suppressing propagation of stress through the component carrier.

Abstract: An electronic assembly includes a substrate film for accommodating electronics, an electrical contact pad coupled to the substrate film, an electrically conductive member coupled to the electrical contact pad, and a material layer molded onto the substrate film to embed the elastic electrically conductive member.

Abstract: A flexible display panel includes a flexible substrate including a first region configured to receive a first stress and a second region configured to receive a second stress less than the first stress. The second region is located in a first direction from the first region. The flexible substrate further includes a conductive layer including a columnar conductive portion and a polycrystalline conductive portion. The columnar conductive portion is disposed on the first region of the flexible substrate and includes conductive columns, and the polycrystalline conductive portion is disposed on the second region of the flexible substrate and includes polycrystalline particles.

Abstract: A preformed lead frame device includes multiple spaced-apart longitudinal sections, multiple spaced-apart transverse sections intersecting the longitudinal sections, and multiple preformed lead frame units each surrounded by two adjacent ones of the longitudinal sections and two adjacent ones of the transverse sections. Each of the preformed lead frame units includes a die pad sub-unit including a die pad portion, multiple pillar portions, and a first gap formed among the die pad portion and the pillar portions, a lead sub-unit including leads and a second gap formed among the die pad sub-unit and the leads, an adhesion-strengthening layer disposed in the first and second gaps, and a molding layer filling the first and second gaps to cover the adhesion-strengthening layer.

Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

Abstract: A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

Abstract: A wiring board includes a first insulating layer including a surface having unevenness, a second insulating layer including a surface having unevenness, laminated on the first insulating layer, and made of the same insulating material as that of the first insulating layer, insulating particles contained in the first and second insulating layers at rate of 40 to 80 wt %, a first wiring conductor on a first underlying metal layer surface, and a second wiring conductor on a second underlying metal layer surface. A second level difference of the unevenness in a surface region of the second insulating layer under the second wiring conductor is smaller than a first level difference of the unevenness in a surface region of the first insulating layer under the first wiring conductor, and the second level difference is not more than ? of an average particle size of the insulating particles.

Abstract: A coil electronic component includes a base layer, a stacked structure of a plurality of coil patterns disposed on the base layer, and a buildup layer disposed between at least two coil patterns of the plurality of coil patterns, the buildup layer at least partially covering the coil patterns and having sintering properties different from those of the base layer.

Abstract: A substrate-with-support includes: a substrate having a wiring area, an outer peripheral area provided on an outer peripheral side of the wiring area, and a plurality of support joint portions being provided on the outer peripheral area; and a support made of metal having an outer frame portion arranged to face the outer peripheral area and to expose the wiring area, and a plurality of protruding portions being provided on the outer frame portion, wherein the support joint portions and the protruding portions are joined to each other.

Abstract: Apparatuses and methods associated with an antenna formed on a transparent substrate are disclosed herein. In embodiments, an electronic device may include a substrate, wherein at least a first region of a plurality of regions of the substrate is transparent; and a plurality of layers formed on the substrate, the plurality of layers including: a first transparent layer formed over the first region; and a second metal layer formed over a second region of the plurality of regions of the substrate, wherein the second metal layer comprises an antenna. Other embodiments may be disclosed or claimed.

Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

Abstract: An electronic component mounting board reduces short-circuiting between a plurality of thick wiring conductors to improve reliability and electrical characteristics. An electronic component mounting board (1) includes a substrate (2) including a mount area (4) in which an electronic component (10) is mountable, a first insulating layer (2a) overlapping the mount area (4), a second insulating layer (2b) on a lower surface of the first insulating layer (2a), and a first metal layer (5) between the first insulating layer (2a) and the second insulating layer (2b).

Abstract: An electronic component includes a first module, a second module and a third module between the first module and the second module. Each of the first module and the second module includes a plurality of conductive pads thereon. A connecting part includes a plate body and a plurality of first tails and a plurality of second tails respectively extending on two opposite sides of the plate body wherein the first tails are soldered upon the first conductive pads and the second tails are soldered upon the second conductive pads, respectively. Each of the first tails and the second tails includes a mounting pad with a through hole therein, and a folded section on the end edge with a solder unit received with a space formed in the folded section and communicatively above the corresponding through hole.

Abstract: A housing for an electric component and a method for producing a housing for an electric component are disclosed. In an embodiment the housing includes a first housing part and a second housing part, wherein the first housing part is connected to the second housing part in a joining region, and wherein the joining region is at least partially covered by a coating containing sprayed-on particles.

Abstract: An enclosure for a portable computing device can include a cover glass affixed to an enclosure without trim pieces disposed between the cover glass and the disclosure. In one embodiment, the enclosure can include an edge profile that can define a relatively large contact pad about the enclosure. The contact pad can distribute impact forces over a relatively large area and thereby protect the cover glass integrity.

Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.

Abstract: Electrically conductive patterns formed on a substrate are provided with a reduced visibility. A region of a major surface of the substrate is selectively roughened to form a roughened pattern on the major surface of the substrate. Electrically conductive traces are directly formed on the roughened region and are conformal with the roughened pattern on the major surface of the substrate.

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.

Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

Abstract: A touch sensor film preventing moire occurring in accordance with deformation of a support is manufactured by performing roll transportation of an elongated transparent support 1 having a thickness smaller than 80 ?m using a plurality of pass rollers 4, 5, and 6; performing annealing treatment with respect to the support 1 at a temperature which is equal to or lower than a temperature obtained by adding 35° C. to a dynamic glass transition temperature of the support 1; and forming a mesh pattern formed of thin metal wires 8a on a surface of the support 1 subjected to the annealing treatment.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.

Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Abstract: Generally, the present disclosure provides example embodiments relating to a printed circuit board (PCB). In an embodiment, a structure includes a PCB including insulating layers with respective metal layers being disposed therebetween. Each of first layers of the insulating layers includes a first fiberglass content. A second layer of the insulating layers has a second fiberglass content less than the first fiberglass content. For example, in some embodiments, the second insulating layer does not include a fiberglass matrix.

Abstract: A medium stores a program. The program causes a computer to: acquire relative area information which at least indicates a relative position of a reference area relative to a reference document and a relative size of the reference area relative to a size of the reference document; acquire target image data which indicates a target image including a document; identify a target area in the target image by use of the target image data, the target area being in the relative position, which is indicated by the relative area information, relative to the target image, the target area having the relative size, which is indicated by the relative area information, relative to the size of the target image; analyze an area, in the target image, including the target area; and output image data based on the target image data.

Abstract: An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower surface spaced from the upper surface along a vertical direction. The composite die pad can include an insulator die pad and a metal die pad. The insulator die pad and the metal die pad can be disposed adjacent one another along the vertical direction. The substrate can include a plurality of leads disposed about at least a portion of a perimeter of the composite die pad. An integrated device die can be mounted on the upper surface of the composite die pad.

Abstract: Provided are circuit board excellent in interlayer adhesion and solder heat resistance, and production method thereof. The circuit board is produced by a method including: preparing a plurality of at least one kind of thermoplastic liquid crystal polymer (TLCP) films, forming a conductor layer on one side or both sides of a film in at least one of the films to obtain a unit circuit board, laminating the films containing the unit circuit board to obtain a stacked material, conducting thermo-compression-bonding of the stacked material under pressurization to a first temperature giving an interlayer adhesion to integrate the stacked material, carrying out structure-controlling thermal treatment by heating the integrated stacked material at a second temperature which is lower than the first temperature and is lower than a melting point of a TLCP having a lowest melting point out of the plurality of TLCP films.

Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. A second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.

Abstract: Flexible antennas for harvesting electromagnetic energy are described. The flexible antenna may be a far field antenna and may comprise a flexible substrate, a first metal layer disposed on one side of the flexible substrate, and a second metal layer disposed on an opposite side of the flexible substrate. The first and second metal layers may be connected through one or more vias. The first metal layer may be sized to capture electromagnetic energy at a frequency in an ISM band.

Abstract: A flexure of a hard disk drive includes a metal base, and a conductive member formed on the metal base. The conductive member includes an insulating layer and a conductive layer. The insulating layer has a flat portion and an elevated portion projected from the flat portion. The conductive layer has a connecting terminal formed along the side surface.

Abstract: A flexible circuit board is disclosed. The flexible circuit board of the present invention comprises: a substrate part; and a transmission part formed to extend from the substrate part, and having two or more lines, which are aligned in parallel in a thickness direction, for transmitting a high frequency.

Abstract: A printed circuit board includes a power input terminal, a positive trunk line, a negative trunk line, a first switching circuit, a second switching circuit, a first positive wire, a second positive wire, a first capacitor, a second capacitor, and a bypass circuit. The first positive wire connecting the positive trunk line with the first switching circuit without passing through the second switching circuit. The second positive wire connecting the positive trunk line with the second switching circuit without passing through the first switching circuit. The first capacitor provided between the first positive wire and the negative trunk line. The second capacitor provided between the second positive wire and the negative trunk line. The bypass circuit connecting the first positive wire with the second positive wire.

Abstract: An optical module is provided in the present disclosure. According to an embodiment, the optical module may comprise a housing, two or more circuit board layers, and a light emitting chip. The two or more circuit board layers may be disposed in the housing and electrically connected to each other; and the light emitting chip may be electrically connected to at least one of the circuit board layers.

Abstract: A peristaltic pump includes a housing, an electric motor and a reduction gear contained in the housing, a head, and a printed circuit board. The reduction gear is configured to be driven by the electric motor. The head contains a tube having two accessible ends and a rotor provided with two or more squeezing elements configured to squeeze the tube. The head is configured to be removably coupled to the housing according to at least two different orientations with respect to the housing. The housing further contains one or more alignment plates for aligning the reduction gear. The alignment plates are coupled to the housing through a snap-fit connection means. The printed circuit board is contained within the housing, and is configured to control the peristaltic pump and to supply power to the electric motor. The printed circuit board being is coupled to the housing through snap-fit connection mean.

Abstract: An embodiment of the present invention provides a PCB module comprising: a multilayer PCB assembly including a heat dissipation plate layer, and an upper PCB and a lower PCB which are attached to the upper surface and the lower surface of the heat dissipation plate layer, respectively; and an upper case and a lower case for covering the upper side and the lower side of the multilayer PCB assembly, respectively, wherein the heat dissipation plate layer includes a plurality of electrically insulating heat dissipation plates arranged on the same plane, and at least one of the plurality of heat dissipation plates comprises: a first heat pole in thermal contact with an electronic circuit element mounted on the upper PCB or the lower PCB; and a second heat pole in thermal contact with the inner surface of at least one of the upper and lower cases.

Abstract: A printed circuit board (PCB) assembly may include a component capable of sending or receiving high-speed differential signal pairs, a package that is connected to the component, and a PCB connected to the package. The PCB assembly may be used to support a first high-speed differential signal pair that includes a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through the PCB assembly. A set of interconnects may be used to intelligently route the first differential signal pair within the package and/or within the PCB. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal and a second interconnect to route the second differential signal toward the particular differential signal.

Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Abstract: To provide a wiring substrate having excellent transmission characteristics, of which initial failure of a plating layer formed on an inner wall surface of a hole is suppressed regardless of the type of the pre-treatment applied to the inner wall surface of the hole, and of which the plating layer has favorable heat resistance, and a process for producing it.