Abstract: A bio-sensor circuit for detecting characteristics of a substance placed thereupon, the bio-sensor circuit has: a printed circuit having at least one electrically conductive contact sensor on a surface of the printed circuit, the electrically conductive contact sensor including a biochemical agent; and an electrically insulative coating affixed to the surface of the printed circuit, the electrically insulative coating having a well associated with the electrically conductive contact sensor, thereby leaving the electrically conductive contact sensor exposed through the electrically insulative coating, the electrically insulative coating being a resinous compound formed by injection molding. An electrochemical change resulting from the interaction of the substance to be characterized and the biochemical agent creates a detectable electrical potential at the electrically conductive contact sensor. A system and method of creating such a circuit via injection molding is also provided.

Abstract: The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.

Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.

Abstract: An optically transparent conductive material including an optically transparent support, sensor parts electrically connected to a terminal area via peripheral wiring parts, and dummy parts not electrically connected to the terminal areas, the sensor parts and the dummy parts being disposed on the optically transparent support, wherein the sensor parts and the dummy parts each have a metal thin wire net-like pattern formed by an assembly of multiple polygons, the metal thin wire pattern of each dummy part includes disconnection parts, and the metal thin wire pattern of each dummy part also includes a region satisfying the following requirement (1) and/or a region satisfying the following requirement (2): (1) each polygon sharing one or more vertices with a polygon having no disconnection part includes at least one disconnection part; and (2) each polygon sharing one or more vertices with at least one of two polygons sharing a side or a vertex and having no disconnection part includes at least one disconnection

Abstract: A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

Abstract: A method for manufacturing a carrier tape housing a plurality of electronic components with seal materials includes forming housing holes in tape-shaped main body with first and second principal surfaces along a longitudinal direction of the tape-shaped main body, the housing holes penetrating from the first principal surface to the second principal surface, affixing an adhesive layer of a tape-shaped seal material to the second principal surface of the tape-shaped main body to cover the housing holes, forming cuts in the tape-shaped seal material to separate portions defining and functioning as the seal materials including portions at least partially overlapping with the respective housing holes in a planar view from the other portions, and providing chip-shaped electronic component into each of the housing holes of the tape-shaped main body and fixing the electronic component to the adhesive layer of the seal material exposed in each of the housing holes.

Abstract: A method for producing a flexible printed circuit board according to an embodiment of the present invention includes a through-hole formation step of preparing a base material including a base film having insulating properties and flexibility and a pair of metal films stacked on both surface sides of the base film, and forming a through-hole in the metal film on a front surface side of the base material and the base film; a filling step of stacking, by electroplating on a front surface of the base material, stacking a conductive material on a surface of the metal film on the front surface side to form a conductive material layer and to fill the through-hole with the conductive material; and a removal step of removing, by etching the front surface of the base material, a surface layer of the conductive material layer stacked on the surface of the metal film on the front surface side and a surface layer of the conductive material filling the through-hole.

Abstract: A printed wiring board includes a substrate having first and second surfaces such that the substrate has a thickness in a range of 30 ?m to 100 ?m between the first and second surfaces, and through hole conductors including plating material such that the through hole conductors are formed in through holes extending from the first surface to the second surface. Each through hole has a first opening portion and a second opening portion connected to the first opening portion such that the first opening portion has a tapered shape decreasing in diameter from the first surface toward the second surface, the second opening portion has a tapered shape decreasing in diameter from the second surface toward the first surface, and center lines of the first and second opening portions are shifted from each other by a distance that is equal to or less than the thickness of the substrate.

Abstract: A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.

Abstract: A highly conductive transparent laminated glass article includes two glass plates and an adhesive film. The adhesive film has a material of Poly(Vinyl Butyral) (PVB) resin and is located between the two glass plates. At least one of the two glass plates is a highly conductive transparent glass-based circuit board with a glass substrate. A surface of the glass substrate is not contact with the adhesive film. A conductive paste, printed on the surface of the glass substrate, is baked, heated, and cooled to form a conductive circuit fused with the surface of the glass substrate. The surface of the glass substrate and an upper surface of the conductive circuit are at the same level. The highly conductive transparent laminated glass article has the characteristics of high conductivity and high light transmittance. The highly conductive transparent laminated glass article is suitable for fabrication, manufacture, and use of industrial and smart-home devices.

Abstract: An inductor component includes a core base material, a magnetic body in the core, a first conductor pattern formed on primary surface of the core, a second conductor pattern formed on secondary surface of the core, and through-hole conductors formed in through holes through the core such that the conductors are connecting the first and second patterns. The first pattern, second pattern and conductors are positioned to form an inductor such that the magnetic body is positioned on inner side of the inductor, each conductor has a diameter k1, each pattern has conductor thickness in range of 50 ?m to 200 ?m and has line patterns each having width w1 and separated by line separation distance w2, and a ratio of cross-sectional area of each line pattern to cross-sectional area of each conductor along the diameter k1 in direction of the width w1 is in range of 0.8 to 2.0.

Abstract: A light emitting device package according to an embodiment comprises: a light emitting device comprising a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer; first and second lead frames disposed to be spaced apart from each other; first and second solder portions disposed on the first and second lead frames, respectively; and first and second pads disposed between the first and second solder portions and the first and second conductive semiconductor layers, respectively, wherein at least one of the first or second pad comprises at least one of a rounding portion and a chamfer portion, wherein the first pad comprises a first-first edge and a first-second edge being positioned farther than the first-first edge from the center of the light emitting device, wherein the second pad comprises a second-first edge and a second-second edge being positioned farther than the second-first edge from the center of the light emitting devic

Abstract: A multi-layer circuit structure including a core layer, a first circuit structure, a second circuit structure, and a build-up circuit structure is provided. The first circuit structure and the second circuit structure are respectively disposed on two opposite surfaces of the core layer. The build-up circuit structure includes a first dielectric layer disposed on the first circuit structure, first conductive blind holes, a second dielectric layer disposed on the first dielectric layer, second conductive blind holes, and a patterned circuit layer disposed on the second dielectric layer. The first conductive blind holes penetrate through the first dielectric layer and electrically contact the first circuit structure. The second conductive blind holes penetrate through the second dielectric layer and electrically contact the first conductive blind holes respectively. The patterned circuit layer electrically contacts the second conductive blind holes.

Abstract: A ceramic substrate and a method for production thereof are provided, in which the ceramic substrate includes a composite of: a first ceramic layer including Sr anorthite and Al2O3 or an oxide dielectric with a dielectric constant higher than that of Al2O3; and a second ceramic layer including Sr anorthite and cordierite and having a dielectric constant lower than that of the first ceramic layer.

Abstract: A method for forming an electronic circuit on a molded plastic substrate. The method includes laser etching at least a portion of the molded plastic substrate; activating via laser selective plating the laser-etched portion of the molded plastic substrate to form one or more electrically conductive traces; placing at least two electrically conductive pads at predetermined positions along the one or more electrically conductive traces that maximize an amount of surface area contact between the at least two electrically conductive pads and the molded plastic substrate; and surface mounting an electrical component to the at least two electrically conductive pads using electrically conductive bonding material.

Abstract: A circuit member includes a metal base, an insulating layer, a conductor, and a cover layer. A termial portion of the circuit member includes a thick portion formed at a part of the insulating layer, a conductor convex portion which is a part of the conductor, and overlaps the thick portion, and a conductor extending portion. By the conductor convex portion and the conductor extending portion, a stepped side pad is formed. The stepped side gad includes a first surface along the conductor extending portion, and a second surface which rises in a thickness direction of the conductor extending portion. The stepped side pad and an element are connected by a conductive member.

Abstract: A light-emitting device (100) includes a substrate (110), a first electrode (120), an auxiliary electrode (124), an insular conductive layer (126), an insulating layer (170), an organic layer (130), and a second electrode (140). The first electrode (120) is formed over the substrate (110), and is formed using a transparent conductive material. The auxiliary electrode (124) is formed over the first electrode (120). The conductive layer (126) is formed over the first electrode (120), and is formed of the same material as that of the auxiliary electrode (124). The insulating layer (170) is formed over a portion of the first electrode (120), and covers the auxiliary electrode (124) and the conductive layer (126). The organic layer (130) is formed over the first electrode (120), and the second electrode (140) is formed over the organic layer (130).

Abstract: A multi-layer circuit member includes: a first layer formed of a conductive material, the first layer including plural signal pads and a first reference plane spaced apart from the signal pads, the first reference plane including an outer region surrounding the signal pads and an inner region separating the plurality of signal pads; a second layer formed of a conductive material, the second layer including plural signal conductors and a second reference plane spaced apart from the signal conductors, the second reference plane including an outer region surrounding the signal conductors and an inner region separating the signal conductors; a ground layer disposed at a side of the second layer opposite from the first layer; plural dielectric layers separating the first layer, the second layer, and the ground layer.

Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.

Abstract: Provided is a printed circuit board having a breakdown detection pattern formed thereon for preventing illicit acquisition of sensitive data, the printed circuit board being configured so that false detection of a disconnection or a short in the breakdown detection pattern can be prevented. The printed circuit board comprises a breakdown detection pattern layer wherein a breakdown detection pattern is formed for detecting a disconnection and/or a shorting thereof, a first pattern layer disposed more to a Y1 direction side than the breakdown detection pattern layer, a second pattern layer disposed more to a Y2 direction side than the breakdown detection pattern layer, and signal pattern layers disposed more to the Y2 direction side than the second pattern layer. Formed in the first pattern layer are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y1 direction side.

Abstract: The chip part of the present invention includes a substrate, an electrode on the substrate and having a front surface in which a plurality of recessed portions are formed toward the thickness direction thereof, and an element region having a circuit element that is electrically connected to the electrode.

Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

Abstract: Disclosed are a chip on film and a display device. the chip on film includes a plurality of output pads independent from each other extending in the first direction on a side of a base material; correspondingly, a flexible display panel in the display device includes a plurality of input pads in one-to-one correspondance with output pads extending in the first direction in the bonding region. The chip on film can improve the bonding yield and stability of the display device.

Abstract: A semiconductor storage device includes a substrate having first, second, third, and fourth lateral sides and a connector interface on the first lateral side, a nonvolatile semiconductor memory disposed on a surface of the substrate between the first lateral side and the second lateral side, which is opposite to the first lateral side, a memory controller disposed on a surface of the substrate between the first lateral side and the second lateral side, and a support for the memory controller disposed on a surface of the substrate to support at least one side of the memory controller.

Abstract: Methods for providing a sensor integrated circuit package including employing a conductive leadframe and forming a non-conductive die paddle in relation to the leadframe. The method can further include placing a die on the non-conductive die paddle to form an assembly, forming at least one electrical connection between the die and the leadframe, and overmolding the assembly to form an integrated circuit package.

Abstract: Through the use of a method of producing electronic components, a plurality of electronic components are obtained by cutting, along a predetermined cutting line, a laminate including a first circuit board and a second circuit board both mounted with circuit components. The method of producing electronic components includes: a stacking step of stacking the second circuit board on the first circuit board with a spacer interposed therewith, the first circuit board being provided with a filled via around a mounting region of the circuit components; a filling step of filling a filling space formed between the first circuit board and the second circuit board using the spacer with insulating resins; and a cutting step of cutting the laminate along the cutting line, the cutting line dividing the filled via, and exposing the filled via from a cut surface to acquire terminal portions of the electronic components.

Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Abstract: A method for manufacturing a sensor packaging according to an exemplary embodiment of the present disclosure includes: forming a via hole penetrating a main substrate by etching each of both surfaces of the main substrate; forming an insulating layer on a wall surface of the via hole and the both surfaces of the main substrate; combining a sub-substrate on which a metallic seed layer and a bonding layer having a pattern for exposing a part of the seed layer are laminated with the main substrate; forming a filling layer configured to cover an upper surface of the main substrate by filling metal in the via hole; and removing the sub-substrate from the main substrate.

Abstract: A semiconductor package includes a circuit pattern extending in a horizontal direction. The circuit pattern is conductive. A first insulation layer is disposed on the circuit pattern. A semiconductor chip is disposed on the first installation layer. The first insulation layer includes first protrusions which protrude from a bottom surface of the first insulation layer, penetrate through at least a portion of the circuit pattern, and have a mesh structure. A second protrusion protrudes from the bottom surface of the first insulation layer and penetrates at least a portion of the circuit pattern. The second protrusion is spaced apart from the semiconductor chip in the horizontal direction. The second protrusion has a width in the horizontal direction wider than that of each of the first protrusions.

Abstract: A control device for the electrical power supply for a semiconductor light source for a light module includes a printed circuit board including at least one electronic component for controlling the electrical power supply. Also provided is a housing suitable for accommodating the printed circuit board, and a protective cap for closing said housing. A first ground belt is arranged on a first face of the printed circuit board and a second ground belt is arranged on a second face of the printed circuit board opposite the first face. The housing includes first points of contact with the second ground belt and the protective cap including second points of contact with the first ground belt, the housing and/or the protective cap including at least one protective curb for all or part of the first and second points of contact.

Abstract: A circuit board includes first and second lines of surface mount pads, and a trace. The surface mount pads within the first line extend from a first edge of the circuit board toward a second edge of the circuit board. The surface mount pads within the second line extend from the first edge of the circuit board toward the second edge of the circuit board, and the surface mount pads within the second line are further from a third edge of the circuit board as compared to the surface mount pads within the first line. The trace is located on a top surface of the circuit board, and extends from the third edge to a fourth edge of the circuit board. The spacing between first adjacent surface mount pads within the first line enables the trace to be routed between the first adjacent surface mount pads with less crosstalk between signals on the trace and signals on the surface mount pads within the first line.

Abstract: A light emitting device includes: a first support member having an opening; a second support member disposed in the opening of the first support member; an adhesive member disposed between the first and second support members; a first lead electrode disposed on the second support member; a second lead electrode disposed on at least one of the first and second support members; a light emitting chip disposed on the first lead electrode, the light emitting chip being electrically connected to the second lead electrode; and a conductive layer disposed under the second support member, wherein the first support member includes a resin material, the second support member includes a ceramic material, and the first lead electrode is disposed between the light emitting chip and the second support member.

Abstract: A through conductor 11 provided in a through hole of a ceramic substrate includes a metal porous body 20, glass phases 17 and 19 formed in pores 16A to 16D of the metal porous body 20 and spaces 30 and 31 in the pores. A ratio of an area of the pores is 5 to 50 percent in a cross section of the through conductor 11. It is provided that the through conductor 11 is separated into a first part 11A on a side of the first main surface 11a and a second part 11B on a side of the second main surface 11b in a direction B of thickness of the ceramic substrate, a ratio of an area of glass phases occupying the pores in the first part 11A is higher than a ratio of an area of glass phases occupying the pores in the second part 11B. A ratio of an area of spaces occupying the pores in the first part 11A is lower than a ratio of an area of the pores occupying the pores in the second part 11B.

Abstract: Disclosed is a 2D Matrix Array Backing Interconnect Assembly that provides a structure that enables simple construction of complex wring for an ultrasonic transducer array of desired dimension. A backing interconnect assembly can be produced by forming a plurality of high density interconnect printed circuit boards, with layers each having a respective array of metal traces, wherein the metal traces are internally connected one-to-one to electrically conductive pads. An end of the metal traces are exposed at a surface to form respective conductive elements. High density interconnect printed circuit boards can be attached to a flexible printed circuit having contact pads that correspond to conductive pads of the printed circuit boards to form interconnect modules. The interconnect modules can be attached to form a backing interconnect assembly. The backing interconnect assembly with exposed conductive elements provides complex wiring interconnect for manufacture of small sized 2D ultrasonic transducer arrays.

Abstract: A package structure that includes a first redistribution structure and a second redistribution structure is provided. The first redistribution structure includes a first dielectric layer, and a first redistribution circuit in the first dielectric layer. The second redistribution structure includes a first portion on the first redistribution structure and a second portion on the first portion, and each of the portions is electrically connected to the first redistribution structure and the first portion, respectively. The circuit density of the second portion is lower than that of the first portion. The first portion includes a second dielectric layer having a second redistribution circuit therein. The second portion includes a third dielectric layer having a third redistribution circuit therein. The third dielectric layer has a stiffener layer, which is separated from the third redistribution circuit by the third dielectric layer. A method of forming a package structure is also provided.

Abstract: To produce a wiring substrate having excellent electrical characteristics with conduction failure in a hole formed in a layer made of a fluororesin material sufficiently suppressed without conducting an etching treatment using metal sodium. A process for producing a wiring substrate, which comprises forming a hole in a laminate comprising a first conductor layer, a layer (A) which is made of a fluororesin material containing a melt-moldable fluororesin having specific functional groups and a reinforcing fiber substrate and which has a dielectric constant from 2.0 to 3.5, a second conductor layer, an adhesive layer and a layer (B) made of a cured product of a thermosetting resin laminated in this order, applying, to an inner wall surface of the hole, either one or both of a treatment with a permanganic acid solution and a plasma treatment without conducting an etching treatment using metal sodium, and then forming a plating layer.

Abstract: A board includes a substrate having a bending property, a wiring pattern formed over the substrate and having a bending property, a conductive member formed over the wiring pattern, an electronic component; and a bonding member that bonds the conductive member and the electronic component to each other. And an electronic device includes a board having a bending property, a wiring pattern formed over the substrate and having a bending property, a conductive member formed over the wiring pattern, an electronic component; and a bonding member that bonds the conductive member and the electronic component to each other.

Abstract: A printed circuit board assembly (1) and a method for manufacturing a printed circuit board assembly (1) are provided. The method comprises: providing a substrate (2), printing a circuit pattern on the substrate (2) thereby forming a bottom layer (4a) of an uncured conductive material (7) and a top layer (4b) of an insulating material (8), arranging at least one electronic component (5), having at least one electrical connection part (6), on the top layer (4b) of the circuit pattern, the at least one electrical connection part (6) of the at least one electronic component (5) forming at least one electrical connection (9) with the bottom layer (4a) comprising the uncured conductive material (7), and, after arranging said at least one electronic component (5) on the top layer (4b), curing the conductive material (7) and the insulating material (8). By this method, the conductive material (7) mechanically secures said at least one electronic component (5) to the substrate (2).

Abstract: A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

Abstract: A connection substrate includes a ceramic substrate with a through hole therein and a through conductor provided in the through hole and having first main surface and a second main surface. The through conductor includes a metal porous body having first open pores communicating with the first main surface, and second open pores communication with the second main surface, first glass phases provided in the first open pores, respectively, second glass phases formed in the second open pores, respectively, first spaces provided in the first open pores, respectively, and second spaces provided in the second open pores, respectively. The first spaces are closed spaces which do not communicate with the first main surface. The second spaces are open spaces communicating with the second main surface.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to stacked dies using one or more interposers and methods of manufacture. The structure includes: at least one die comprising a plurality of via interconnects, the plurality of via interconnects comprising at least one functional via interconnect, one defective via interconnect and one redundant functional via interconnect to compensate for the one defective via interconnect; and an interposer which includes interconnects that aligns to and electrically connects the at least one functional via interconnect and the redundant functional via interconnect of different dies when the interposer is oriented in a predetermined orientation.

Abstract: The present invention is a touch detection panel that uses capacitance changes between electrodes and changes thereof to determine a position of touch. The touch panel can be used in commercial applications where using a finger, stylus, or other object is the desired method of interface with an electronic system. The touch panel includes conductive electrodes and conductive lines connecting the conductive electrodes. The conductive electrodes themselves can be made of opaque conductive material, substantially transparent conductive material, or transparent conductive material depending on the requirements of an application. The Touch panel is connected to a controller that applies current and/or voltage to the touch panel and senses current and/or voltage from the touch panel to determine either single or multiple touch locations.

Abstract: A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.

Abstract: Shield structures with reduced spacing between adjacent insulation components and systems and methods for making the same are provided. In some embodiments, different insulation components of different layers of a stack may be attached to the same surface of a shield component during a single attachment (e.g., lamination) operation to attenuate the spacing between the different insulation components attached to the shield component. Limiting the size of a spacing between adjacent insulation components along a shield component of a shield structure may limit the size of an exposed portion of the shield component, which may limit the opportunity for that exposed shield component portion to be shorted to another structure (e.g., a support structure of an electronic device that includes the shield structure).

Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure is removed, and the continuous seed metal layer remains. An interconnect metal layer is formed on the continuous seed layer, and an electrically insulating material layer is formed on the interconnect metal layer. An electrically conductive support material is formed to encapsulate a majority of the interconnect metal layer, wherein the ends of the interconnect metal layer are exposed through opposing surfaces of the electrically conductive support material to provide an interconnect extending through the electrically conductive support material.

Abstract: A method of applying an electroplated layer to a surface of a polymeric composite material, the method includes the steps of: providing an uncured polymeric composite substrate; positioning a veil layer over a surface of the uncured polymeric composite substrate, the veil layer providing a conductive surface on the uncured polymeric composite substrate, the veil layer having a mat of metal coated fibres consolidated by an organic binder material; subjecting the uncured polymeric composite substrate to a curing cycle to form a cured polymeric composite material in which the veil layer is partially exposed; and applying an electroplated layer to the conductive surface of the cured polymeric composite material.

Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

Abstract: An electric connection is provided, and has a first copper (Cu) layer, a second Cu layer, and a composite metal layer disposed between the first Cu layer and the second Cu layer. The composite metal layer has 0.01 wt. %?gallium (Ga)?20 wt. %, 0.01 wt. %?copper (Cu)?50 wt. %, and 30 wt. %?nickel (Ni)?99.98 wt. %. Moreover, a method of manufacturing the electric connection is provided, and has the steps of: (1) providing a first Cu layer and a second Cu layer; (2) forming a first Ni layer on the first Cu layer; (3) forming a second Ni layer on the second Cu layer; (4) forming a Ga layer on the first Ni layer; and (5) keeping the second Ni layer in contact with the Ga layer and carrying out a thermo-compress bonding therebetween to form the electric connection.

Abstract: A circuit board includes a rigid board including a first wiring layer formed on its upper surface side, and a flexible board including a base material having flexibility and disposed on an upper surface side of the first wiring layer, a second wiring layer formed on the base material, and a via wiring formed in a through-hole passing through the second wiring layer and the base material. The via wiring has a protrusion protruding from an upper surface of the second wiring layer, and extending on the upper surface of the second wiring layer positioned on an outer circumferential side of the through-hole.