Abstract: An objective of this invention is to provide an interlayer dielectric film with a carrier material used in a multilayer printed circuit board, which exhibits sufficient rigidity for a thin multilayer printed circuit board. According to the present invention, there is provided an interlayer dielectric film with a carrier material comprising a carrier material comprised of a metal foil or resin film and an interlayer dielectric film formed on one side of the carrier material, wherein the interlayer dielectric film is comprised of a base material impregnated with a resin; the base material has a thickness of 8 ?m to 20 ?m; and when the resin is cured at 170° C. for one hour under a pressure of 30 kgf/cm2, an elongation percentage of the interlayer dielectric film in a planar direction is 0.05% or less as determined by a TMA method.

Abstract: Fabrics with a multi-layered circuit of high reliability and a manufacturing method thereof are provided. The fabrics with the multi-layered circuit include: a base layer; a first conductive pattern which is formed on the base layer; a second conductive pattern which is formed to intersect with the first conductive pattern at least in part; and an insulating pattern which is formed on an intersection portion which is a region where the first conductive pattern and the second conductive pattern intersect.

Abstract: A printed wiring board includes a core substrate, a first buildup layer formed on a first surface of the core substrate and including an insulation layer and a conductive layer, a second buildup layer formed on a second surface of the core substrate on the opposite side with respect to the first buildup layer and including an insulation layer and a conductive layer, and an inductor device positioned in the second buildup layer and including a resin insulation layer and a coil layer formed on the resin insulation layer. The second buildup layer has a cavity in which the inductor device is accommodated.

Abstract: A touch-sensing substrate including a substrate, a patterned conductive layer and a patterned insulating layer is provided. The substrate has a plurality of first striped regions and a plurality of second striped regions. The first striped regions are intersected with the second striped regions to define a plurality of sensing-pad disposition regions. The patterned conductive layer includes a plurality of sensing pads disposed in the sensing-pad disposition regions. The patterned insulating layer is disposed on the first striped regions and the second striped regions. The patterned insulating layer and the patterned conductive layer are spliced to form a patterned light-shielding layer. The patterned light-shielding layer has a plurality of enclosed notches arranged in array, wherein parts of the enclosed notches are surrounded by the patterned conductive layer, and other parts of the enclosed notches are surrounded by the patterned conductive layer and the patterned insulating layer.

Abstract: Provided is a printed circuit board consisting of laminated substrates each with a fiberglass cloth contained in its resin and with a wiring arranged onto at least one of its surfaces, wherein, in at least one of substrates provided with a wiring for transmitting a higher speed signal than that transmitted by wirings arranged onto the other substrates, a fiberglass cloth having a different property from that of said the other substrates is contained.

Abstract: For producing a three-dimensional circuit component, an electronic component is mounted on a synthetic resin block. A plurality of electrically-conductive patterns used to establish an electrical connection to the electronic component are formed on the block along a three-dimensional shape of the block. An end of each electrically-conductive patterns is provided with a solder-disposed section. A solder is provided between the solder-disposed section and an opposed surface of the electronic component. The section of each electrically-conductive patterns other than the solder-disposed section and a section on which the electronic component is mounted is internally formed in the block. Since the section of each electrically-conductive patterns other than the section on which the electronic component is mounted is internally formed in the block, the electrically-conductive patterns are not unnecessarily exposed.

Abstract: A memory unit for a computing device is described. The memory device can include a number of memory chips, such as flash nand chips, linked together via a flexible circuit connector. During installation of the memory device, portions of the flexible circuit connector can be bent or folded in different locations to allow an orientation of the memory chips to be changed relative to one another. In one embodiment, a memory device with a number of chips can be provided in a flat configuration and then can be folded to allow the chips to be installed in a stacked configuration. In another embodiment, the flexible circuit connector can be grounded to other conductive components to allow the flexible circuit connector to be used as part of a faraday cage surrounding the memory chips.

Abstract: This invention relates to an epoxy resin composition, an insulating film formed therefrom, and a printed circuit board, and more particularly to an epoxy resin composition including an epoxy resin, an acid anhydride curing agent, etc., which exhibits improved dielectric properties by decreasing permittivity, dielectric tangent, etc. in a build-up type multilayer printed circuit board, and to an insulating film manufactured using the epoxy resin composition, and to a multilayer printed circuit board in which inner circuits formed of copper (Cu) are insulated by virtue of the insulating film to thus form multiple layers.

Abstract: The semiconductor device 1 includes a substrate 3, a semiconductor chip 4 mounted on the substrate 3, the substrate 3, a bump 5 connecting the substrate 3 and the semiconductor chip 4, and an underfill 6 filling in around the bump 5. In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.

Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

Abstract: A conductive laminate includes a substrate, a crosslinked layer, and a conductive layer and a protective layer, wherein (i) the crosslinked layer is composed of a crosslinked polymer including a structure in which compounds, each having two or more carbon-carbon double bond groups contributing to a polymerization reaction, are subjected to the polymerization reaction, and also the mass content of a unit structure portion of the carbon-carbon double bond group in the structure derived from the carbon-carbon double bond group is from 9 to 26% by mass relative to the total mass of the crosslinked layer; (ii) the crosslinked layer has a thickness of 50 nm to 1 ?m; (iii) the conductive layer contains a conductive component having a network structure composed of linear structures; and (iv) the protective layer has an average thickness (t) of 70 nm to 1 ?m.

Abstract: There are provided a resin composition including: (a) a maleimide compound with at least two N-substituted maleimide groups per molecular structure; and (b) a silicone compound with at least one amino group per molecular structure and also provided a prepreg, a laminated plate, and a printed wiring board that are formed by using this resin composition. The multi-layered printed wiring board produced by using the laminated plate produced by laminating and molding the prepreg obtained from the resin composition of the present invention has excellent glass transition temperature, coefficient of thermal expansion, solder heat resistance, and warp characteristics. The multi-layered printed wiring board is useful as a highly integrated printed wiring board for an electronic device.

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract: Methods and structures are provided for implementing feed-through and domain isolation using ferrite and containment barriers. A vertical isolator is provided between a first domain and a second domain on a printed circuit board with signals passing between the first domain and the second domain. The vertical isolator is placed over a domain separation gap between the first and second domains in the printed circuit board, the vertical isolator having a vertical isolation barrier between a first vertical plate coupled to the first domain and a second vertical plate coupled to the second domain. The vertical isolation barrier is formed of a unitary ferrite block or a non-conductive magnetic absorber material. A plurality of capacitance feed-through plates and a dielectric material are provided within the vertical isolator.

Abstract: The present invention provides an insulating film including: a (A) binder polymer; (B) spherical organic beads; and (C) fine particles containing at least one element selected from the group consisting of phosphorus, aluminum, and magnesium, both the (B) spherical organic bead and the (C) fine particles being dispersed in a predetermined state in the insulating film.

Abstract: A laminated multilayer electronic support structure comprising a dielectric with integral vias and feature layers and further comprising a planar metal core characterized by a thickness of less than 100 microns.

Abstract: A wiring board includes a core layer; a through hole penetrating through the core layer in a thickness direction of the core layer; and an electronic part accommodated inside the through hole, wherein the through hole includes a first opening portion provided on a first surface of the core layer, a second opening portion provided on a second surface of the core layer, and an inward protruding portion inwardly protruding relative to the first and second opening portions, and wherein the electronic part is held by the inward protruding portion.

Abstract: Disclosed is a manufacturing method of a multilayer wiring board. The multilayer wiring board includes an outer resin insulation layer made of an insulating resin material, containing a filler of inorganic oxide and having an outer surface defining a chip mounting area to which an electronic chip is mounted with an underfill material filled in between the outer resin insulation layer and the electronic chip and holes through which conductor parts are exposed. The manufacturing method includes a hole forming step of forming the holes in the outer resin insulation layer by laser processing, a desmear treatment step of, after the hole forming step, removing smears from inside the holes of the outer resin insulation layer, and a filler reducing step of, after the desmear treatment step, reducing the amount of the filler exposed at the outer surface of the outer resin insulation layer.

Abstract: A thin film stack (100, 200) is provided for use in electronic devices such as photovoltaic devices. The stack (100, 200) may be integrated with a substrate (110) such as a light transmitting/transmissive layer. An electrical conductor layer (120, 220) is formed on a surface of the substrate (110) or device layer such as a transparent conducting (TC) material layer (120, 220) with pin holes or defects (224) caused by manufacturing. The stack (100) includes a thin film (130, 230) of metal that acts as a barrier for environmental contaminants (226, 228). The metal thin film (130, 230) is deposited on the conductor layer (120, 220) and formed from a self-healing metal such as a metal that forms self-terminating oxides. A permeation plug or block (236) is formed in or adjacent to the thin film (130, 230) of metal at or proximate to the pin holes (224) to block further permeation of contaminants through the pin holes (224).

Abstract: A printed circuit board having a plating pattern buried in a via. The printed circuit board has: an insulating substrate including an electrically insulating resin; a via hole passing through the insulating substrate; a via including a metal layer formed on an inner wall of the via hole and a filler charged in the via hole; a circuit layer including a circuit pattern buried in the insulating substrate and transmitting an electrical signal; and a plating pattern buried in an end of the filler.

Abstract: Semiconductor chip mounting yield and semiconductor package reliability deteriorate due to warpage of a multilayer circuit board. A multilayer circuit board (1) using an interlayer insulating layer (6) can suppress warpage of the entire multilayer circuit board (1) by making the interlayer insulating layer (6) serve as a buffer material. In the multilayer circuit board (1) using the interlayer insulating layer (6), conductor circuit layers (11) and interlayer insulating layers (6) are alternately arranged. The interlayer insulating layer (6) to be used in the multilayer circuit board (1) includes a first insulating layer and a second insulating layer having an elastic modulus higher than that of the first insulating layer.

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Abstract: A multilayer substrate includes a plurality of stacked thermoplastic resin layers each including an in-plane conductive pattern provided on one principal surface thereof and an interlayer conductive portion arranged to penetrate through the thermoplastic resin layer in a thickness direction. The plurality of thermoplastic resin layers include a first thermoplastic resin layer and a second thermoplastic resin layer, a stacking direction of which is inverted with respect to a stacking direction of the first thermoplastic resin layer. The second thermoplastic resin layer is thicker than the first thermoplastic resin layer. One end in the thickness direction of the interlayer conductive portion provided in the second thermoplastic resin layer is connected with the interlayer conductive portion of the thermoplastic resin layer adjacent to the second thermoplastic resin layer in the thickness direction such that the in-plane conductive pattern is not interposed therebetween.

Abstract: Disclosed is a prepreg obtained by impregnating a woven fabric base with a thermosetting resin composition, wherein the thermosetting resin composition contains 80 to 200 volume parts of an inorganic filler per 100 volume parts of a thermosetting resin, and the inorganic filler contains (A) gibbsite aluminum hydroxide particles having an average particle diameter (D50) of 2 to 15 ?m, (B) at least one inorganic component selected from the group consisting of boehmite particles having an average particle diameter (D50) of 2 to 15 ?m and inorganic particles that have an average particle diameter (D50) of 2 to 15 ?m and that contain crystal water having a release initiation temperature of 400° C. or higher or contain no crystal water, and (C) aluminum oxide particles having an average particle diameter (D50) of 1.

Abstract: A multilayer electronic support structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein a stacked via structure crossing at least two via layers of the plurality of layers comprises at least two via posts in neighboring via layers wherein the at least two stacked via posts in neighboring layers have different dimensions in the X-Y plane, such that the stacked via structure tapers.

Abstract: A spring finger interconnection system can include a plug and a receptacle. In one embodiment, the plug can include spring finger contacts configured to carry electrical signals. The receptacle can include a cavity to receive the plug and the cavity can be constructed with printed circuit board fabrication techniques. In one embodiment, the cavity can be formed, at least in part, in a pre-impregnation layer and a first and a second layer can be disposed above and below the pre-impregnation layer to further form the cavity. In one embodiment, contacts can be arranged on the first layer to contact the spring fingers when the plug is inserted into the cavity. In another embodiment, contacts can be arranged on both the first and the second layers. In yet another embodiment, the cavity can be shaped to aid in contact-to-spring finger alignment when the plug is inserted in the cavity.

Abstract: A multilayer electronic structure comprising a plurality of dielectric layers extending in an X-Y plane and comprising at least one coaxial pair of stacked posts extending through at least one dielectric layer in a Z direction that is substantially perpendicular to the X-Y plane, wherein the coaxial pair of stacked via posts comprises a central post surrounded by a torroidal via post separated from the central post by a separating tube of dielectric material.

Abstract: An electronic component built-in substrate comprises a substrate having a core member with an opening in which an electronic component is disposed, a first auxiliary insulating layer formed on a first surface of the core member; a second auxiliary insulating layer formed on a second surface of the core member, the second auxiliary insulating layer having a first via hole, a filling resin portion filling a gap between the electronic component and a side surface of the opening of the core member, and a first wiring layer formed on the second auxiliary insulating layer and connected to the connection terminal of the electronic component through the first via hole. The whole of the first surface and the whole of the second surface of the core member are in direct contact with the first auxiliary insulating layer and the second auxiliary insulating layer, respectively.

Abstract: A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer.

Abstract: Circuit modules and methods of construction thereof that contain composite meta-material dielectric bodies that have high effective values of real permittivity but which minimize reflective losses, through the use of host dielectric (organic or ceramic), materials having relative permittivities substantially less than ceramic dielectric inclusions embedded therein. The composite meta-material bodies permit reductions in physical lengths of electrically conducting elements such as antenna element(s) without adversely impacting radiation efficiency. The meta-material structure may additionally provide frequency band filtering functions that would normally be provided by other components typically found in an RF front-end.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract: Provided is a method of manufacturing a printed circuit board including, disposing first and second insulating members and first and second conductive films on both sides of a separating member to perform a thermocompression bonding process on the first and second insulating members and the first and second conductive films on the both sides of the separating member, so as to attach the first member to the second member with the separating member therebetween and attach the first insulating member to the first conductive film and attach the second insulating member to the second conductive film, selectively removing the first and second conductive films to form first and second circuit patterns, and cutting the separating member and the first and second insulating members to separate the first and second insulating members with the first and second circuit patterns from the separating member.

Abstract: Provided is a method of manufacturing a circuit board including preparing a board structural body (11) and covering a conductor circuit element (13) on an outermost layer of the board structural body (11) with a cover film (14), wherein a heat treatment is performed while having a release material (15) interposed between the cover film (14) and a heat-processing device. The release material (15) is a laminate at least including, sequentially from the cover film toward the heat-processing device, a low friction film (16) selected from an ultrahigh-molecular-weight polyethylene film and a polytetrafluoroethylene film, a first aluminum foil (17), a first high-density polyethylene film (18a), a second high-density polyethylene film (18b), and a second aluminum foil (19). The first high-density polyethylene film (18a) and the second high-density polyethylene film (18b) are positioned such that respective MD directions are perpendicular to each other.

Abstract: A printed circuit board includes a line intensive distribution area, a line sparse distribution area, a solder mask layer, and a signal layer. A first signal line is laid on the signal layer. The first signal line crosses the line intensive distribution area and the line sparse distribution area. The first signal line is narrower in the line intensive distribution area than in the line sparse distribution area. The solder mask layer is thicker in the line intensive distribution area than in the line sparse distribution area.

Abstract: There is provided a space transformer for a probe card, including: a substrate having a first surface and a second; a plurality of first pads formed on the first surface to be spaced apart from each other and connected to a printed circuit board of a probe card; a plurality of second pads formed on the second surface in positions corresponding to those of the first pads and receiving external electrical signals applied thereto; a plurality of via electrodes penetrating through the substrate and respectively connected to the plurality of first pads and the plurality of second pads formed in the positions corresponding to each other; a ground layer formed to cover the second surface and provided with a plurality of second pad exposure holes; and an insulating layer formed to cover the ground layer and the plurality of second pads.

Abstract: The present invention provides a substrate for an optical semiconductor apparatus for mounting optical semiconductor devices, the substrate includes first leads to be electrically connected to first electrodes of the optical semiconductor devices and second leads to be electrically connected to second electrodes of the optical semiconductor devices, wherein the first leads and the second leads are arranged each in parallel, a molded body of a thermosetting resin composition is molded in a penetrating gap between the first leads and the second leads, a reflector of the thermosetting resin composition is molded at a periphery of respective regions on which the optical semiconductor devices are to be mounted, and the resin molded body and the reflector are integrally molded with the first leads and the second leads by injection molding.

Abstract: Based on a result of repeated analysis of stress caused by application of an external impact in a circuit board, which is rectangular or substantially rectangular in plan view and includes mounting electrodes, included in an electronic component, the mounting electrodes near four corners of the circuit board, of the mounting electrodes provided on a back surface of the circuit board included in the electronic component, are provided at positions shifted from diagonal lines of the back surface. Hence, the stress produced near the four corners of the circuit board is reduced, and this can effectively prevent a fracture, a chip, and a crack from being caused in the circuit board.

Abstract: Provided is a touch panel. The touch panel includes a substrate and an electrode member disposed on the substrate. The electrode member includes a base material for electrode having first and second surfaces opposite to each other, a first electrode disposed on the first surface, and a second electrode disposed on the second surface.

Abstract: Disclosed is an electrode member. The electrode member includes a substrate, and an electrode provided in the shape of a mesh on the substrate.

Abstract: There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: Disclosed is a halogen-free flame-retardant epoxy resin composition for printed circuit board, which includes (A) a halogen-free epoxy resin; (B) a copolymer of styrene and maleic anhydride used as a first curing agent; (C) poly(1,3-phenylene methylphosphonate) used as a second curing agent; (D) a curing accelerator; and (E) an inorganic filler.

Abstract: A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount (1) for having a semiconductor device mounted thereon comprises a submount substrate (2), a substrate protective layer (3) formed on a surface of the submount substrate (2), an electrode layer (4) formed on the substrate protective layer (3) and a solder layer (5) formed on the electrode layer (3) wherein the electrode layer (4) is made having an average surface roughness of less than 1 ?m. The reduced average surface roughness of the electrode layer (4) improves wettability of the solder layer (5), allowing the solder layer (5) and a semiconductor device to be firmly bonded together without any flux therebetween. A submount (1) is thus obtained which with the semiconductor device mounted thereon is reduced in heat resistance, reducing its temperature rise and improving its performance and service life.

Abstract: Silsesquioxane polymers, silsesquioxane polymers in negative tone photo-patternable dielectric formulations, methods of forming structures using negative tone photo-patternable dielectric formulations containing silsesquioxane polymers, and structures made from silsesquioxane polymers.

Abstract: Provided are a multi-layer interconnection structure and a manufacturing method thereof. The multi-layer interconnection structure includes a substrate; a first wiring on the substrate; an interlayer insulation layer on the first wiring; a second wiring on the interlayer insulation layer; and a via contact including at least one conductive filament penetrating through the interlayer insulation layer between the second wiring and the first wiring to be electrically connected to the first wiring and the second wiring.

Abstract: The present invention relates to design and processes for the manufacture of backplane for segment displays. The process comprises: a) forming conductive lines on a non-conductive substrate layer; b) covering the conductive lines with a photoimageable material; c) forming conductive areas connected to the conductive lines and embedded in the photoimageable material; d) plating a conductive material over the photoimageable material to form segment electrodes; and e) optionally filling gaps between said segment electrodes with a thermal or radiation curable material followed by hardening said thermal or radiation curable material.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: Systems and methods for shielding circuitry from interference with conformal coating are disclosed. Systems having conformal EMI shields according to embodiments are provided by applying insulating and conductive layers to areas of a printed circuit board (PCB). This produces systems that may be thinner and also smaller in surface area, and that may be suitable as part of electronic devices.

Abstract: A porous electrode sheet (1) includes a resin film (2) being transparent and having insulating properties, and a transparent electrode (3) placed on one face (2a) of the resin film (2). The resin film (2) is provided with a plurality of through holes (21) extending linearly from the one face (2a) to the other face (2b). The transparent electrode (3) has openings (31) at positions corresponding respectively to the through holes (21). The through holes (21) of the resin film (2) and the openings (31) of the transparent electrode (3) communicate with each other, and thereby form passages (10) penetrating the porous electrode sheet (1) in the thickness direction.