Abstract: A circuit board comprising a first sub-circuit board, a second sub-circuit board, and a circuit connection structure. The first and second sub-circuit board having a first and second connection terminal, respectively. The circuit connection structure has a first port for mating with the first connection terminal, and a second port for mating with the second connection terminal. The first connection terminal, the second connection terminal, the first port, and the second port are configured such that when the first sub-circuit board is connected to the second sub-circuit board through the circuit connection structure, a first connection terminal end face faces the first port in a first direction, and a second connection terminal end face faces the second port in a second direction, and an angle between the first direction and the second direction is greater than 90° and less than or equal to 180°.

Abstract: Discharge circuits, devices and methods. In some embodiments, a MEMS device can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS device can further include a discharge circuit implemented relative to the electromechanical assembly. The discharge circuit can be configured to provide a preferred arcing path during a discharge condition affecting the electromechanical assembly. The MEMS device can be, for example, a switching device, a capacitance device, a gyroscope sensor device, an accelerometer device, a surface acoustic wave (SAW) device, or a bulk acoustic wave (BAW) device. The discharge circuit can include a spark gap assembly having one or more spark gap elements configured to facilitate the preferred arcing path.

Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.

Abstract: A vibrator device includes a base, a vibrator that includes a vibrator element and a vibrator element package, which accommodates the vibrator element and has a first terminal on a surface on a base side, a circuit element that is disposed between the base and the vibrator and has a first connection pad on a surface on a vibrator side, and a conductive connecting member that is disposed between the circuit element and the vibrator, bonds the circuit element and the vibrator together, and electrically connects the first connection pad and the first terminal together.

Abstract: Devices and systems for controlling electrostatic discharge on electronic at the interface of mating electrical connectors. An electrostatic discharge (ESD) control device comprises a substrate and at least one connector pin hole. An outer edge of the substrate is also electrically conductive and configured to be electrically connected to a ground. Each the connector pin hole(s) is electrically conductive such that it electrically connects to a respective pin of one of the mating electrical connectors. For each of the connector pin hole(s), an electrically conductive trace is disposed in the substrate. Each of the traces has a pair of opposing sharp points in close proximity to each other and directed at each other. One of the sharp points is electrically connected to the electrically conductive connector pin hole, and the other sharp point is electrically connected to the electrically conductive outer edge of the substrate.

Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

Abstract: A failure prediction device is provided for predicting, using a structure having a high degree of design freedom, failure at a soldered joint due to vibration stress, and a circuit board using the same. The failure prediction device is disposed on a substrate having a mounting component that is fixed thereon through a solder joint. The failure prediction device is provided with a load amplifying portion that includes a pair of support leg portions each having one end to be fixed to the substrate or the mounting component, and a sacrificial fracture portion that is supported by the other ends of the pair of support leg portions, wherein the load amplifying portion transmits, to the sacrificial fracture portion via the pair of support leg portions, vibration that is applied to the substrate.

Abstract: An electronic component includes a body, external electrodes including head portions disposed on external surfaces of the body, and band portions extending from the head portions to top and bottom surfaces and both side surfaces of the body, respectively, each of the band portions including an extending portion disposed on at least one surface of the body extending beyond a band portion disposed on another surface of the body, and metal frames electrically connected to the pair of external electrodes, respectively. The metal frames includes support portions bonded to the head portions, mounting portions extending from ends of the support portions in a first direction and spaced apart from the body and the external electrodes, and bonding portions extending from the support portions to be bonded to the extending portions.

Abstract: A printed circuit board includes an electronic component having a first land, and a printed wiring board having a second land soldered to the first land. The printed wiring board includes a first wiring pattern, a resist opening formed around the second land configured to expose at least part of the first wiring pattern to outside, and a second wiring pattern disposed at least a portion of a periphery of the resist opening. A heat capacity of the first wiring pattern is smaller than that of the second wiring pattern.

Abstract: An electronic control unit has a substrate that includes a terminal connection portion that is a through hole that extends through the substrate from a first surface to a second surface. A resist opening along an outer edge of the terminal connection portion exposes a circuit pattern from a surface resist layer. A plurality of vias are disposed at positions adjacent to the resist opening in a heat receiving area to facilitate the transfer of heat during a soldering process from the first surface to the second surface.

Abstract: An optical circuit includes a substrate, a waveguide, and a mirror. The substrate includes a first surface. The waveguide includes a first core. The first core is formed of a semiconductor material. The waveguide is over a first surface of the substrate. The mirror reflects light emitted from the waveguide in a direction away from the first surface of the substrate. The mirror is a concave mirror. The waveguide includes a region that functions as an SSC.

Abstract: A glue dispensing method includes making a glue dispensing hole in a processing region. The processing region is a region that is in a surface mount region corresponding to the surface mount component and in which no electronic circuit and pad exist. The method also includes welding the surface mount component onto the circuit board. The method further includes injecting glue into the glue dispensing hole, to fill a gap between the surface mount component and the circuit board, and placing the circuit board still, to wait for curing of the glue.

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

Abstract: A printed circuit substrate includes a circuit unit, a first main frame ground interconnection, a first sub frame ground interconnection spaced away from the first main frame ground interconnection in a first direction, and a first conductive via connecting the first main frame ground interconnection and the first sub frame ground interconnection to each other. In plan view from the first direction, a second outer periphery of the first sub frame ground interconnection is surrounded by a first outer periphery of the first main frame ground interconnection. Thus, a printed circuit substrate that can prevent the circuit unit from malfunctioning can be provided.

Abstract: A light emitting diode package includes an upper housing and a lower housing. The upper housing includes a first light emitting diode (LED) chip arranged therein, a second LED chip arranged to be spaced apart from the first LED chip in a first direction, two light discharge structures, first electrodes formed on a lower surface of the first LED chip, and second electrodes formed on a lower surface of the second LED chip. The lower housing includes at least three grooves at a lower surface thereof. The lower housing further includes three or more pads. The first pair of via-holes are arranged to connect the first electrodes to one or more of the pads in a second direction perpendicular to the first direction. The second pair of via-holes are arranged to connect the second electrodes to one or more of the pads in the second direction.

Abstract: The present disclosure relates to a substrate apparatus and a method of manufacturing a substrate apparatus capable of improving a manufacturing quality and reliability of the substrate apparatus as an electronic device. By laminating a plurality of sheet-like substrates on which a wiring pattern is formed, an individual substrate in which internal wiring is formed is formed, and the individual substrate physically and electrically connects two substrates. The present disclosure is capable of being applied to the substrate apparatus.

Abstract: An element body of a rectangular parallelepiped shape includes a first principle surface arranged to constitute a mounting surface, a second principle surface opposing the first principle surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction. An external electrode is disposed at an end portion of the element body in the third direction. The external electrode includes a conductive resin layer formed on the end surface. A thickness of the conductive resin layer gradually increases from the second principle surface toward the first principle surface in the first direction. The conductive resin layer includes a thickest portion at a position near the first principle surface in the first direction.

Abstract: A relay apparatus in a wireless power transmission system includes a relay power reception antenna that receives power transmission alternating current power from a power transmission power transmission antenna, a relay rectifier that converts the power transmission alternating current power into relay direct current power, a relay inverter circuit that converts the relay direct current power into relay alternating current power, and a relay power transmission antenna that wirelessly transmits the relay alternating current power. When transmitting data to the power transmission apparatus through amplitude modulation, the relay apparatus varies amplitude of voltage of the power transmission alternating current power received by the relay power reception antenna between a first amplitude and a second amplitude and performs control for eliminating a difference between a third amplitude of the relay alternating current power and a fourth amplitude of the relay alternating current power.

Abstract: First and second circuit patterns (5,6) are provided on an insulating substrate (1). First and second semiconductor chips (7,8) are provided on the first circuit pattern (5). A relay circuit pattern (10) is provided between the first semiconductor chip (7) and the second semiconductor chip (8) on the insulating substrate (1). A wire (11) is continuously connected to the first semiconductor chip (7), the relay circuit pattern (10), the second semiconductor chip (8) and the second circuit pattern (6) which are sequentially arranged in one direction.

Abstract: A multilayer ceramic electronic component array includes a plurality of multilayer ceramic electronic components including a ceramic body including a dielectric layer and first and second internal electrodes, and first and second external electrodes, respectively; and an interposer including an insulating body disposed below the plurality of multilayer ceramic electronic components, a first terminal electrode disposed on the insulating body and connected to at least a portion of the respective first external electrodes of the plurality of multilayer ceramic electronic components, and a second terminal electrode disposed on the insulating body and connected to at least a portion of the respective second external electrodes of the plurality of multilayer ceramic electronic components.

Abstract: A board element for board-to-board interconnect formation is provided. An embodiment includes embedding a signal via element in the board element and cutting through respective sections of the board element and the signal via element to expose a new board element edge and an outwardly facing surface of the signal via element.

Abstract: A stacked tube heat exchanger consisting of tubes that are affixed to a header or headers that are additively manufactured.

Abstract: A plurality of lid structures include at least one lid structure configured to overlie one or more heat sources within a multi-chip-module and at least one lid structure configured to overlie one or more temperature sensitive components within the multi-chip-module. The plurality of lid structures are configured and positioned such that each lid structure is separated from each adjacent lid structure by a corresponding thermal break. A heat spreader assembly is positioned in thermally conductive interface with the plurality of lid structures. The heat spreader assembly is configured to cover an aggregation of the plurality of lid structures. The heat spreader assembly includes a plurality of separately defined heat transfer members respectively configured and positioned to overlie the plurality of lid structures. The heat spreader assembly is configured to limit heat transfer between different heat transfer members within the heat spreader assembly.

Abstract: A voltage-controlled oscillator (VCO) having an operating frequency dependent on a total capacitance of selectable tuning capacitors can be fabricated within an integrated circuit (IC). The VCO can include active electronic devices fabricated within a set of lower layers of the IC and selectable tuning capacitors having electrically conductive structures separated by dielectric material fabricated within a set of upper layers of the IC. The upper layers of the IC are located above the set of lower layers of the IC. The VCO can also include a set of interconnect structures configurable to select a total capacitance of the selectable tuning capacitors by electrically interconnecting the first portion of the VCO to capacitors of the at least one selectable tuning capacitor.

Abstract: A method for embedding a component in a printed circuit board or a printed circuit board intermediate product, wherein the printed circuit board or the printed circuit board intermediate product comprises at least one insulating layer made of a prepreg material, and the component is fixed by the resin of the prepreg material, is characterized by the following steps: providing a combination of the layers of the printed circuit board, or of the printed circuit board intermediate product, wherein this combination includes at least one curable prepreg material; creating a clearance in the combination for accommodating the component to be embedded; covering at least the region of the clearance with a first temporary carrier layer on a first side of the combination; positioning the component to be embedded in the clearance by way of the first temporary carrier layer; covering at least the region of the clearance on the second side of the combination with a second temporary carrier layer; compressing the combinatio

Abstract: Provided are a solid-state imaging apparatus capable of having reduction in height and size while easily controlling warp with high handling reliability when the solid-state imaging apparatus is mounted on another substrate, and a method for manufacturing the solid-state imaging apparatus. The solid-state imaging apparatus includes a substrate having a recess on a surface thereof, an imaging chip disposed and fixed on an inner bottom surface of the recess, and a filler filled and solidified in the whole of a gap between a side surface of the imaging chip and an inner surface of the recess. A groove having a substantially constant width is formed between the side surface of the imaging chip and the inner surface of the recess. An expansion portion having width equal to or larger than the constant width is in a portion of the groove.

Abstract: An electronic component mounting substrate 10A is configured of an electronic component 20, and a mounting substrate 10 mounting the electronic component 20 thereon, in which concave parts 24 are formed on a mounting surface 23 of the electronic component 20 opposite to the mounting substrate 10, a connection part 39 is exposed at the bottom of the concave part 24, and electronic component attachment parts 12 provided on the mounting substrate 10 are soldered to the connection parts 39 provided in the electronic component 20.

Abstract: An electronic component includes a multilayer capacitor including a capacitor body, and an external electrode disposed on an external surface of the capacitor body, an interposer including an interposer body, and an external terminals disposed on an external surface of the interposer body, and an encapsulation portion disposed to cover the multilayer capacitor. The external terminal includes a bonding portion disposed on a first surface of the interposer body to be electrically connected to the external electrode, a mounting portion disposed on a second surface of the interposer opposing the first surface, and a connection portion disposed on an end surface of the interposer to electrically connect the bonding portion to the mounting portion. A thickness of the encapsulation portion is within a range from 0.001 to 0.01 of a length of the electronic component.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and first and second internal electrodes stacked to be alternately exposed to first and second outer surfaces with the dielectric layer interposed therebetween; and first and second external electrodes disposed on the first and second outer surfaces of the ceramic body to be electrically connected to the first and second internal electrodes, respectively. The ceramic body further includes a protective layer disposed on at least one of upper and lower portions of the first and second internal electrodes, the protective layer includes a plurality of dummy electrode cells each having the plurality of dummy electrodes stacked thereon, and a thickness from the uppermost dummy electrode to the lowermost dummy electrode of each of the plurality of dummy electrode cells is greater than a length of each of the plurality of dummy electrode cells.

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers.

Abstract: The present invention relates to a capacitor assembly (1) which comprises at least one ceramic multilayer capacitor (2) comprising ceramic layers (4) and first and second electrodes (5a, 5b) arranged therebetween, and a base (3). The base (3) comprises a substrate (9) and conductor tracks (10a, 10b), wherein the conductor tracks (10a, 10b) lead from a top side (11) of the substrate (9) said top side facing toward the multilayer capacitor (2), to an underside (12) of the substrate (9), said underside facing away from the multilayer capacitor (2). The multilayer capacitor (2) is mechanically secured on the base (3). The first electrodes (5a) and the second electrodes (5c) are electrically contacted with the conductor tracks (10a, 10b).

Abstract: A resin multilayer substrate includes a first resin layer including a thermoplastic resin as a main material, a second resin layer including the thermoplastic resin as a main material and superposed on the first resin layer, a first interlayer-connection conductor passing through the first resin layer in a thickness direction, and a first conductor pattern at an area including a region in which the first interlayer-connection conductor is exposed at the surface of the first resin layer between the first resin layer and the second resin layer. The first conductor pattern includes a portion in or at which a portion of the first interlayer-connection conductor is disposed. The first conductor pattern includes a first portion covering the region exposed at the surface of the first resin layer; and a second portion disposed surrounding the first portion. The first portion and the second portion have different thicknesses from each other.

Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: An electronic component includes: a plurality of multilayer capacitors stacked in multiple rows and columns and each having external electrodes on both ends thereof in a first direction; and a board including a body and a connection portion. The connection portion includes: a plurality of positive electrode land patterns; a plurality of negative electrode land patterns; positive and negative electrode terminal patterns formed on a lower surface of the body to be spaced apart from each other in the first direction; a positive electrode connection portion connecting the plurality of positive electrode land patterns to the positive electrode terminal pattern; and a negative electrode connection portion connecting the plurality of negative electrode land patterns to the negative electrode terminal pattern.

Abstract: The disclosure is related to various connecting methods for a welding auxiliary joining part having a head and a rounded tip for setting in at least one first component having a die as counter-bearing, which has a concave recess with an inner wall having at least in sub-areas an arc shape and having a matrix radius MR in the range from 1.0 mm?MR?60 mm, for preparing a subsequent welding method. The geometry of the welding auxiliary joining part and the die meet the following condition: 0.001 ? SR MR ? 0.1 , in particular 0.002 ? SR MR ? 0.08 , wherein SR designates a tip radius of the rounded tip of the welding auxiliary joining part.

Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

Abstract: Provided is a high density multi-component package and a method of manufacturing a high density multi-component package. The high density multi-component package comprises at least two electronic components wherein each electronic component of the electronic components comprise a first external termination and a second external termination. At least one interposer is between the adjacent electronic components and attached to the interposer by an interconnect wherein the interposer is selected from an active interposer and a mechanical interposer. Adjacent electronic components are connected serially.

Abstract: In order to inspect a substrate, an image information of a substrate before applying solder is displayed. Then, at least one inspection region on the substrate is image-captured to obtain an image of the inspection region that is image-captured. Then, image information that is to be displayed is renewed and the renewed image information is displayed. And, in order to inspect a foreign substance, obtained image of the inspection region is compared with a reference image of the substrate. Therefore, an operator can easily catch a region corresponding to a specific region of the image that is displayed, and easily detect a foreign substance on the substrate.

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Abstract: Provided is a high density multi-component package and a method of manufacturing a high density multi-component package. The high density multi-component package comprises at least two electronic components wherein each electronic component of the electronic components comprise a first external termination and a second external termination. At least one interposer is between the adjacent electronic components and attached to the interposer by an interconnect wherein the interposer is selected from an active interposer and a mechanical interposer. Adjacent electronic components are connected serially.

Abstract: A printed circuit board has a printed wiring board and a semiconductor package mounted on the printed wiring board. The printed wiring board and the semiconductor package are connected with a plurality of solder balls. An underfill material covering the plurality of solder balls is filled between the printed wiring board and the semiconductor package. The underfill material has a relative dielectric constant of 8.6 or more and 54.4 or less. Thus, crosstalk noise generated in wiring in the out-of-plane direction is reduced without increasing the mounting area.

Abstract: According to one embodiment, an interposer substrate for switching wiring lines, includes a substrate body having through holes penetrating from a first main surface thereof to a second main surface, through-conductive portions provided respectively in the through holes, grouped into first groups and second groups different from the first groups, first wiring lines each provided on the first main surface and for a respective one of the first groups, second wiring lines each provided on the second main surface and for a respective one of the second groups, first terminals provided on the first main surface and connected respectively to the first wiring lines, and second terminals provided on the second main surface and connected respectively to the second wiring lines.

Abstract: A PCB and a signal transmission system are provided. The PCB includes a connection module, and at least two signal layers and at least two reference layers spaced apart. The connection module comprises a first connection terminal and a second connection terminal. The first connection terminal is connected to at least one first signal layer and is connectable to an external optical interface. The second connection terminal is connected to at least one second signal layer and is connectable to an external electrical interface. Each reference layers is provided with a through-hole, and for each reference layers, there is an overlapping region between a projection region of an orthogonal projection of the connection module onto the reference layer and a hole region of the through-hole arranged on the reference layer.

Abstract: An electronic device, and methods of manufacturing the same are disclosed. The method of manufacturing the electronic device includes forming a first metal layer on a first substrate, forming an integrated circuit or a discrete electrical component on a second substrate, forming electrical connectors on input and/or output terminals of the integrated circuit or discrete electrical component, forming a second metal layer on the first metal layer, the second metal layer improving adhesion and/or electrical connectivity of the first metal layer to the electrical connectors on the integrated circuit or discrete electrical component, and electrically connecting the electrical connectors to the second metal layer.

Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.

Abstract: A thin film component sheet includes: a conducting interconnection layer formed of a conductor; an insulating layer that is laminated on the conducting interconnection layer and is formed of an insulating material; and a plurality of thin film electronic components, each of which has a pair of first and second electrode layers and a dielectric layer provided between the first and second electrode layers, and which are arranged to be separated on the insulating layer. In a state in which a main surface of the first electrode layer in each of the plurality of thin film electronic components is exposed to an outside on a main surface of one side of the thin film component sheet, a flat surface of the main surface of the thin film component sheet is formed.

Abstract: A touch controller includes a touch data generator that is connected to a plurality of sensing lines, the touch data generator sensing a change in capacitance of a sensing unit connected to each of the sensing lines and generating touch data by processing the sensing signal corresponding to the result of sensing; and a signal processor that controls a timing of generating the touch data by receiving at least one piece of timing information for driving a display panel from a timing controller, and then providing either the timing information or a signal generated from the timing information as a control signal to the touch data generator.

Abstract: A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.