Abstract: A package is disclosed. The package includes a substrate and an electrical component vertically mounted to the substrate. The electrical component has a first end, a second end vertically spaced from the first end, and a side wall extending from the first end to the second end. The first end of the electrical component is positioned between the substrate and the second end of the electrical component. The package can also include a molding material disposed at least partially along the side wall of the electrical component.

Abstract: An apparatus includes a module base configured to carry one or more devices to be cooled. The module base includes a cover and a heat sink connected to the cover. The cover includes first and second encapsulation layers and a thermal spreader between the encapsulation layers. The first encapsulation layer is configured to receive thermal energy from the device(s). The thermal spreader is configured to spread out at least some of the thermal energy and to provide the spread-out thermal energy to the second encapsulation layer. The heat sink is configured to receive the thermal energy through the second encapsulation layer and to transfer the thermal energy out of the module base. The first encapsulation layer includes multiple openings. The module base includes multiple tabs inserted through the openings. Each tab is configured to provide a thermal interface between at least one of the device(s) and the thermal spreader through the first encapsulation layer.

Abstract: A multi-layer ceramic electronic component includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a direction of a first axis, internal electrodes positioned between the ceramic layers, and a side surface facing in a direction of a second axis orthogonal to the first axis, the internal electrodes being exposed from the side surface, the multi-layer unit having a first dimension of 0.5 mm or less along a direction of a third axis orthogonal to the first axis and the second axis, the side surface having an area of 0.1 mm2 or more. The side margin covers the side surface of the multi-layer unit.

Abstract: An electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween, having first to sixth surfaces, and including one ends of the first and second internal electrodes exposed through the third and fourth surfaces, respectively; first and second external electrodes respectively including first and second head portions, and first and second band portions; a first connection terminal having conductive portions disposed on both ends thereof and connected to the first and second band portions, respectively; and a second connection terminal having conductive portions on both ends thereof and connected to the first and second band portions, respectively. The second connection terminal is spaced apart from the first connection terminal in a direction connecting the fifth and sixth surfaces.

Abstract: A device comprising: a substrate; a semiconductor die mounted on the substrate; a transmit antenna fabricated on the substrate and configured to transmit radio-frequency (RF) signals at least at a first center frequency; a receive antenna fabricated on the substrate and configured to receive RF signals at least at a second center frequency different than the first center frequency; and circuitry integrated with the semiconductor die and configured to provide RF signals to the transmit antenna and to receive RF signals from the receive antenna.

Abstract: A multi-layer ceramic electronic component includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a first direction, internal electrodes disposed between the ceramic layers, a main surface that faces in the first direction, and a side surface that faces in a second direction orthogonal to the first direction, the internal electrodes being exposed from the side surface. The side margin includes a side-surface-covering portion that is disposed on the side surface, and an end portion that includes an extended portion extending from the side surface to the main surface and having a first dimension of 0.1 ?m or more in the first direction and a second dimension of 0.1 ?m or more in the second direction.

Abstract: An acoustic wave device includes: a first substrate that has a first surface and a second surface, the second surface being an opposite surface of the first substrate from the first surface; an acoustic wave element that is located on the first surface; a wiring portion that electrically connects the acoustic wave element and a metal portion through a through hole, the metal portion being located on the second surface, the through hole penetrating through the first substrate; and a sealing portion that is located on the first surface so as to surround the acoustic wave element, overlaps with at least a part of the through hole in plan view, and seals the acoustic wave element in an air gap.

Abstract: Provided is a method of manufacturing a component carrier that includes forming a magnetic core on a base structure; forming a through hole in at least one dielectric layer; forming a plurality of electrically conductive windings on the at least one dielectric layer around the through hole; forming a stack with the base structure having the magnetic core, the at least one dielectric layer and another base structure such that the magnetic core is inserted into the through hole and the conductive windings are arranged around the magnetic core such that the magnetic core and the plurality of electrically conductive windings are interposed between the base structure and the other base structure.

Abstract: Implementations of semiconductor packages may include: a substrate having a first side and a second side and a die having an active area on a second side of the die. A first side of the die may be coupled to the second side of the substrate. The semiconductor package may also include a glass lid having a first side and a second side. The glass lid may be coupled over a second side of the die. The semiconductor package may include a first and a second molding compound and one or more cushions positioned between a first side of the glass lid and a portion of the first molding compound. The second molding compound may be coupled to the substrate and the around the die and the glass lid.

Abstract: A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a first component embedded in the stack, having at least one first pad on a bottom surface of the first component. The at least one first pad is electrically connected with a bottom surface of the stack. A second component embedded in the stack, having at least one second pad on a top surface of the second component. The at least one second pad is electrically connected with a top surface of the stack. The stack includes a first redistribution structure electrically connecting the at least one first pad of the first component with the bottom surface of the stack, and a second redistribution structure electrically connecting the at least one second pad of the second component with the top surface of the stack.

Abstract: In a copper-ceramic bonded body of the present invention, at a bonding interface of a copper member and a ceramic member, there are formed a nitride compound layer containing one or more nitride forming elements selected from Ti, Nb, Hf, and Zr, and an Ag—Cu eutectic layer, in order from the ceramic member side, the thickness of the nitride compound layer is 0.15 ?m or more and 1.0 ?m or less, an intermetallic compound phase formed of an intermetallic compound that contains the nitride forming element and Si is present between the copper member and the ceramic member, and Cu and Si are present at the grain boundary of the nitride compound layer.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

Abstract: A capacitor component includes a body including dielectric layers and first and second internal electrodes disposed to face each other while having the dielectric layer interposed therebetween; and first and second external electrodes disposed on an external surface of the body and electrically connected to the first and second internal electrodes, respectively. The body includes a capacitance forming portion including the first and second internal electrodes disposed to face each other while having the dielectric layer interposed therebetween and in which capacitance is formed, and cover portions formed on upper and lower surfaces of the capacitance forming portion, and hardness of the cover portions is 9.5 GPa or more and 14 GPa or less.

Abstract: A multilayer electronic component includes a capacitor body including a plurality of dielectric layers and a plurality of first and second internal electrodes, and having first to sixth surfaces; first and second external electrodes including first and second connection portions and first and second band portions, respectively; and first and second connection terminals disposed on the first and second band portions on the first surface of the capacitor body. The first and second connection terminals are each provided with a solder receiving portion to have a symmetrical shape in a direction connecting the third and fourth surfaces and a direction connecting the fifth and sixth surfaces.

Abstract: A composite electronic component includes a multilayer ceramic capacitor including a ceramic body configured by stacking a plurality of dielectric layers and configured by stacking a plurality of internal electrodes facing each other with the dielectric layer interposed therebetween and first and second external electrodes disposed on opposing end portions of the ceramic body, and a pair of substrates spaced apart from a lower portion of the multilayer ceramic capacitor and each including, on opposing end portions, first terminal electrodes connected to the first external electrode and second terminal electrodes connected to the second external electrode.

Abstract: In one embodiment, an apparatus generally comprises a power delivery board for integration with a printed circuit board, the power delivery board comprising a power plane for delivering power from a voltage regulator module to an application specific integrated circuit (ASIC) mounted on a first side of the printed circuit board. The power plane in the power delivery board interconnects with power vias in the power delivery board for vertical alignment with the ASIC through power vias in the printed circuit board to electrically couple the voltage regulator module and the ASIC when the power delivery board is mounted on a second side of the printed circuit board.

Abstract: The present disclosure describes expansion card interfaces for a printed circuit board and methods of making the same. The methods include forming electrical pads of the expansion card interface on a substrate, and dividing at least one electrical pad into a first portion and a second portion. The resulting expansion card interfaces have the first portion conductively coupled to a circuit on the printed circuit board, and the second portion conductively isolated from the first portion.

Abstract: A chip package includes a circuit board, a chip and an underfill. A solder resist layer formed on the circuit board is modified in edge profile so as to reduce required amount of the underfill. The fewer underfill is still enough to be filled between the circuit board and the chip, and still can cover circuit lines that are not covered by the solder resist layer to protect the circuit lines from oxidation.

Abstract: A multi-piece wiring substrate includes a matrix substrate including a first main surface, a second main surface opposite to the first main surface, a third main surface disposed between the first main surface and the second main surface, an arrangement of a plurality of wiring substrate regions, a margin region surrounding the plurality of wiring substrate regions, and a dividing groove. The multi-piece wiring substrate further includes a through-hole disposed across the boundary between the wiring substrate regions or the boundary between the wiring substrate regions and the margin region, and which penetrates from the first main surface to the second main surface, and an external connection conductor at each corner of the wiring substrate regions on the second main surface. An auxiliary conductor is disposed around the through-hole on the third main surface.

Abstract: A multilayer ceramic electronic component includes a multilayer ceramic electronic component including a ceramic body including a dielectric layer, and a first internal electrode and a second internal electrode facing each other with the dielectric layer interposed therebetween, and first and second external electrodes respectively electrically connected to the first and second internal electrodes, disposed in an outer portion of the ceramic body. The first and second external electrodes include a first electrode layer including a conductive metal, a first plating layer disposed on the first electrode layer and including nickel (Ni), and a second plating layer disposed on the first plating layer and including tin (Sn). A ratio (t1/t2) between a thickness (t1) of the first plating layer including nickel (Ni) and a thickness (t2) of the second plating layer including tin (Sn) is within a range from 1.0 to 9.0.

Abstract: The present invention relates to a carrier (2) with a passive cooling function for a semiconductor component (3), having a main body (6) with a top side (7) and a bottom side (8) and at least one electrical component (13, 13a, 13b) that is embedded in the main body (6), wherein the carrier (2) has a first thermal via (14), which extends from the top side (7) of the main body (6) to the at least one electrical component (13, 13a, 13b), wherein the carrier (2) has a second thermal via (15), which extends from the at least one electrical component (13, 13a, 13b) to the bottom side (8) of the main body (6), and wherein the at least one embedded electrical component (13, 13a, 13b) is electrically contacted by the first and the second thermal via (14, 15).

Abstract: A solid-state drive (SSD) heat dissipation device is disclosed. The SSD heat dissipation device comprises a solid-state drive substrate, a chip heat dissipation component, a memory heat dissipation component, and a spacer. A control IC and a flash memory are disposed on the solid-state drive substrate, the chip heat dissipation component is disposed on the control IC, and the memory heat dissipation component is disposed on the flash memory. The chip heat dissipation component and the memory heat dissipation component are disposed separately.

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

Abstract: A display device includes a first panel including a pad side area at one side of the first panel, a first optically transparent adhesive member on one surface of the first panel, a printed circuit board including a first attachment portion attached to the one surface of the first panel at the pad side area, a window on the first optically transparent adhesive member, a second optically transparent adhesive member on the other surface of the first panel, and a second panel on the second optically transparent adhesive member opposite the first panel, wherein the pad side area has a connection area at which the printed circuit board is attached to the first panel, and at which an edge of the first optically transparent adhesive member extends beyond an edge of the second optically transparent adhesive member, and a non-connection area at which the printed circuit board is not attached.

Abstract: A multilayer ceramic capacitor includes: a multilayer structure in which dielectric layers and internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer structure; and a first cover layer and a second cover layer that sandwich the multilayer structure, a main component of the first cover layer and the second cover layer being the same as that of the dielectric layers, wherein the first cover layer is thicker than the second cover layer, wherein a concentration of Mn of at least a part of the first cover layer is higher than a concentration of Mn of the dielectric layers in an effective capacity region in which a set of internal electrode layers exposed to a first edge face of the multilayer structure face with another set of internal electrode layers exposed to a second edge face of the multilayer structure.

Abstract: A substrate-embedded electronic component includes a first core layer, a first through-portion penetrating the first core layer, a first electronic component disposed in the first through-portion, an encapsulant disposed in at least a portion of the first through-portion, and covering at least a portion of the first electronic component, a second core layer disposed on the encapsulant, and a first through-via penetrating the second core layer, wherein the first through-via is connected to the first electronic component.

Abstract: An assembly for connecting controlled-impedance cables to a PCB using a crescent-shaped connector that can be located much closer to the unit under test than those of the prior art. On the PCB, equal-length signal traces run from UUT contacts to signal pads that form an arc. All signal pads are surrounded by a ground land. The connector has an anchor block for permanently or removably securing the cables. The connector uses skewed coil contacts held within an electrically conductive plate. The signal contacts are captured in signal through apertures within insulating plugs in the plate. The ground contacts are captured in a ground through apertures. Each signal contact is electrically connected to a cable signal conductor and the ground contacts are electrically connected to the anchor block or ferrule. The connector is shaped so that the signal contacts trace an arc, so that they align with the signal pads.

Abstract: A multilayer ceramic electronic component includes a ceramic body having at least one rounded corner, and including dielectric layers and first and second internal electrodes laminated with respective dielectric layers interposed therebetween, and first and second external electrodes, electrically connected to corresponding internal electrodes, respectively. The first and second external electrodes include first and second base electrode layers, each having at least a portion in contact with first and second external surfaces of the ceramic body, first and second conductive resin layers disposed to cover the first and second base electrode layers, respectively, and first and second plating layers disposed to cover the first and second conductive resin layers, respectively.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric and an internal electrode, an electrode layer eletrically connected to the internal electrode, and a conductive resin layer disposed on the electrode layer and including a conductive metal, a graphene platelet, and a base resin.

Abstract: Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other.

Abstract: A (meth)acrylic conductive material which contains a (meth)acrylic elastomer and a conductive agent, and which is characterized in that: the (meth)acrylic elastomer is obtained by polymerizing a monomer component containing a (meth)acrylic monomer represented by formula (I) (wherein R1 represents a hydrogen atom or a methyl group; and R2 represents an alkyl group having 1-10 carbon atoms, which may have a hydroxyl group or a halogen atom, or an alkoxyalkyl group having 2-12 carbon atoms, which may have a hydroxyl group); and the (meth)acrylic elastomer has a weight average molecular weight of 1,200,000 to 10,000,000 and a molecular weight distribution (weight average molecular weight/number average molecular weight) of 1-6.

Abstract: A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board.

Abstract: A capacitor component includes a humidity resistant layer formed on a portion of the external surface of a body on which an external electrode is not formed, and further includes a humidity resistant layer disposed inside the external electrode, to improve humidity resistance reliability. The capacitor component includes an opening portion formed by removing a portion of the humidity resistant layer disposed inside the external electrode to improve electrical connection.

Abstract: An electronic component includes a multilayer capacitor comprising a capacitor body, and an external electrode disposed on an end of the capacitor body, and an interposer comprising an interposer body, and an external terminal disposed on an end of the interposer body. The external terminal includes a connection portion disposed on a first surface of the interposer body and connected to the external electrode, a mounting portion disposed on a second surface of the interposer body opposing the first surface, and a side connection portion disposed on the first and second surfaces and a side surface of the interposer to connect the connection portion and the mounting portion. The side connection portion includes a cutting portion.

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Abstract: A multilayer electronic component includes: a capacitor body including first and second internal electrodes disposed to be alternately exposed through opposite surfaces, respectively, with respective dielectric layers interposed therebetween; first and second thin film layers including at least one of titanium nitride (TiN), ruthenium (Ru), platinum (Pt), iridium (Ir), or titanium (Ti), disposed on the surfaces of the capacitor body, and connected to the first and second internal electrodes, respectively; and first and second external electrodes formed on the first and second thin film layers. A thickness of the first or second thin film layer is less than or equal to 60 nm.

Abstract: An electronic device module includes: a substrate; at least one electronic device mounted on a first surface of the substrate; a connection portion mounted on the first surface of the substrate; and a shielding portion disposed along an external surface of the connection portion and electrically connected to a ground of the substrate through at least one connection conductor.

Abstract: Provided is a printed wiring board comprising: a substrate; a conductive layer including a land and a wiring and formed on a surface of the substrate, the wiring having a width smaller than the land and drawn from the land; and an insulating layer formed on the conductive layer. The insulating layer has an opening corresponding to a position of the land, and an edge of the opening runs above the land and above one of edges in a width direction of the wiring.

Abstract: A multilayer ceramic electronic device includes a pair of external electrodes respectively covering end surfaces of a main body, wherein a height of the multilayer ceramic electronic device that includes the pair of eternal electrodes is greater than 0.80 times and less than 1.25 times as much as the lessor of a width dimension of the electronic device and a length dimension of the electronic device, and wherein each of the pair of external electrodes includes a tin plating film as an outermost layer, and a thickness of the tin plating film on the end surface of the main body is smaller than a thickness of the tin plating film on side surfaces of the main body.

Abstract: A processor comprising an ALU a programmable function unit wherein the functional unit may be programmed to comprise multistage logic.

Abstract: A ceramic electronic part which includes a ceramic part body substantially in a parallelepiped form and having a first outer electrode at one end portion thereof and a second outer electrode at an opposite end portion thereof. The first outer electrode contiguously includes a main part provided on one surface in the third direction of the ceramic part body and a sub part provided on one surface in the first direction of the ceramic part body, and the second outer electrode contiguously includes a main part provided on one surface in the third direction of the ceramic part body and a sub part provided on an other surface in the first direction of the ceramic part body. The ceramic electronic part suffers warpage causing first and second maximum gaps to occur between centers in the second direction of the main parts of the outer electrodes and a virtual plane.

Abstract: In large area plasma processing systems, process gases may be introduced to the chamber via the showerhead assembly which may be driven as an RF electrode. The gas feed tube, which is grounded, is electrically isolated from the showerhead. The gas feed tube may provide not only process gases, but also cleaning gases from a remote plasma source to the process chamber. The inside of the gas feed tube may remain at either a low RF field or a zero RF field to avoid premature gas breakdown within the gas feed tube that may lead to parasitic plasma formation between the gas source and the showerhead. By feeding the gas through an RF choke, the RF field and the processing gas may be introduced to the processing chamber through a common location and thus simplify the chamber design.

Abstract: A package carrier includes a plurality of first circuit patterns, a plurality of second circuit patterns and an insulating material layer. The second circuit patterns are disposed between any two the first circuit patterns and are directly connected to the first circuit patterns. In a cross-sectional view, a first thickness of each of the first circuit patterns is greater than a second thickness of each of the second circuit patterns. A first surface of each of the first circuit patterns is aligned with a second surface of each of the second circuit patterns. The insulating material layer at least contacts the first circuit patterns.

Abstract: A printed circuit board (PCB) with at least one mechanical stress relief zone and at least one electrical component zone, wherein the at least one mechanical stress relief zone allows the PCB to flex proximate the at least one mechanical stress relief zone of the PCB without compromising the at least one electrical component zone.

Abstract: A package structure is provided. The package structure includes a redistribution layer and a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer. The package structure also includes first bumps electrically connected to the first integrated circuit chip through the redistribution layer. In addition, the first bumps overlap the first integrated circuit chip and are arranged along a first chip edge of the first integrated circuit chip. The package structure further includes second bumps electrically connected to the first integrated circuit chip through the redistribution layer without overlapping the first integrated circuit chip and the second integrated circuit chip. In addition, none of the second bumps is arranged between the first chip edge and the second chip edge.

Abstract: A display panel including a first array substrate, a first pad, and a second pad is provided. The first array substrate includes a first substrate, a first active element, a first display element, and a second display element. The first substrate has a top surface and a bottom surface disposed opposite to each other. The first active element is disposed on the top surface of the first substrate. The first display element is disposed on the top surface of the first substrate and is electrically connected to the first active element. The second display element is disposed on the top surface of the first substrate and is disposed separately from the first display element.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface disposed to oppose each other and including an insulating member having a plurality of insulating layers and a plurality of redistribution layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one of the plurality of redistribution layers includes a dummy electrode pattern in which a plurality of holes are arranged, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude externally from different positions.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and first and second internal electrodes which face each other with the dielectric layer interposed therebetween. The first and second internal electrodes include a conductive metal and an additive. In a cross-section of the ceramic body in the length-thickness (L-T) plane, a ratio of content of the additive in the first and second internal electrodes in upper and lower portions of the ceramic body to a content of the additive in the first and second internal electrodes in a central portion of the ceramic body is around 0.63 to around 1.03.

Abstract: A high-frequency board includes an insulating substrate, a first line conductor, and a second line conductor. The insulating substrate has an upper surface with a recess. The first line conductor is located on the upper surface of the insulating substrate. The second line conductor is located on the upper surface of the insulating substrate and extends parallel to the first line conductor with a space from the first line conductor as viewed from above. The recess is located between the first line conductor and the second line conductor, and has a lower dielectric constant than the insulating substrate.

Abstract: A circuit board comprising a first sub-circuit board, a second sub-circuit board, and a circuit connection structure. The first and second sub-circuit board having a first and second connection terminal, respectively. The circuit connection structure has a first port for mating with the first connection terminal, and a second port for mating with the second connection terminal. The first connection terminal, the second connection terminal, the first port, and the second port are configured such that when the first sub-circuit board is connected to the second sub-circuit board through the circuit connection structure, a first connection terminal end face faces the first port in a first direction, and a second connection terminal end face faces the second port in a second direction, and an angle between the first direction and the second direction is greater than 90° and less than or equal to 180°.