Abstract: A multilayer ceramic electronic component includes a ceramic body, and first and second external electrodes disposed on the surface of the ceramic body, respectively. The ceramic body includes a capacitance forming portion including a dielectric layer and internal electrodes, margin portions disposed on both sides of the capacitance forming portion, and cover portions disposed on both sides of the capacitance forming portion. The first and second external electrodes include first and second base electrodes, respectively, first and second conductive layers disposed on edges of the first and second base electrodes, respectively, and first and second terminal electrodes covering the first and second base electrodes, respectively.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and an internal electrode and an external electrode disposed on an exterior of the body. The external electrode includes an electrode layer connected to the internal electrode and a plating portion including a nickel (Ni) plating layer, a nickel-tin (Ni—Sn) intermetallic compound layer, and a tin (Sn) plating layer, sequentially disposed on the electrode layer. The Ni—Sn intermetallic compound layer has a thickness of 0.1 ?m or more.

Abstract: An electronic component includes a capacitor body having first to sixth surfaces, and including a plurality of dielectric layers and first and second internal electrodes; first and second external electrodes disposed on both ends of the capacitor body in a second direction in which the third and fourth surfaces oppose each other, respectively; a third external electrode disposed on the first surface of the capacitor body; and first to third metal frames connected to the first to third external electrodes, respectively, both ends of the first internal electrode are exposed through the third and fourth surfaces of the capacitor body, respectively, and the second internal electrode includes a lead portion exposed through the first surface of the capacitor body and connected to the third external electrode.

Abstract: A vertically structured pad system and method can include: a platform having etch attributes, a platform top surface, and a platform side surface; a structure on the platform, the structure including a structure side surface extended up from the platform top surface terminating in a structure top surface, the structure including a structure interior surface defining a cavity within the structure, and the platform top surface exposed from within the cavity; and an interconnect structure adhered to the platform and the structure, the interconnect structure conforming with an exterior shape of the platform side surface in combination with the structure for locking the interconnect structure onto the platform and the structure.

Abstract: An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.

Abstract: An inductor built-in substrate includes a core substrate having an opening and a first through hole formed therein, a magnetic resin filling the opening and having a second through hole formed therein, a first through-hole conductor including a metal film formed in the first through hole, and a second through-hole conductor including a metal film formed in the second through hole. The core substrate and the magnetic resin are formed such that a surface in the first through hole has a roughness that is larger than a roughness of a surface in the second through hole.

Abstract: An electronic component includes a multilayer capacitor and an interposer. First and second internal electrodes of the multilayer capacitor are such that 0.95?{(Wm1+Wm2)/Wa}/{(Lm1+Lm2)/La}?4.93, in which Lm2 is a distance between a first internal electrode and a fourth surface of a capacitor body, Lm1 is a distance between a second internal electrode and a third surface of the capacitor body opposite the fourth surface in a first direction, Wm1 is a distance between the first or second internal electrode and a second surface of the capacitor body, Wm2 is a distance between the first or second internal electrode and a first surface of the capacitor body opposite the second surface in a third direction, La is a length in the first direction of a region of overlap of the first and second internal electrodes, and Wa is a length in the third direction of the region of overlap.

Abstract: The various embodiments of the present disclosure are directed to devices, systems and methods for mitigating fault propagation between two or more safety components. A system, for avoiding propagation of a fault between two or more safety components may include a control unit outputting an input signal, a first safety component electrically coupled to receive the input signal from the control unit; a second safety component electrically coupled to receive the input signal from the control unit; and a first isolating component electrically disposed between and further coupling the control unit with the first safety component. Each of the first safety component and the second safety component are electrically coupled to the control unit by at least a common lead. The first isolating component prevents a first IC fault arising with respect to the first safety component from propagating, via the input signal, to the second safety component.

Abstract: An electronic component and a board having the same mounted thereon are provided. The electronic component includes: a body; an electrode disposed on an end of the body in a first direction; a metal frame including a support layer bonded to the external electrode, a mounting portion extending in the first direction in a lower end of the support layer and having a protruding portion on a lower surface, and a coating film formed to cover an upper surface of the protruding portion on an upper surface of the mounting portion and including titanium (Ti).

Abstract: A wiring circuit board includes an insulating layer and a conductive layer disposed on a front surface of the insulating layer. The conductive layer includes a first wiring, a first terminal electrically connected to the first wiring, a second wiring independent of the first wiring and having a thick thickness T2 with respect to a thickness T1 of the first wiring, and a second terminal electrically connected to the second wiring. The surfaces of the first terminal and the second terminal are disposed at generally the same position in a thickness direction.

Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and first and second internal electrodes stacked with the dielectric layer interposed therebetween, and having first and second external electrodes disposed on the ceramic body and connected to the first and second internal electrodes, respectively. The first external electrode includes a first electrode portion and a first band portion, and the second external electrode comprises a second electrode portion and a second band portion. A length of the ceramic body in a first direction is L, a width thereof in a second direction is W, a length of the first and second electrode portions in the first direction is BW, a width of the first or second band portion in the second direction is SW, a ratio SW/W is less than 0.46, and a ratio BW/L exceeds 0.10.

Abstract: A substrate with an electronic component embedded therein includes a core substrate including an insulating body having a first surface and a second surface, opposite to the first surface, a first wiring layer embedded in the insulating body such that one surface thereof is exposed from the first surface, and a second wiring layer disposed on the insulating body to protrude on the second surface, the core substrate having a cavity penetrating a portion of the insulating body from the first surface toward the second surface and having a stopper layer as a bottom surface thereof; an electronic component disposed on the stopper layer in the cavity; a first insulating material covering at least a portion of each of the core substrate and the electronic component; and a third wiring layer disposed on the first insulating material.

Abstract: A display apparatus includes a base substrate, a plurality of data lines disposed in a display area on the base substrate, wherein at least a portion of the data lines extend to a first peripheral area adjacent to the display area, a plurality of detour lines disposed in the display area, wherein at least a portion of the detour lines extend to the first peripheral area, and a data driver electrically connected to the data lines and the detour lines, wherein at least one of the data lines electrically contacts at least one of the detour lines in the first peripheral area.

Abstract: A display device including a substrate including a display area and a non-display area, a plurality of signal lines disposed in the display area and extending along a first direction and from the non-display area to the display area, a connection line extending from the non-display area and electrically connected to a respective signal line of the plurality of signal lines in the non-display area, and an initialization voltage line extending in a second direction intersecting the first direction, wherein the connection line overlaps the initialization voltage line in a thickness direction of the display device.

Abstract: A resin multilayer board includes an insulating substrate including a first main surface and mounting electrodes only on the first main surface. The insulating substrate includes first and second resin layers that are laminated. The Young's modulus of the second resin layers is higher than that of the first resin layers. The first and second resin layers are arranged in a distributed manner along a lamination direction of the first and second resin layers. The insulating substrate includes a first and second portions that are two equally divided portions of the insulating substrate in the lamination direction and are respectively positioned closer to the first main surface and farther from the first main surface, and a volume ratio of the second resin layers in the first portion is higher than a volume ratio of the second resin layers in the second portion.

Abstract: A method of manufacturing a multilayer ceramic capacitor includes forming a water-repellent coating layer on surfaces of a multilayer ceramic capacitor having an internal electrode, a dielectric layer, and an external electrode; and removing at least a portion of the water-repellent coating layer formed on the surfaces of the external electrode such that another portion of the water-repellent coating layer remains on surfaces of the dielectric layer. The external electrode has first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a length direction.

Abstract: A flexible printed circuit board and an electronic device using the same are provided. The electronic device includes a first casing, a second casing, and a printed circuit board combination. The printed circuit board combination includes a first printed circuit board, a second printed circuit board, and a flexible printed circuit board. The flexible printed circuit board includes a body portion, a first extending end, and a second extending end. The body portion defines an opening. The first extending end bends from a first side of the body portion toward the body portion and extends toward a first direction after passing through the opening to connect the first printed circuit board. The second extending end extends from a second side of the body portion toward a second direction to connect the second printed circuit board.

Abstract: A semiconductor package includes a first substrate having a first surface and including a first electrode, a first bump pad located on the first surface of the first substrate and connected to the first electrode, a second substrate having a second surface facing the first surface of the first substrate and including a second electrode, a second bump pad and neighboring second bump pads on the second surface of the second substrate, and a bump structure. The second bump pad has a recess structure. That is recessed from a side surface of the second bump pad toward a center thereof. The second bump pad may be connected to the second electrode. A bump structure may contact the first bump pad and the second bump pad. The bump structure may have a portion protruding through the recess structure. The neighboring second bump pads may neighbor the second bump pad and include recess structures oriented in different directions.

Abstract: Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

Abstract: A display device is provided and includes a display panel and a flexible printed wiring substrate. The display panel is provided with a binding structure. The binding structure includes a plurality of first connection terminals arranged along a width direction of the display panel; and a flexible printed wiring substrate is electrically connected to the bonding structure of the display panel. Each of the first connection terminals is obliquely disposed along a lateral edge of the width direction of the display panel, and adjacent lateral edges of two of the adjacent first connection terminals along the width direction of the display panel are parallel to each other.

Abstract: A module. In some embodiments, the module includes a substrate; a plurality of electronic components, secured to an upper surface of the substrate; a thermally conductive heat spreader, on the electronic components and in thermal contact with an electronic component of the plurality of electronic components; a standoff, between the substrate and the heat spreader; an alignment element, extending into the substrate; a hard stop, under the substrate; and a plurality of compressible interconnects, under the substrate, and extending through the hard stop. The electronic components may be within a sight area of the substrate. The module may be configured to transmit a compressive load from an upper surface of the standoff to a lower surface of the substrate through a load path not including any of the electronic components.

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

Abstract: The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.

Abstract: A multichip module provided with a first substrate, a first semiconductor chip, a second substrate and a third substrate. The first semiconductor chip has a first surface provided with a first electrode and a second surface mounted on the first substrate so that the first wiring of a first mount surface of the first substrate is electrically connected to the first electrode. The second substrate has a second mounting surface and a third mounting surface bonded to the first substrate so that the second mounting surface is opposed to the first mounting surface. The third substrate has a fourth mounting surface provided with a second wiring and a fifth mounting surface bonded to the second silicon substrate so that the fourth mounting surface is opposed to the third mounting surface and is mounted with the first semiconductor chip so that the second wiring is electrically connected to the second surface.

Abstract: A multi-layer ceramic electronic component includes a ceramic body and an external electrode, the ceramic body including a protective portion and a functional portion, the protective portion including an end surface facing in a first direction, circumferential surfaces connected to the end surface and extending in the first direction, and a ridge that includes a recess extending along the first direction and connects the circumferential surfaces, the functional portion being disposed inside the protective portion, the external electrode including a base film covering the end surface, and a plating film formed on the base film, the base film including a first covering portion formed on the end surface, second covering portions formed on the circumferential surfaces, and a third covering portion formed on the recess and spaced apart from at least one second covering portion, the plating film continuously covering the first, second, and third covering portions.

Abstract: An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.

Abstract: A ceramic electronic device includes: a multilayer chip including a multilayer structure and cover layers, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic, the cover layers being provided on an upper face and a lower face of the multilayer structure in a stacking direction; and a pair of external electrodes that are formed on the two edge faces, wherein each of the external electrodes has a smaller thickness on a corner portion of the cover layers, has a crook toward the internal electrode layers, and has a larger thickness on an area of the two edge faces where the internal electrode layers are extracted.

Abstract: A fingerprint identification module and a terminal device are provided. The fingerprint identification module includes: a decorative ring, provided with a mounting opening; an encapsulation cover, arranged on the decorative ring to close a side of the mounting opening; a fingerprint chip, disposed in the mounting opening, a space is formed between an outer side surface of the fingerprint chip and an inner wall surface of the decorative ring; a protective film, disposed on a side of the fingerprint chip that is towards the encapsulation cover; and a flexible printed circuit (FPC) board, disposed inside the mounting opening, the protective film covers a first partial area of the FPC board, and a second partial area of the FPC board is exposed out of the protective film; the second partial area is an area of the FPC board which is different from the first partial area of the FPC board.

Abstract: A connector device that includes a circuit board; a connector attached to the circuit board; a plurality of collars for external attachment; a first molded resin that is made of a first resin material whose melting point or softening point is 230° C. or less, and covers the entire circuit board and part of the connector; and a second molded resin that is welded to the first molded resin, is made of a second resin material whose melting point or softening point is higher than that of the first resin material for the first molded resin, and covers outer circumferences of the collars.

Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and an external electrode. A cover portion of the body has curved corners, and a radius of curvature, R, of each of the curved corners and a thickness, T, of the body satisfy a condition of 10 ?m?R?T/3, and a width, W, and a thickness, T, of the body satisfy a condition of T/W<0.8.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

Abstract: An electronic component includes: a capacitor body; first and second external electrodes disposed on both ends of the capacitor body in a length direction; and first and second connection terminals disposed on a mounting surface of the capacitor body and electrically connected to the first and second external electrodes, respectively, and having first and second cut portions on surfaces facing each other in the length direction of the capacitor body, respectively.

Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.

Abstract: An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

Abstract: A thin film video device is mounted onto a card stock and incorporated into a card, such as a greeting card. The thin film video device comprises a thin film video display coupled to a computer chip and a speaker. The thin film video device is powered by a local power source such as a small battery. The thin film video device is activated when the user unfolds the card, at which time an audiovisual message is displayed on the thin film video display and through the speaker.

Abstract: A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component which is embedded in the stack and a stabilizing structure arranged between a stack surface of the stack and a main surface of the component. The stabilizing structure provides an interface adhesion to the main surface of the component.

Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.

Abstract: Described are processes for developing laminated circuit boards, as well as the resulting circuit boards themselves. Accordingly, at least two circuit boards at least partially overlap each other, and at least one through-hole is formed in an overlapping region thereof. The through-hole is filled with an electrically-conductive material, forming a through-via that enables the circuit boards to be electrically connected. When a circuit on each circuit board is laid out so that a part thereof reaches a region in which the through-via is to be formed, then that part of the circuit can be electrically connected to the through-via. Thus, portions of the circuits on the circuit boards can be electrically connected to each other via common through-vias to realize an integrated device in which the circuits on the laminated circuit boards function.

Abstract: A line length between an input end of a switching circuit and a high frequency capacitor is shorter than a line length between an output end of a DC power supply and the high frequency capacitor. A current path going through the switching circuit and the high frequency capacitor is the shortest among a plurality of current paths through which a switching current is caused to flow by switching at the switching circuit. Furthermore, the high frequency capacitor makes the ratio of time during which the voltage across the high-side switch element changes by a switching operation of the high-side switch element and the ratio of time during which the voltage across the low-side switch element changes by a switching operation of the low-side switch element the same, and thus reduces a harmonic wave current included in a current output from the high frequency power generation circuit.

Abstract: At least one redistribution layer (RDL) is provided on a silicon die. A passivation layer is deposited on the RDL. First openings having a first diameter are etched in the passivation layer where copper posts are to be formed. A seed layer is deposited over the passivation layer and within the openings. A photoresist layer is coated on the seed layer and patterned to form second openings having a second diameter over the first openings larger than the first diameter. Copper is plated on the seed layer to form copper posts filling the second openings. The silicon die is die attached to a metal substrate. A lamination layer is coated over the silicon die and the copper posts. Third openings are formed through the lamination layer to the copper posts and to metal pads on the metal substrate. Metal vias are formed in the third openings.

Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate layers, second conductor layers including second inner, outer and intermediate layers, interlayer insulating layers interposed between the first conductor layers and between the second conductor layers, and via conductors formed in the insulating layers such that each via conductor connects two conductor layers and is integrally formed with one of the conductor layers on side away from the core layer. The first and/or second inner conductor layers has a first conductor layer structure including metal foil and plating film layers, the first and/or second outer conductor layers has the first structure, the first and/or second intermediate conductor layers has a second conductor layer structure including metal foil and plating film layers, and the via conductors include a group integrally formed with the first structure and including constricted via conductors each having a constricted portion.

Abstract: A component carrier with a stack having at least one electrically conductive layer structure and a plurality of electrically insulating layer structures and a component embedded in the stack. The plurality of electrically insulating layer structures include a first dielectric structure and a second dielectric structure differing concerning at least one physical property.

Abstract: A capacitor component includes a body having a first surface and a second surface opposing each other and including a multilayer structure in which a plurality of dielectric layers are stacked and first and second internal electrodes are alternately disposed with respective dielectric layers interposed therebetween and exposed to the first surface and the second surface, respectively, first and second metal layers covering the first surface and the second surface and connected to the first and second internal electrodes, respectively, first and second ceramic layers covering the first and second metal layers, and first and second external electrodes covering the first and second ceramic layers and connected to the first and second metal layers to be electrically connected to the first and second internal electrodes, respectively.

Abstract: A substrate includes primary side terminal holes into which the primary side terminals are inserted, secondary side terminal holes into which the secondary side terminals are inserted, and a slit disposed between the primary side terminal holes and the secondary side terminal holes. A transformer is mounted from the side of a mounting surface of the substrate. An insulating member is inserted into the slit from the side of a soldering surface of the substrate. The insulating member includes a protrusion portion that protrudes outside an area defined by virtual lines which are direct extension lines of the width of the slit to the side of the soldering surface. The protrusion portion is formed at a position more distant from the substrate than an end position of the shortest terminal of the primary side terminals and the secondary side terminals from the soldering surface of the substrate.

Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.

Abstract: A multilayer capacitor includes a body including a stacked structure of a plurality of dielectric layers and a plurality of internal electrodes, wherein, in the body, corners of cover portions are formed as curved surfaces, and 10 ?m?R?T/4 in which R is a radius of curvature of the curved surface corners and T is a thickness of the body, and 0.8?Tg/Wg?1.2 in which Wg is a margin of the body in a width direction, and Tg is a margin of the body in a thickness direction.

Abstract: The present disclosure is directed to a micro module with a support structure. The micro module includes a carrier substrate having contacts and a bonding pad, a semiconductor die, and a support structure. The semiconductor die is positioned on the bonding pad and is electrically coupled to the contacts. The support structure is positioned on the bonding pad and adjacent to the semiconductor die. The support structure reinforces the bonding pad such that the bonding pad is more rigid than flexible. As a result, an external force applied to the micro module is less likely to cause the micro module to bend and damage the semiconductor die.

Abstract: A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP1. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP2, and LP2>LP1. The package system includes a first integrated circuit over the first interposer.