Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.

Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Abstract: A wired circuit board includes a metal supporting layer, an insulating base layer and a conductor layer from bottom to top. A peripheral edge of the insulating base layer includes an extension part extending further outward relative to the metal supporting layer. The metal supporting layer has a thickness T1 of 50 ?m or more.

Abstract: An embedded magnetic component device includes a magnetic core located in a cavity extending into an insulating substrate. The cavity and magnetic core are covered with a cover layer. Through holes extend through the cover layer and the insulating substrate, and are plated to define conductive vias. Metallic traces are provided at exterior surfaces of the cover layer and the insulating substrate to define upper and lower winding layers. The metallic traces and conductive vias define the respective primary and secondary side windings for an embedded transformer. At least a first isolation barrier is provided on the cover layer, and at least a third insulating layer is provided on the substrate. The second and third insulating layers provide additional insulation for the device, and define and function as a circuit board for surface mounted power electronics.

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

Abstract: A antenna assembly includes: a first antenna disposed on the first support provided with a first through hole, wherein the first antenna includes a first part disposed on an upper surface of the first support, a second part disposed inside the first through hole, and a third part disposed on a lower surface of the first support; a first connecting plate, an upper surface of which abuts against the third part, and lower surface is attached to an upper surface of the circuit board; a second connecting plate, an upper surface of which is attached to a lower surface of the circuit board; and a second antenna disposed on a middle frame of the terminal and connected to a lower surface of the second connecting plate, the first antenna being connected to a feed point of the second antenna through the first connecting plate and the second connecting plate.

Abstract: A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure.

Abstract: A method for producing a camera module having a first part, preferably a housing part, and a second part, preferably a circuit board or a cover part, in which the two parts are connected in positive locking fashion. The positive lock is produced in that a connecting element connected to the first part in the form of a tongue, sleeve or a pin is guided through an opening of the second part, the first part is brought to abut on the second part and subsequently the end of the connecting element protruding beyond the second part is curled in a deforming process so that the curled end abuts on the second part in a pretensioned manner. A camera module is also described.

Abstract: A through-hole via penetrating, in a thickness direction, through a circuit board provided with multiple wiring layers in which a conductor pattern is formed on a surface of an insulating layer, wherein the through-hole via has a first through-hole conductor that is disposed inside a hole penetrating through the circuit board and that is formed from a conductor; a second through-hole conductor that is disposed inside the hole so as to be spaced, in a circumferential direction of the hole, from the first through-hole conductor; a first land portion that connects the first through-hole conductor to the conductor pattern on one insulating layer; and a second land portion that connects the first through-hole conductor with the second through-hole conductor on another insulating layer different from the one insulating layer.

Abstract: A printed circuit board includes a layered substrate having a plurality of layers having an electrical connector footprint configured to receive an electrical connector. The printed circuit board includes pair anti-pads passing through the layered substrate around pairs of signal vias. The printed circuit board includes ground vias passing through the layered substrate. The ground vias are configured to receive ground pins of the electrical connector. The ground vias are located outside of the pair anti-pads. The printed circuit board includes SI vias passing through the layered substrate. The SI vias form an SI fence surrounding the corresponding pair anti-pad.

Abstract: The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

Abstract: A display device includes: a panel including a display region and a touch region; and a circuit board, and including a first conductive layer, a second conductive layer and a first insulating layer between the first conductive layer and the second conductive layer. The circuit board includes: a plurality of data lines electrically connected with a plurality of data signal lines; a plurality of touch lines electrically connected with a plurality of touch electrodes; and a first ground line disposed between at least two or more of the plurality of data lines and the plurality of touch lines. The first ground line includes a first part of the first conductive layer, a first part of the second conductive layer, and a first via passing through the first insulating layer and connecting the first part of the first conductive layer with the first part of the second conductive layer.

Abstract: A circuit board may include a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together and a via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the via comprising a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board and a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth.

Abstract: Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.

Abstract: A manufacturing method of a carrier for a semiconductor chip mounting thereon is provided. The method includes at least the following steps. A plurality of conductive connectors is formed on a fine redistribution structure to form a first portion, where the semiconductor chip is adapted to be mounted on the fine redistribution structure opposite to the conductive connectors. Each of the conductive connectors includes a bump and a solder cap formed on the bump, and the bump is directly connected to the fine redistribution structure. The first portion is disposed on a second portion, where the second portion includes a top redistribution structure directly connected to the solder cap and a second redistribution structure connected to the top redistribution structure, the first portion is disposed on the top redistribution structure, and a contact density of the top redistribution structure is denser than a contact density of the bottom redistribution structure.

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.

Abstract: A via hole structure includes: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.

Abstract: Systems and assemblies are provided for exchanged signal routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. Exchanged signal routing techniques involve “exchanging” the signal routing lanes on the PCB, which reduces coupled signal amplitude and phase relationship. Exchanged signal routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. A printed circuit board (PCB) can include an array of contact pads, a plurality of signal lines that include an escape route. One or more exchange junctions disposed within the escape route can route a first signal line of a first routing channel in the escape route into a second routing channel in the escape route.

Abstract: A printed circuit board deformable in both length and width includes a first conductive circuit layer, a second conductive circuit layer, an elastic film, and conductive via holes. The first conductive circuit layer includes first conductive circuits. First honeycomb holes are defined on the first conductive circuits. The second conductive circuit layer faces away from the first conductive circuit layer, the second conductive circuit layer comprises second conductive circuits, second honeycomb holes being defined on the second conductive circuits, each of the second honeycomb holes corresponds to one of the first honeycomb holes. The first conductive circuits are embedded in the elastic film. Each of the conductive via holes corresponds to one first honeycomb holes.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

Abstract: A method of producing a light source device includes providing a light emitting device having a substrate including a base member that includes a bottom surface and a recess. The substrate further including a wiring portion in the recess. The method further including providing a support substrate having a support base member, a first wiring pattern on a top surface of the support base member and including a joining region, and an insulating region, and applying a solder member such that the solder member on the insulating region has a volume larger than that of the solder member on the joining region. The light emitting device is placed on the support substrate while the solder member is separate from a portion of the wiring portion positioned in the vicinity of the bottom surface and the wiring portion is joined to the joining region.

Abstract: A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.

Abstract: An electrical component, such as an RF device or thermal bridge, for use with a printed circuit board. The component has a first dielectric layer having a top and a bottom, a first conductive trace positioned on the bottom of the dielectric layer, and a first ground layer positioned on the bottom of the dielectric layer and spaced apart from the first conductive trace. For RF applications, a second conductive trace is positioned on top of first dielectric, a second dielectric is positioned on top of the second conductive trace, and a second ground plane is positioned on top of the second dielectric. A printed circuit board having a third conductive trace may then be coupled to the first conductive trace by a first solder layer.

Abstract: A wiring board comprising an insulation substrate comprising a main surface and a penetrating portion that has an insulation property; and an external connection conductor, a portion of which is positioned in the insulation substrate and a different portion of which is exposed at the main surface, wherein the penetrating portion penetrates into the external connection conductor.

Abstract: A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

Abstract: Wearable apparatus for monitoring various physiological and environmental factors are provided. Real-time, noninvasive health and environmental monitors include a plurality of compact sensors integrated within small, low-profile devices, such as earpiece modules. Physiological and environmental data is collected and wirelessly transmitted into a wireless network, where the data is stored and/or processed.

Abstract: A carrier for a semiconductor chip mounting thereon and a manufacturing method thereof are provided. The carrier includes a fine redistribution structure, a plurality of conductive connectors, and an insulating layer. The fine redistribution structure has a first surface and a second surface opposite to each other, where the semiconductor chip is mounted on the first surface of the fine redistribution structure. The conductive connectors are disposed on the second surface of the fine redistribution structure and electrically coupled to the semiconductor chip through the fine redistribution structure. The insulating layer is disposed on the second surface of the fine redistribution structure to laterally cover the conductive connectors.

Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.

Abstract: A semiconductor device includes: a sealed unit that seals a semiconductor element therein; a connection terminal that is electrically connected to the semiconductor element and is provided so as to project outward from the sealed unit; and a pedestal that is provided to surround a bottom part of an exposed portion of the connection terminal that is exposed from the sealed unit. The pedestal has a base attached to the sealed unit and a guide part that has an inclined side face.

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.

Abstract: A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad.

Abstract: A conductive terminal includes a holding portion, a positioning portion and a welding portion. The positioning portion is connected to the holding portion and includes two positioning branches separated by a first trench. The welding portion is connected to the positioning portion and the positioning portion is located between the holding portion and the welding portion. The welding portion includes two welding branches separated by a second trench, wherein the first trench is communicated with the second trench and each of the welding branches is connected to one of the positioning branches. The positioning portion has a first outer diameter, and a second outer diameter on at least part of the welding portion is greater than the first outer diameter. An electrical connecting structure is further provided.

Abstract: In at least one illustrative embodiment, a printed circuit board may comprise at least one insulating layer, first and second conductive layers separated from one another by the at least one insulating layer, and a conductive via extending through the at least one insulating layer and electrically coupling the first and second conductive layers. The conductive via may include an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches) and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches).

Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors. A method for improving signal integrity in a computer interconnect can include carrying differential signals on a set of differential signal vias in a connector pinfield; carrying sideband signals on a set of sideband vias in the connector pinfield; and reducing via-to-via crosstalk between a particular one of the sideband vias and one of the differential signal vias through one or more thru-hole ground vias adjacent to the particular sideband via in the pinfield.

Abstract: Provided is a substrate including a first wiring layer, wherein the first wiring layer has a structure in which among a plurality of first connection parts of a plurality of vias, at least one of first connection parts of two vias located closer to both ends of the first wiring layer is coupled to a body of the first wiring layer through a first conductive portion, each of the plurality of first connection parts being coupled to the first wiring layer, and a cross-sectional area of the first conductive portion is less than an area of a first part of the first wiring layer, the first part being in contact with a first connection part of a via other than the first connection parts of the two vias.

Abstract: A burr-suppressing copper foils are described. In an embodiment, the burr suppressing copper foil includes a poly-based film having an adhesive on a first side and an adhesive on a second side. A copper foil contacts the adhesive at the first side of the poly-based film to removably couple the poly-based film to the copper foil. A metallic burr suppressor contacts the adhesive on the second side to removably couple the poly-based film to the metallic burr suppressor.

Abstract: Various examples provide a printed circuit board (PCB) comprising a first route from a first through-hole via to a second through-hole via, and a second route from the second through-hole via to a first microvia (e.g., coupled to a second memory module socket). Additional microvias may have a route from the first microvia that effectively daisy chains the microvias from the second through-hold via. Various examples also provide a PCB comprising a first route from a first through-hole via to a second through-hole via, and a second route from the second through-hole via to a first sequential lamination via. Additional sequential lamination vias may have a route from the first microvia that effectively daisy chains the sequential lamination vias from the second through-hold via.

Abstract: A power line structure, an array substrate including the power line structure and a display panel are provided. The power line structure includes a conductive plate, the conductive plate includes a through hole disposing area, the through hole disposing area is provided with a plurality of via holes; in at least one sub-area of the through hole disposing area, a distribution density of the via holes increases along a direction of decreasing a current density in the conductive plate.

Abstract: A connection structure for a laser and a laser assembly are provided. The connection structure for a laser includes a first insulation substrate, where the first insulation substrate includes a conductive path separately on an upper surface and a lower surface thereof. A second insulation substrate is disposed on the upper surface of the first insulation substrate. An upper surface of the second insulation substrate includes a conductive path. The conductive path on the upper surface of the second insulation substrate is electrically connected to the conductive path on the lower surface of the first insulation substrate via a through-hole. The connection structure for a laser and the laser assembly in the present disclosure are configured to supplying power to a laser.

Abstract: An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.

Abstract: A circuit board includes a flexible wiring board with a reinforcing member. The flexible wiring board has a first, second and third sections. The reinforcing member is embedded in a cavity in the first section of the wiring board, and is sandwiched by a pair of resin layers provided below and above. A pair of wiring layers are disposed on the pair of the resin layers, respectively. The metal reinforcing member has either a plate shape or a frame shape and is disposed closer to one of the pair of the wiring layers than to another of the pair of the wiring layers in a vertical direction.

Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.

Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.

Abstract: A three-dimensional data generation device includes a data division unit, a detection unit, an output command unit, and a data correction unit. The data division unit divides sectional shape data on one layer of a shaped object into mark data for shaping a mark for correction of sectional shape data on a different layer to be output as superposed on the one layer and post-removal data obtained by removing the mark data from the sectional shape data on the one layer. The detection unit detects an amount of misregistration of the mark output using the mark data from a position determined in advance. The output command unit commands output using the post-removal data so as to form the one layer of the shaped object together with the mark. The data correction unit corrects the sectional shape data on the different layer using the amount of misregistration of the detected mark.

Abstract: A quadrature coupler having: a pair of overlying strip conductors separated by a first dielectric layer to provide a coupling region between the coupling region of overlying strip conductors; a pair of opposing ground pads, the coupling region being disposed between the pair of opposing ground pads; a second dielectric layer disposed over the coupling region and between the pair of opposing ground pads; and an electrically conductive shield layer disposed over the second dielectric layer, extending over opposing sides of the dielectric layer and onto the pair of opposing ground pads. Portions of coupler are formed by printing or additive manufacturing.