Hollow (e.g., Plated Cylindrical Hole) Patents (Class 174/266)
  • Patent number: 11404335
    Abstract: A manufacturing method of a carrier for a semiconductor chip mounting thereon is provided. The method includes at least the following steps. A plurality of conductive connectors is formed on a fine redistribution structure to form a first portion, where the semiconductor chip is adapted to be mounted on the fine redistribution structure opposite to the conductive connectors. Each of the conductive connectors includes a bump and a solder cap formed on the bump, and the bump is directly connected to the fine redistribution structure. The first portion is disposed on a second portion, where the second portion includes a top redistribution structure directly connected to the solder cap and a second redistribution structure connected to the top redistribution structure, the first portion is disposed on the top redistribution structure, and a contact density of the top redistribution structure is denser than a contact density of the bottom redistribution structure.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: August 2, 2022
    Inventor: Dyi-Chung Hu
  • Patent number: 11406006
    Abstract: Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: August 2, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaoming Chen, Darryl Sheldon Jessie
  • Patent number: 11355426
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 7, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Patent number: 11335625
    Abstract: A via hole structure includes: a first conductive layer, an interlayer insulating layer, and a second conductive layer that are sequentially arranged, wherein the interlayer insulating layer is provided with a via hole, the second conductive layer is overlapped with the first conductive layer by the via hole, and at least part of a surface, in contact with the second conductive layer, of the interlayer insulating layer is uneven.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 17, 2022
    Assignees: Mianyang BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Lei Zhang, Daqing Sun, Wei Qiu, Fangliang Yan
  • Patent number: 11289401
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 29, 2022
    Assignee: Powertech Technology Inc.
    Inventor: Kun-Yung Huang
  • Patent number: 11281833
    Abstract: Systems and assemblies are provided for exchanged signal routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. Exchanged signal routing techniques involve “exchanging” the signal routing lanes on the PCB, which reduces coupled signal amplitude and phase relationship. Exchanged signal routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. A printed circuit board (PCB) can include an array of contact pads, a plurality of signal lines that include an escape route. One or more exchange junctions disposed within the escape route can route a first signal line of a first routing channel in the escape route into a second routing channel in the escape route.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: March 22, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Karl J. Bois
  • Patent number: 11246212
    Abstract: A printed circuit board deformable in both length and width includes a first conductive circuit layer, a second conductive circuit layer, an elastic film, and conductive via holes. The first conductive circuit layer includes first conductive circuits. First honeycomb holes are defined on the first conductive circuits. The second conductive circuit layer faces away from the first conductive circuit layer, the second conductive circuit layer comprises second conductive circuits, second honeycomb holes being defined on the second conductive circuits, each of the second honeycomb holes corresponds to one of the first honeycomb holes. The first conductive circuits are embedded in the elastic film. Each of the conductive via holes corresponds to one first honeycomb holes.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: February 8, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Wei-Xiang Li, Ming-Liang Zuo
  • Patent number: 11211327
    Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chin-Shen Lin, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11177205
    Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Ho Park, Jong Youn Kim, Min Jun Bae
  • Patent number: 11171081
    Abstract: A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 9, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomoaki Machida
  • Patent number: 11171272
    Abstract: A method of producing a light source device includes providing a light emitting device having a substrate including a base member that includes a bottom surface and a recess. The substrate further including a wiring portion in the recess. The method further including providing a support substrate having a support base member, a first wiring pattern on a top surface of the support base member and including a joining region, and an insulating region, and applying a solder member such that the solder member on the insulating region has a volume larger than that of the solder member on the joining region. The light emitting device is placed on the support substrate while the solder member is separate from a portion of the wiring portion positioned in the vicinity of the bottom surface and the wiring portion is joined to the joining region.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 9, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Takuya Nakabayashi
  • Patent number: 11158920
    Abstract: An electrical component, such as an RF device or thermal bridge, for use with a printed circuit board. The component has a first dielectric layer having a top and a bottom, a first conductive trace positioned on the bottom of the dielectric layer, and a first ground layer positioned on the bottom of the dielectric layer and spaced apart from the first conductive trace. For RF applications, a second conductive trace is positioned on top of first dielectric, a second dielectric is positioned on top of the second conductive trace, and a second ground plane is positioned on top of the second dielectric. A printed circuit board having a third conductive trace may then be coupled to the first conductive trace by a first solder layer.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 26, 2021
    Assignee: TTM Technologies Inc.
    Inventors: Michael Len, Hans Peter Ostergaard
  • Patent number: 11116077
    Abstract: A wiring board comprising an insulation substrate comprising a main surface and a penetrating portion that has an insulation property; and an external connection conductor, a portion of which is positioned in the insulation substrate and a different portion of which is exposed at the main surface, wherein the penetrating portion penetrates into the external connection conductor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 7, 2021
    Assignee: KYOCERA CORPORATION
    Inventors: Takuo Kisaki, Keisuke Sawada
  • Patent number: 11094636
    Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 17, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegwon Jang, Inwon O, Jongyoun Kim, Seokhyun Lee, Yeonho Jang
  • Patent number: 11096291
    Abstract: A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 17, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Chan Choi, Young Kwon Jeong, Min Soo Kim, Seong Jae Mun
  • Patent number: 11083378
    Abstract: Wearable apparatus for monitoring various physiological and environmental factors are provided. Real-time, noninvasive health and environmental monitors include a plurality of compact sensors integrated within small, low-profile devices, such as earpiece modules. Physiological and environmental data is collected and wirelessly transmitted into a wireless network, where the data is stored and/or processed.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 10, 2021
    Assignee: Valencell, Inc.
    Inventors: Steven Francis LeBoeuf, Jesse Berkley Tucker, Michael Edward Aumer
  • Patent number: 11049779
    Abstract: A carrier for a semiconductor chip mounting thereon and a manufacturing method thereof are provided. The carrier includes a fine redistribution structure, a plurality of conductive connectors, and an insulating layer. The fine redistribution structure has a first surface and a second surface opposite to each other, where the semiconductor chip is mounted on the first surface of the fine redistribution structure. The conductive connectors are disposed on the second surface of the fine redistribution structure and electrically coupled to the semiconductor chip through the fine redistribution structure. The insulating layer is disposed on the second surface of the fine redistribution structure to laterally cover the conductive connectors.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: June 29, 2021
    Inventor: Dyi-Chung Hu
  • Patent number: 11037918
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz
  • Patent number: 10966322
    Abstract: A semiconductor device includes: a sealed unit that seals a semiconductor element therein; a connection terminal that is electrically connected to the semiconductor element and is provided so as to project outward from the sealed unit; and a pedestal that is provided to surround a bottom part of an exposed portion of the connection terminal that is exposed from the sealed unit. The pedestal has a base attached to the sealed unit and a guide part that has an inclined side face.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Patent number: 10892213
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Li-Yu Hsieh, Yan Wen Chung
  • Patent number: 10832998
    Abstract: A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jee Ae Heo
  • Patent number: 10826206
    Abstract: A conductive terminal includes a holding portion, a positioning portion and a welding portion. The positioning portion is connected to the holding portion and includes two positioning branches separated by a first trench. The welding portion is connected to the positioning portion and the positioning portion is located between the holding portion and the welding portion. The welding portion includes two welding branches separated by a second trench, wherein the first trench is communicated with the second trench and each of the welding branches is connected to one of the positioning branches. The positioning portion has a first outer diameter, and a second outer diameter on at least part of the welding portion is greater than the first outer diameter. An electrical connecting structure is further provided.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: November 3, 2020
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventor: Pao-Hsiu Fan
  • Patent number: 10820420
    Abstract: In at least one illustrative embodiment, a printed circuit board may comprise at least one insulating layer, first and second conductive layers separated from one another by the at least one insulating layer, and a conductive via extending through the at least one insulating layer and electrically coupling the first and second conductive layers. The conductive via may include an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches) and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches).
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 27, 2020
    Assignee: ABB POWER ELECTRONICS INC.
    Inventor: Robert Joseph Roessler
  • Patent number: 10811823
    Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors. A method for improving signal integrity in a computer interconnect can include carrying differential signals on a set of differential signal vias in a connector pinfield; carrying sideband signals on a set of sideband vias in the connector pinfield; and reducing via-to-via crosstalk between a particular one of the sideband vias and one of the differential signal vias through one or more thru-hole ground vias adjacent to the particular sideband via in the pinfield.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Patent number: 10777497
    Abstract: Provided is a substrate including a first wiring layer, wherein the first wiring layer has a structure in which among a plurality of first connection parts of a plurality of vias, at least one of first connection parts of two vias located closer to both ends of the first wiring layer is coupled to a body of the first wiring layer through a first conductive portion, each of the plurality of first connection parts being coupled to the first wiring layer, and a cross-sectional area of the first conductive portion is less than an area of a first part of the first wiring layer, the first part being in contact with a first connection part of a via other than the first connection parts of the two vias.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Takahito Takemoto
  • Patent number: 10716210
    Abstract: Various examples provide a printed circuit board (PCB) comprising a first route from a first through-hole via to a second through-hole via, and a second route from the second through-hole via to a first microvia (e.g., coupled to a second memory module socket). Additional microvias may have a route from the first microvia that effectively daisy chains the microvias from the second through-hold via. Various examples also provide a PCB comprising a first route from a first through-hole via to a second through-hole via, and a second route from the second through-hole via to a first sequential lamination via. Additional sequential lamination vias may have a route from the first microvia that effectively daisy chains the sequential lamination vias from the second through-hold via.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: July 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Christopher M Barnette, William K Fitzgerald, Michael Day
  • Patent number: 10716217
    Abstract: A burr-suppressing copper foils are described. In an embodiment, the burr suppressing copper foil includes a poly-based film having an adhesive on a first side and an adhesive on a second side. A copper foil contacts the adhesive at the first side of the poly-based film to removably couple the poly-based film to the copper foil. A metallic burr suppressor contacts the adhesive on the second side to removably couple the poly-based film to the metallic burr suppressor.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 14, 2020
    Assignee: Advanced Copper Foil Inc.
    Inventor: Shane Hugh Stewart
  • Patent number: 10617004
    Abstract: A power line structure, an array substrate including the power line structure and a display panel are provided. The power line structure includes a conductive plate, the conductive plate includes a through hole disposing area, the through hole disposing area is provided with a plurality of via holes; in at least one sub-area of the through hole disposing area, a distribution density of the via holes increases along a direction of decreasing a current density in the conductive plate.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yunfei Li, Tian Dong
  • Patent number: 10587093
    Abstract: A connection structure for a laser and a laser assembly are provided. The connection structure for a laser includes a first insulation substrate, where the first insulation substrate includes a conductive path separately on an upper surface and a lower surface thereof. A second insulation substrate is disposed on the upper surface of the first insulation substrate. An upper surface of the second insulation substrate includes a conductive path. The conductive path on the upper surface of the second insulation substrate is electrically connected to the conductive path on the lower surface of the first insulation substrate via a through-hole. The connection structure for a laser and the laser assembly in the present disclosure are configured to supplying power to a laser.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 10, 2020
    Assignees: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD., HISENSE USA CORP., HISENSE INTERNATIONAL CO., LTD.
    Inventors: Hao Wang, Hongwei Mu, YongLiang Huang, Shun Zhang
  • Patent number: 10573623
    Abstract: An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: February 25, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Chih-Hsien Chiu
  • Patent number: 10499494
    Abstract: A circuit board includes a flexible wiring board with a reinforcing member. The flexible wiring board has a first, second and third sections. The reinforcing member is embedded in a cavity in the first section of the wiring board, and is sandwiched by a pair of resin layers provided below and above. A pair of wiring layers are disposed on the pair of the resin layers, respectively. The metal reinforcing member has either a plate shape or a frame shape and is disposed closer to one of the pair of the wiring layers than to another of the pair of the wiring layers in a vertical direction.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yutaka Hata
  • Patent number: 10485096
    Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Chun-Lin Liao
  • Patent number: 10426030
    Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
  • Patent number: 10375818
    Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: August 6, 2019
    Assignee: NEC CORPORATION
    Inventors: Kazuhiro Kashiwakura, Ayako Uemura
  • Patent number: 10369746
    Abstract: A three-dimensional data generation device includes a data division unit, a detection unit, an output command unit, and a data correction unit. The data division unit divides sectional shape data on one layer of a shaped object into mark data for shaping a mark for correction of sectional shape data on a different layer to be output as superposed on the one layer and post-removal data obtained by removing the mark data from the sectional shape data on the one layer. The detection unit detects an amount of misregistration of the mark output using the mark data from a position determined in advance. The output command unit commands output using the post-removal data so as to form the one layer of the shaped object together with the mark. The data correction unit corrects the sectional shape data on the different layer using the amount of misregistration of the detected mark.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 6, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Tetsuhiro Inoue, Masaomi Sakamoto, Fumihiko Ogasawara, Osamu Yasui, Yosuke Tashiro, Shinya Miyamori
  • Patent number: 10374280
    Abstract: A quadrature coupler having: a pair of overlying strip conductors separated by a first dielectric layer to provide a coupling region between the coupling region of overlying strip conductors; a pair of opposing ground pads, the coupling region being disposed between the pair of opposing ground pads; a second dielectric layer disposed over the coupling region and between the pair of opposing ground pads; and an electrically conductive shield layer disposed over the second dielectric layer, extending over opposing sides of the dielectric layer and onto the pair of opposing ground pads. Portions of coupler are formed by printing or additive manufacturing.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 6, 2019
    Assignee: Raytheon Company
    Inventors: Christopher M. Laighton, Susan C. Trulli, Elicia K. Harper
  • Patent number: 10332843
    Abstract: A fan-out semiconductor package includes a semiconductor chip disposed in a through-hole of a first connection member having the through-hole and a second connection member disposed on an active surface of the semiconductor chip. A plurality of dummy vias surrounding the semiconductor chip are disposed in the first connection member.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Ho Baek, Moon Hee Yi, Kyung Sang Lim
  • Patent number: 10298000
    Abstract: A door hole seal is provided between an inner panel and a door trim of an automobile door. The door hole seal comprises a slit mechanism used to pull out a wire harness from an outer-cabin side to an inner-cabin side or from the inner-cabin side to the outer-cabin side. The slit mechanism comprises a first slit extending up and down with respect to the main sheet and a circular hole formed at a lower end of the first slit. The circular hole has a diameter that is identical to or slightly smaller than that of a wire harness, and is arranged to receive the wire harness.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 21, 2019
    Assignees: NISHIKAWA RUBBER CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Yasuhiro Itsuki, Naoya Sasaki, Satoshi Endo, Hiromu Inoue
  • Patent number: 10299370
    Abstract: A differential trace pair system includes a first conductive layer that is located immediately adjacent a first insulating layer. The system includes a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, and includes an aperture that extends through the second conductive layer. A second insulating layer is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer. The system includes a first differential trace pair that is included in the second insulating layer and that includes a first differential trace that is positioned adjacent the aperture and references the second conductive layer, and a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and references the first conductive layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: May 21, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury
  • Patent number: 10251265
    Abstract: The present invention provides the prepreg being formed by impregnating a fiber base material with a resin composition and the resin composition comprising an acrylic resin, wherein the ratio of the peak height near 2240 cm?1 due to nitrile groups (PCN) with respect to the peak height near 1730 cm?1 due to carbonyl groups (PCO) in the IR spectrum of the cured resin composition (PCN/PCO) is no greater than 0.001 and the like in order to provide a prepreg, a film with a resin, a metal foil with a resin and a metal-clad laminate, which exhibit excellent bending resistance while also prevent ion migration and have excellent insulating reliability when printed wiring boards are fabricated, as well as a printed wiring board employing the same.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 2, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Akiko Kawaguchi, Nozomu Takano, Yasuyuki Mizuno, Kazumasa Takeuchi, Shigeru Haeno, Yoshinori Nagai, Masato Fukui
  • Patent number: 10249503
    Abstract: Disclosed is a printed circuit board including an insulating layer, a circuit layer formed on a lower surface of the insulating layer, and a metal post contacting the circuit layer and extending from the lower surface to an upper surface of the insulating layer. The printed circuit board is able to prevent shorts while components are mounted by forming a metal post to have a secured height tolerance to connect with a die and to be in a caved shape into the board.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung-Ro Yoon, Hyun-Kyung Park
  • Patent number: 10204203
    Abstract: Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Yan Lin, Yi-Min Jiang, Phillip H. Tai, Lin Yuan
  • Patent number: 10187971
    Abstract: A wiring board that includes: insulation layers and wiring layers which are laminated alternately; a component connection pad present on one surface of the wiring board in a lamination direction of the insulation layers and the wiring layers, and to which an electronic component is connected; a circuit connection pad present on another surface of the wiring board in the lamination direction and is connected to a circuit board; and a structure which includes a coaxial structure, wherein each of the wiring layers is connected by a via, and the coaxial structure includes an inner wiring part extending in the lamination direction and an outer wiring part located on a side corresponding to an outer peripheral surface of the inner wiring part through an insulating resin, and the inner wiring part is electrically connected to the component connection pad and the circuit connection pad.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 22, 2019
    Assignee: Sony Corporation
    Inventor: Kosuke Hareyama
  • Patent number: 10164361
    Abstract: A separator is configured to separate first and second printed circuit boards that are in electrical communication with each other through first and second pluralities of electrical connectors that are mounted to the first and second substrates, respectively, and mated to each other.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 25, 2018
    Assignee: FCI USA LLC
    Inventor: Steven E. Minich
  • Patent number: 10163557
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Patent number: 10165688
    Abstract: A flexible electronic device including a first flexible substrate, an electronic component, and a control device is provided. The electronic component includes a conductive layer. The control device includes at least one integrated circuit and a circuit layer set. The circuit layer set includes a plurality of circuit layers and at least one first dielectric layer, and at least a portion of the first dielectric layer is interposed between two adjacent circuit layers. The integrated circuit is electrically connected to the electronic component through the circuit layer set and the conductive layer. At least a portion of the conductive layer and at least a portion of one circuit layer are integrally formed, and the conductive layer and the circuit layer are both disposed on the first flexible substrate. A fabricating method of a flexible electronic device is also provided.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Po Wang, Heng-Yin Chen, Cheng-Chung Lee, Jia-Chong Ho, Yung-Hui Yeh, Tai-Jui Wang
  • Patent number: 10135335
    Abstract: In some examples, a device comprises an inductor and a package comprising at least one power device. The package is attached to the inductor by an adhesion layer, and the inductor comprises one or more leads. A first lead of the one or more leads is configured to conduct electricity between the at least one power device and the inductor, and a surface of the first lead and a surface of the package are substantially co-planar.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 10111338
    Abstract: Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Frank Truong, Dilan Seneviratne
  • Patent number: 10111368
    Abstract: Systems to manufacture an electronic circuit assembly are disclosed. In one embodiment, the system includes a flexible substrate with a substrate registration feature and a carrier with a carrier registration feature. A removable fastener removably fixes the flexible substrate to the carrier by being received into the substrate registration feature and the carrier registration feature. Once the flexible substrate is removably affixed to the carrier, the carrier provides the flexible substrate with rigidity to receive at least one electronic device of the electronic circuit assembly.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Joshua D. Heppner
  • Patent number: 10062677
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz