Hollow (e.g., Plated Cylindrical Hole) Patents (Class 174/266)
  • Patent number: 10892213
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Li-Yu Hsieh, Yan Wen Chung
  • Patent number: 10832998
    Abstract: A semiconductor package includes an organic interposer, a semiconductor chip, a passivation layer, and an underbump metallurgy (UBM) layer. The organic interposer includes insulating layers and wiring layers disposed on the insulating layers. The semiconductor chip is disposed on one surface of the organic interposer. The passivation layer is disposed on another surface of the organic interposer opposing the one surface on which the semiconductor chip is disposed, and has openings extending to portions of the wiring layer. The UBM layer includes UBM pads disposed on the passivation layer and UBM vias disposed in the openings and connecting the UBM pads and the wiring layer to each other. At least one groove portion is disposed in an outer circumferential surface of the UBM pad.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jee Ae Heo
  • Patent number: 10826206
    Abstract: A conductive terminal includes a holding portion, a positioning portion and a welding portion. The positioning portion is connected to the holding portion and includes two positioning branches separated by a first trench. The welding portion is connected to the positioning portion and the positioning portion is located between the holding portion and the welding portion. The welding portion includes two welding branches separated by a second trench, wherein the first trench is communicated with the second trench and each of the welding branches is connected to one of the positioning branches. The positioning portion has a first outer diameter, and a second outer diameter on at least part of the welding portion is greater than the first outer diameter. An electrical connecting structure is further provided.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: November 3, 2020
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventor: Pao-Hsiu Fan
  • Patent number: 10820420
    Abstract: In at least one illustrative embodiment, a printed circuit board may comprise at least one insulating layer, first and second conductive layers separated from one another by the at least one insulating layer, and a conductive via extending through the at least one insulating layer and electrically coupling the first and second conductive layers. The conductive via may include an annular via sidewall having an average radial thickness of at least 2.5 mils (0.0025 inches) and a conductive pad having an average thickness of no more than 3.2 mils (0.0032 inches).
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 27, 2020
    Assignee: ABB POWER ELECTRONICS INC.
    Inventor: Robert Joseph Roessler
  • Patent number: 10811823
    Abstract: A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors. A method for improving signal integrity in a computer interconnect can include carrying differential signals on a set of differential signal vias in a connector pinfield; carrying sideband signals on a set of sideband vias in the connector pinfield; and reducing via-to-via crosstalk between a particular one of the sideband vias and one of the differential signal vias through one or more thru-hole ground vias adjacent to the particular sideband via in the pinfield.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventor: Timothy D. Wig
  • Patent number: 10777497
    Abstract: Provided is a substrate including a first wiring layer, wherein the first wiring layer has a structure in which among a plurality of first connection parts of a plurality of vias, at least one of first connection parts of two vias located closer to both ends of the first wiring layer is coupled to a body of the first wiring layer through a first conductive portion, each of the plurality of first connection parts being coupled to the first wiring layer, and a cross-sectional area of the first conductive portion is less than an area of a first part of the first wiring layer, the first part being in contact with a first connection part of a via other than the first connection parts of the two vias.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Takahito Takemoto
  • Patent number: 10716217
    Abstract: A burr-suppressing copper foils are described. In an embodiment, the burr suppressing copper foil includes a poly-based film having an adhesive on a first side and an adhesive on a second side. A copper foil contacts the adhesive at the first side of the poly-based film to removably couple the poly-based film to the copper foil. A metallic burr suppressor contacts the adhesive on the second side to removably couple the poly-based film to the metallic burr suppressor.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 14, 2020
    Assignee: Advanced Copper Foil Inc.
    Inventor: Shane Hugh Stewart
  • Patent number: 10716210
    Abstract: Various examples provide a printed circuit board (PCB) comprising a first route from a first through-hole via to a second through-hole via, and a second route from the second through-hole via to a first microvia (e.g., coupled to a second memory module socket). Additional microvias may have a route from the first microvia that effectively daisy chains the microvias from the second through-hold via. Various examples also provide a PCB comprising a first route from a first through-hole via to a second through-hole via, and a second route from the second through-hole via to a first sequential lamination via. Additional sequential lamination vias may have a route from the first microvia that effectively daisy chains the sequential lamination vias from the second through-hold via.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: July 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Christopher M Barnette, William K Fitzgerald, Michael Day
  • Patent number: 10617004
    Abstract: A power line structure, an array substrate including the power line structure and a display panel are provided. The power line structure includes a conductive plate, the conductive plate includes a through hole disposing area, the through hole disposing area is provided with a plurality of via holes; in at least one sub-area of the through hole disposing area, a distribution density of the via holes increases along a direction of decreasing a current density in the conductive plate.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yunfei Li, Tian Dong
  • Patent number: 10587093
    Abstract: A connection structure for a laser and a laser assembly are provided. The connection structure for a laser includes a first insulation substrate, where the first insulation substrate includes a conductive path separately on an upper surface and a lower surface thereof. A second insulation substrate is disposed on the upper surface of the first insulation substrate. An upper surface of the second insulation substrate includes a conductive path. The conductive path on the upper surface of the second insulation substrate is electrically connected to the conductive path on the lower surface of the first insulation substrate via a through-hole. The connection structure for a laser and the laser assembly in the present disclosure are configured to supplying power to a laser.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 10, 2020
    Assignees: HISENSE BROADBAND MULTIMEDIA TECHNOLOGIES CO., LTD., HISENSE USA CORP., HISENSE INTERNATIONAL CO., LTD.
    Inventors: Hao Wang, Hongwei Mu, YongLiang Huang, Shun Zhang
  • Patent number: 10573623
    Abstract: An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: February 25, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Chih-Hsien Chiu
  • Patent number: 10499494
    Abstract: A circuit board includes a flexible wiring board with a reinforcing member. The flexible wiring board has a first, second and third sections. The reinforcing member is embedded in a cavity in the first section of the wiring board, and is sandwiched by a pair of resin layers provided below and above. A pair of wiring layers are disposed on the pair of the resin layers, respectively. The metal reinforcing member has either a plate shape or a frame shape and is disposed closer to one of the pair of the wiring layers than to another of the pair of the wiring layers in a vertical direction.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yutaka Hata
  • Patent number: 10485096
    Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 19, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Chun-Lin Liao
  • Patent number: 10426030
    Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
  • Patent number: 10369746
    Abstract: A three-dimensional data generation device includes a data division unit, a detection unit, an output command unit, and a data correction unit. The data division unit divides sectional shape data on one layer of a shaped object into mark data for shaping a mark for correction of sectional shape data on a different layer to be output as superposed on the one layer and post-removal data obtained by removing the mark data from the sectional shape data on the one layer. The detection unit detects an amount of misregistration of the mark output using the mark data from a position determined in advance. The output command unit commands output using the post-removal data so as to form the one layer of the shaped object together with the mark. The data correction unit corrects the sectional shape data on the different layer using the amount of misregistration of the detected mark.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 6, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Tetsuhiro Inoue, Masaomi Sakamoto, Fumihiko Ogasawara, Osamu Yasui, Yosuke Tashiro, Shinya Miyamori
  • Patent number: 10374280
    Abstract: A quadrature coupler having: a pair of overlying strip conductors separated by a first dielectric layer to provide a coupling region between the coupling region of overlying strip conductors; a pair of opposing ground pads, the coupling region being disposed between the pair of opposing ground pads; a second dielectric layer disposed over the coupling region and between the pair of opposing ground pads; and an electrically conductive shield layer disposed over the second dielectric layer, extending over opposing sides of the dielectric layer and onto the pair of opposing ground pads. Portions of coupler are formed by printing or additive manufacturing.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 6, 2019
    Assignee: Raytheon Company
    Inventors: Christopher M. Laighton, Susan C. Trulli, Elicia K. Harper
  • Patent number: 10375818
    Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: August 6, 2019
    Assignee: NEC CORPORATION
    Inventors: Kazuhiro Kashiwakura, Ayako Uemura
  • Patent number: 10332843
    Abstract: A fan-out semiconductor package includes a semiconductor chip disposed in a through-hole of a first connection member having the through-hole and a second connection member disposed on an active surface of the semiconductor chip. A plurality of dummy vias surrounding the semiconductor chip are disposed in the first connection member.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Ho Baek, Moon Hee Yi, Kyung Sang Lim
  • Patent number: 10299370
    Abstract: A differential trace pair system includes a first conductive layer that is located immediately adjacent a first insulating layer. The system includes a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, and includes an aperture that extends through the second conductive layer. A second insulating layer is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer. The system includes a first differential trace pair that is included in the second insulating layer and that includes a first differential trace that is positioned adjacent the aperture and references the second conductive layer, and a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and references the first conductive layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: May 21, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury
  • Patent number: 10298000
    Abstract: A door hole seal is provided between an inner panel and a door trim of an automobile door. The door hole seal comprises a slit mechanism used to pull out a wire harness from an outer-cabin side to an inner-cabin side or from the inner-cabin side to the outer-cabin side. The slit mechanism comprises a first slit extending up and down with respect to the main sheet and a circular hole formed at a lower end of the first slit. The circular hole has a diameter that is identical to or slightly smaller than that of a wire harness, and is arranged to receive the wire harness.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 21, 2019
    Assignees: NISHIKAWA RUBBER CO., LTD., HONDA MOTOR CO., LTD.
    Inventors: Yasuhiro Itsuki, Naoya Sasaki, Satoshi Endo, Hiromu Inoue
  • Patent number: 10251265
    Abstract: The present invention provides the prepreg being formed by impregnating a fiber base material with a resin composition and the resin composition comprising an acrylic resin, wherein the ratio of the peak height near 2240 cm?1 due to nitrile groups (PCN) with respect to the peak height near 1730 cm?1 due to carbonyl groups (PCO) in the IR spectrum of the cured resin composition (PCN/PCO) is no greater than 0.001 and the like in order to provide a prepreg, a film with a resin, a metal foil with a resin and a metal-clad laminate, which exhibit excellent bending resistance while also prevent ion migration and have excellent insulating reliability when printed wiring boards are fabricated, as well as a printed wiring board employing the same.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 2, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Akiko Kawaguchi, Nozomu Takano, Yasuyuki Mizuno, Kazumasa Takeuchi, Shigeru Haeno, Yoshinori Nagai, Masato Fukui
  • Patent number: 10249503
    Abstract: Disclosed is a printed circuit board including an insulating layer, a circuit layer formed on a lower surface of the insulating layer, and a metal post contacting the circuit layer and extending from the lower surface to an upper surface of the insulating layer. The printed circuit board is able to prevent shorts while components are mounted by forming a metal post to have a secured height tolerance to connect with a die and to be in a caved shape into the board.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung-Ro Yoon, Hyun-Kyung Park
  • Patent number: 10204203
    Abstract: Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: February 12, 2019
    Assignee: Synopsys, Inc.
    Inventors: Yan Lin, Yi-Min Jiang, Phillip H. Tai, Lin Yuan
  • Patent number: 10187971
    Abstract: A wiring board that includes: insulation layers and wiring layers which are laminated alternately; a component connection pad present on one surface of the wiring board in a lamination direction of the insulation layers and the wiring layers, and to which an electronic component is connected; a circuit connection pad present on another surface of the wiring board in the lamination direction and is connected to a circuit board; and a structure which includes a coaxial structure, wherein each of the wiring layers is connected by a via, and the coaxial structure includes an inner wiring part extending in the lamination direction and an outer wiring part located on a side corresponding to an outer peripheral surface of the inner wiring part through an insulating resin, and the inner wiring part is electrically connected to the component connection pad and the circuit connection pad.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 22, 2019
    Assignee: Sony Corporation
    Inventor: Kosuke Hareyama
  • Patent number: 10164361
    Abstract: A separator is configured to separate first and second printed circuit boards that are in electrical communication with each other through first and second pluralities of electrical connectors that are mounted to the first and second substrates, respectively, and mated to each other.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 25, 2018
    Assignee: FCI USA LLC
    Inventor: Steven E. Minich
  • Patent number: 10163557
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Patent number: 10165688
    Abstract: A flexible electronic device including a first flexible substrate, an electronic component, and a control device is provided. The electronic component includes a conductive layer. The control device includes at least one integrated circuit and a circuit layer set. The circuit layer set includes a plurality of circuit layers and at least one first dielectric layer, and at least a portion of the first dielectric layer is interposed between two adjacent circuit layers. The integrated circuit is electrically connected to the electronic component through the circuit layer set and the conductive layer. At least a portion of the conductive layer and at least a portion of one circuit layer are integrally formed, and the conductive layer and the circuit layer are both disposed on the first flexible substrate. A fabricating method of a flexible electronic device is also provided.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Sheng-Po Wang, Heng-Yin Chen, Cheng-Chung Lee, Jia-Chong Ho, Yung-Hui Yeh, Tai-Jui Wang
  • Patent number: 10135335
    Abstract: In some examples, a device comprises an inductor and a package comprising at least one power device. The package is attached to the inductor by an adhesion layer, and the inductor comprises one or more leads. A first lead of the one or more leads is configured to conduct electricity between the at least one power device and the inductor, and a surface of the first lead and a surface of the package are substantially co-planar.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette
  • Patent number: 10111338
    Abstract: Embodiments herein relate to creating a high-aspect ratio opening in a package. Embodiments may include applying a first laminate layer on a side of a substrate, applying a seed layer to at least part of the laminate layer, building up one or more copper pads on the seed layer, etching the seed layer to expose a portion of the first laminate layer, applying a second laminate layer to fill in around the sides of one or more copper pads, and removing part of the buildup copper pads. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Frank Truong, Dilan Seneviratne
  • Patent number: 10111368
    Abstract: Systems to manufacture an electronic circuit assembly are disclosed. In one embodiment, the system includes a flexible substrate with a substrate registration feature and a carrier with a carrier registration feature. A removable fastener removably fixes the flexible substrate to the carrier by being received into the substrate registration feature and the carrier registration feature. Once the flexible substrate is removably affixed to the carrier, the carrier provides the flexible substrate with rigidity to receive at least one electronic device of the electronic circuit assembly.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Joshua D. Heppner
  • Patent number: 10064271
    Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 28, 2018
    Assignee: ZTE CORPORATION
    Inventors: Bi Yi, Fengchao Ma, Yonghui Ren, Wang Xiong, Yingxin Wang
  • Patent number: 10064270
    Abstract: Provided herein are flexible interconnects, systems containing one or more flexible interconnects, and textiles including one or more flexible interconnects.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 28, 2018
    Assignee: North Carolina State University
    Inventors: Jesse S. Jur, Murat Yokus, Rachel Foote, Amanda Caton Myers, Raj Pravinbhai Bhakta
  • Patent number: 10062677
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz
  • Patent number: 10015881
    Abstract: A method is disclosed for making an interconnection component. The steps include forming a mask layer covering a first opening in a sheet-like element that has first and second opposed surfaces; forming a plurality of mask openings in the mask layer, wherein the first opening and a portion of the first surface are partly aligned with each mask opening; and forming electrical conductors on spaced apart portions of the first surface and on spaced apart portions of the interior surface within the first opening which are exposed by the mask openings. The element may consist essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. Each conductor may extend along an axial direction of the first opening and the first conductors may be fully separated from one another within the first opening.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: July 3, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Craig Mitchell, Belgacem Haba, Ilyas Mohammed
  • Patent number: 9998234
    Abstract: An optical receiver is disclosed having a dielectric non-conductive substrate. A ground plane is positioned on the dielectric non-conductive substrate. An optical signal converting photodiode is also positioned on the dielectric non-conductive substrate, and has an optical signal receiver and an electrical signal output. An electrical signal amplifier is provided having an input connected to the electrical signal output of the optical signal converting photodiode. A first opening is positioned in the ground plane and surrounds the optical signal converting photodiode. The first opening has a resonance frequency higher than a fundamental frequency such that crosstalk is reducible at the input of the electrical signal amplifier.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 12, 2018
    Assignee: FINISAR CORPORATION
    Inventors: Andrei Kaikkonen, Lennart Per Olof Lundqvist, Lars-Goete Svensson, Peter Lindberg
  • Patent number: 9966513
    Abstract: A light emitting device includes a light emitting element; a light reflecting member having an Ag-containing layer on a surface thereof; and a protective film having a thickness of 1 nm to 300 nm and covering a surface of the light reflecting member, the protective film covering a surface of the light reflecting member, in which the Ag-containing layer has a thickness of 0.1 ?m to 0.5 ?m.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: May 8, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Masakazu Sakamoto, Yoshiki Sato, Yasuo Kato
  • Patent number: 9951420
    Abstract: A nanoparticles aerosol generator is disclosed. The nanoparticles aerosol generator includes an evaporation chamber having a wall, a container containing a source material, and a heating device configured to heat the source material. The nanoparticles aerosol generator also includes a carrier gas source configured to blow a carrier gas toward the source material to generate a nanoparticles aerosol with nanoparticles of the source material suspended therein. The nanoparticles aerosol generator further includes a dilution gas source configured to supply a dilution gas into the chamber to flow substantially along the wall within the chamber and to dilute the nanoparticles aerosol.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 24, 2018
    Assignee: SOL VOLTAICS AB
    Inventor: Greg Alcott
  • Patent number: 9935066
    Abstract: The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 3, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, Robert Hartmann
  • Patent number: 9930775
    Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. A first liquid dielectric layer is imaged directly on the first surface of the first circuitry layer to form a first dielectric layer with a plurality of first recesses. Conductive plating substantially fills a plurality of the first recesses to create a plurality of first solid copper conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A second liquid dielectric layer is imaged directly on the first dielectric layer to form a second dielectric layer with a plurality of second recesses. Conductive plating substantially fills a plurality of the second recesses to form a plurality of second solid copper conductive pillars electrically coupled to, and extending parallel with, the first conductive pillars. An IC device is electrically coupled to a plurality of the second conductive pillars.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 27, 2018
    Assignee: HSIO Technologies, LLC
    Inventor: Jim Rathburn
  • Patent number: 9905519
    Abstract: An electronic structure process includes the following steps. A redistribution structure and a carrier plate are provided. A plurality of first bonding protruding portions and a first supporting structure are formed on the redistribution structure. A first encapsulated material is formed and filled between a first opening and the first bonding protruding portions. The carrier plate is removed. A plurality of second bonding protruding portions and a second supporting structure are formed on the redistribution structure. A second encapsulated material is formed and filled between a second opening and the second bonding protruding portions.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 27, 2018
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Chen-Yueh Kung
  • Patent number: 9853414
    Abstract: A connection structure for a laser and a laser assembly are provided. The connection structure for a laser includes a first insulation substrate, where the first insulation substrate includes a conductive path separately on an upper surface and a lower surface thereof. A second insulation substrate is disposed on the upper surface of the first insulation substrate. An upper surface of the second insulation substrate includes a conductive path. The conductive path on the upper surface of the second insulation substrate is electrically connected to the conductive path on the lower surface of the first insulation substrate via a through-hole. The connection structure for a laser and the laser assembly in the present disclosure are configured to supplying power to a laser.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 26, 2017
    Assignees: Hisense Broadband Multimedia Technologies Co., Ltd., Hisense USA Corp., Hisense International Co., Ltd.
    Inventors: Hao Wang, Hongwei Mu, YungLiang Huang, Shun Zhang
  • Patent number: 9844146
    Abstract: The invention is related to an electrical circuitry assembly as well as a method for manufacturing such an electrical circuitry assembly, wherein the assembly basically but not exclusively comprising of an electrically conductive metal plate and a circuit including a conductive layer and wherein both the metal plate and the circuit shall be electrically connected to each other.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: December 12, 2017
    Assignee: Flextronics Automotive GmbH & Co. KG
    Inventors: Peter Lutz, Kevin Buermann
  • Patent number: 9832888
    Abstract: A method of manufacture of a circuit board without annular through-hole rings and thus allowing a higher component density includes a base layer, a first wire pattern layer, and a second wire pattern layer on both sides of the base layer. A portion of the base layer not covered by the first wire pattern layer defines at least one first hole. The circuit board further includes a wire layer. The wire layer includes at least a first portion and a second portion connecting to the first portion. The first portion is filled in the first hole. The second portion is formed on the first portion extending away from the base layer. A diameter of the second portion is less than an aperture diameter of the first hole. The wire layer is electrically conductive between the first wire pattern layer and the second wire pattern layer through the first portion.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 28, 2017
    Assignees: Avary Holding (Shenzhen) Co., Limited, HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Yan-Lu Li, Mei Yang, Cheng-Jia Li
  • Patent number: 9763331
    Abstract: A printed circuit board includes: a first electrode made of a tubular electric conductor formed on an inner wall of a first hole formed in the printed circuit board; a dielectric body disposed inside the first electrode; and a second electrode made of a tubular electric conductor formed on an inner wall of a second hole extending through the dielectric body, the second electrode having a center axis concentric with the first electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiyuki Hiroshima, Naoki Nakamura, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Patent number: 9730313
    Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers; an antipad of a first type around and between the first and second signal vias in one or more of the attachment layers; and antipads of a second type around the first and second signal vias in at least one routing layer adjacent to the breakout layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 8, 2017
    Assignee: Amphenol Corporation
    Inventors: Mark W. Gailus, Marc B. Cartier, Jr., Vysakh Sivarajan, David Levine
  • Patent number: 9683292
    Abstract: A metal circuit structure is provided. The metal circuit structure includes a substrate, a first trigger layer and a first metal circuit layer. The first trigger layer is disposed on the substrate and includes a first metal circuit pattern. The first metal circuit layer is disposed on the first circuit pattern and is electrically insulated from the substrate. The composition of the first trigger layer includes an insulating gel and a plurality of trigger particles. The trigger particles are at least one of organometallic particles, a chelation and a semiconductor material having an energy gap greater than or equal to 3 eV. The trigger particles are disposed in the insulating gel, such that the dielectric constant of the first trigger layer after curing is between 2 and 6.5.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: June 20, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tune-Hune Kao, Meng-Chi Huang, Min-Chieh Chou
  • Patent number: 9655236
    Abstract: A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 16, 2017
    Assignee: HARRIS CORPORATION
    Inventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Casey Philip Rodriguez
  • Patent number: 9603255
    Abstract: A method for producing a printed circuit board is disclosed. In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: March 21, 2017
    Assignee: NextGin Technology BV
    Inventor: J. A. A. M. Tourne
  • Patent number: 9585260
    Abstract: There are provided an electronic component module capable of increasing a degree of integration by mounting electronic components on both surfaces of a substrate, and a manufacturing method thereof. The electronic component module according to an exemplary embodiment of the present disclosure includes: a substrate; a plurality of electronic components mounted on both surfaces of the substrate; connection conductors each having one end bonded to one surface of the substrate using an conductive adhesive; and a molded portion having the connection conductor embedded therein and formed on one surface of the substrate, wherein the connection conductor may have at least one blocking member preventing a spread of the conductive adhesive.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 28, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hyun Lim, Jong In Ryu, Sun Ho Kim, Eun Jung Jo, Kyu Hwan Oh, Do Jae Yoo
  • Patent number: 9578743
    Abstract: A circuit board is provided that includes an outermost conductor layer including a plurality of terminals for flip-chip bonding and an outermost resin insulating layer defining a first opening and a second opening in an electronic-component mounting region. One of a power supply terminal and a ground terminal is exposed in the first opening. A plurality of signal terminals are exposed in the second opening. The resin insulating layer includes a reinforcing portion that defines an inner bottom surface of the second opening. A height of a portion of the terminal exposed in the first opening, the portion projecting from an inner bottom surface of the first opening, is greater than a height of portions of the terminals exposed in the second opening, the portions projecting from the inner bottom surface of the second opening.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 21, 2017
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Makoto Nagai, Seiji Mori, Tatsuya Ito