Abstract: In one embodiment, a printed circuit board (PCB) comprises one or more signal contact pads on a surface of the PCB and a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pads) having gaps in line with the trace(s). In another embodiment, a PCB comprises one or more signal traces on a first surface of the PCB, a plurality of ground planes embedded in the PCB, and at least one blind via interconnecting the ground planes. In still another embodiment, a PCB comprises one or more signal contact pads on a first surface of the PCB, a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pad(s) having a gap in line with the signal contact pad(s), and at least one blind via interconnecting the ground planes. In still another embodiment, signal contact pads may be formed on both major surfaces of the PCB.

Abstract: Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

Abstract: Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

Abstract: An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad.

Abstract: A printed circuit board, and method of manufacture, for high speed signals. The printed circuit board has small diameter vias of uniform inside diameter when plated. The uniformity of the inside diameter, at least over the region in which a press fit segment is inserted, is sufficient to make a reliable electrical and mechanical connection to the press fit segment with reduced risk of damage to the press fit segment.

Abstract: Embodiments of the invention provide a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.

Abstract: An electronic device including a first ground conductor layer positioned at an underside of a first insulation layer; a second ground conductor layer positioned at an upper side of the first insulation layer; a second insulation layer positioned at an upper side of the second ground conductor layer; a first connection pattern formed on an inside wall of a first opening penetrating the first insulation layer and the second insulation layer and interconnecting the first ground conductor layer and the second ground conductor layer; a conductive member provided in the first opening and connected to the first ground conductor layer; and an electronic element mounted on the member and grounded to the member.

Abstract: The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: preparing a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier; then attaching an interconnect substrate to the supporting board using a dielectric layer; then removing the bump and a portion of the flange to form a cavity and expose the dielectric layer; and then forming a via opening in the dielectric layer to expose a selected portion of the interconnect substrate. A semiconductor device can be mounted on the cavity substrate and electrically connected to the exposed portion of the interconnect substrate. The interconnect substrate provides signal routing for the semiconductor device while the stiffener can provide adequate mechanical support for the interconnect substrate and the semiconductor device.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A multi-finish printed circuit board may include one or more electrically conductive elements, such as through hole pads, that may have a first surface finish and one or more electrically conductive elements, such as surface mount pads, that may have a second surface finish that is different from the first surface finish. The first surface finish may be a hot air solder leveling (HASL) surface finish or a lead-free hot air solder leveling (LF HASL) surface finish and the second surface finish may be an organic surface protector (OSP) surface finish. The second surface finish may be applied to one or more electrically conductive elements from which the first surface finish was removed.

Abstract: In one embodiment, an apparatus includes a cover panel. An adhesive layer is coupled to the cover panel. A perimeter of the adhesive layer forms at least a portion of a gasket seal extending substantially perpendicular to an inner surface of the cover panel. An inner surface of the gasket seal defines an edge of a channel. The apparatus also includes a substrate coupled to the adhesive layer. The substrate includes an outer surface having disposed thereon a connection pad region and drive or sense electrodes. The drive or sense electrodes are disposed between the substrate and the cover panel. At least a portion of the channel is disposed between the gasket seal and the connection pad region. The apparatus further includes a flexible printed circuit (FPC) electrically coupled by the connection pad region to the drive or sense electrodes. A first portion of the FPC extends through the channel.

Abstract: An insulating layer is formed on a support substrate having a conductive property. Write wiring traces, read wiring traces, and first and second electrode pad pairs are formed on the insulating layer. The first electrode pad pair is connected to the write wiring traces. The second electrode pad pair is connected to the read wiring traces. Parts of regions of the support substrate, which overlap the electrode pads, are removed. Thus, openings are formed in the regions of the support substrate, which overlap the electrode pads.

Abstract: An improvement in the manufacturing efficiency of a circuit substrate and a semiconductor module where a semiconductor device including electrodes on a front and a back surface is mounted. [Solution] A semiconductor module includes a wiring substrate where a via and a interconnecting pattern are formed, a semiconductor device disposed on a first surface side of the wiring substrate, and a bonding portion including a first bonding layer disposed on the wiring substrate side and a second bonding layer disposed on the semiconductor device side.

Abstract: A printed wiring board includes an insulating substrate having a penetrating hole formed through the substrate, a first conductive pattern formed on first surface of the substrate, a second conductive pattern formed on second surface of the substrate on the opposite side of the first surface, and a through-hole conductor formed in the penetrating hole in the substrate such that the conductor is connecting the first conductive pattern on the first surface of the substrate and the second conductive pattern on the second surface of the substrate. The penetrating hole has a first opening portion opening on the first surface of the substrate, a second opening portion opening on the second surface of the substrate and a third opening portion connecting the first and second opening portions, and the third opening portion has the maximum diameter which is greater than the minimum diameters of the first and second opening portions.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: In accordance with the various embodiments disclosed herein, electrical connector footprints, such as printed circuit boards, is described comprising one or more of signal traces that each include a first section that extends parallel to the linear array direction and a second section extends in a direction that is different than the linear array direction.

Abstract: In accordance with the various embodiments disclosed herein, an improved electrical connector footprints, such as printed circuit boards (printed circuit board), is described comprising one or more of, for example, a first linear array containing at least a first anti-pad extending along a first direction, a first electrical signal trace extending along the first direction and spaced from the first linear array along a second direction that is perpendicular to the first direction, a group of ground isolation vias containing at least one electrically conductive ground via arranged along a line extending parallel to the first direction and spaced from the first electrical signal trace along the second direction, and a second linear array containing at least a second anti-pad extending along the first direction spaced from the group of ground isolation vias along the second direction.

Abstract: It is impossible to make a wiring board for noise suppression thinner, therefore, a wiring board according to an exemplary aspect of the invention includes a first wiring layer, an intermediate layer, and a second wiring layer; wherein the second wiring layer, the intermediate layer, and the first wiring layer are stacked in this order; the first wiring layer comprises a first wiring and a second wiring separated from the first wiring; the intermediate layer comprises a first via and a second via; the second wiring layer comprises a third wiring and a non-wiring portion where wirings are not formed; the first wiring is separated from the third wiring; the first via and the second via electrically connect the second wiring to the third wiring respectively; the non-wiring portion is located at a portion corresponding to an area between the first via and the second via; and the first wiring and the second wiring cross over the non-wiring portion.

Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.

Abstract: A circuit board and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A substrate having a first surface and a second surface opposite to each other is provided. A first circuit layer is formed on the first surface. A stress is applied to the first circuit layer and the substrate using a awl tool, such that the first circuit layer and the substrate are deformed to form a through hole. A portion of the first circuit layer is located on the sidewalls of the through hole and an end of the through hole is protruded from the second surface. A printing process is performed to form a second circuit layer on the second surface. The second circuit layer is connected to the first circuit layer located in the through hole.

Abstract: The present disclosure relates to a method of optimizing via cutouts, including selecting a geometry of a via cutout on a first ground reference layer adjacent to a first differential trace, the geometry selected to provide an extension region extending in the direction of the first differential trace. Additionally, the method includes the steps of selecting a geometry of the first differential trace, wherein a spacing of the first differential trace in the extension region is different from a spacing of the first differential trace outside the extension region, and selecting a radial dimension of a first and second via cutout on a second ground reference layer adjacent to and between the first and second differential traces, the radial dimension of the first via cutout and the second via cutout selected such that the second ground reference layer remains intact in the area adjacent the second differential trace.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: The invention provides a method for manufacturing a circuit board comprising the steps of: (a) forming a through hole in a substrate; (b) providing a photo resist to cover a predetermined area adjacent to the through hole on a first surface and a second surface opposite to the first surface of the substrate; and (c) performing an etching process to make the through hole has a shape of dumbbell.

Abstract: A method for manufacturing a printed wiring board includes preparing a metal sheet having metal members and connectors joining the metal members, forming a structure having core substrates which are connected through the connectors and which have insulation structure portions covering the metal members, respectively, cutting the connectors in the structure such that an independent core substrate having a recessed portion is formed and a respective one of the connectors is removed from the independent core substrate, and covering the recess portion of the independent core substrate with a resin. The covering of the recess portion includes either forming an interlayer insulation layer on a surface of the independent core substrate or forming interlayer insulation layers on opposing surfaces of the independent core substrate.

Abstract: A wiring substrate includes a first wiring layer with a wiring pattern and a metal foil. A first insulating layer includes a first through hole having a first end facing the metal foil and a second end. A second wiring layer includes a first opening having a diameter smaller than the second end. A second insulating layer includes a second through hole having a third end facing the wiring pattern and a fourth end. A third wiring layer includes a second opening having a diameter smaller than the fourth end. A first via is filled in the first opening, the first through hole, and a first recess, in the metal foil, having a diameter greater than the first end. A second via is filled in the second opening, the second through hole, and a second recess, in the wiring pattern, having a diameter greater than the third end.

Abstract: A circuit board includes an inorganic material insulating layer, a first circuit pattern layer formed on a surface of the inorganic material insulating layer, a first build-up insulating layer formed on the inorganic material insulating layer and formed of an organic material, and a second circuit pattern layer formed on a surface of the first build-up insulating layer.

Abstract: The invention proposes a printed circuit board with multiple layers, which features at least one outer layer and at least one inner layer adjacent to the outer layer. The printed circuit board features a plurality of micro-through-holes, which are formed between a supply voltage area of at least one outer layer and a supply voltage area of at least one inner layer.

Abstract: Disclosed herein is a printed circuit board, including: a base substrate; a first insulating layer formed on the base substrate; a first via formed on the base substrate and formed to penetrate through the first insulating layer; a first plating layer formed to surround an upper part of the first insulating layer and a side and a lower part of the first via; a second via formed on at least one of the first via and the first insulating layer; and a second insulating layer formed on the first insulating layer and formed to surround a side of the second via.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

Abstract: A wiring substrate includes an inorganic substrate including a substrate body formed of an inorganic material, a wiring pattern formed on the substrate body, and an external connection terminal being electrically connected to the wiring pattern, an organic substrate that is formed below the inorganic substrate, the organic substrate including an insulating layer and a wiring layer formed on the insulating layer, and a bonding layer interposed between the inorganic substrate and the organic substrate, the bonding layer including a stress buffer layer and a penetration wiring that penetrates the stress buffer layer. A thermal expansion coefficient of the stress buffer layer is greater than a thermal expansion coefficient of the inorganic substrate and less than a thermal expansion coefficient of the organic substrate. The wiring pattern and the wiring layer are electrically connected by way of the penetration wiring.

Abstract: Disclosed herein are a printed circuit board (PCB) and a method of manufacturing the same. The PCB includes a core layer, metal bumps embedded in the core layer, one surface of the metal bumps being opened to the outside, and a solder resist layer including an opening is manufactured by a separating substrate manufacture method. In the PCB, empty space between the bumps is filled with an insulating material instead of solder resist, and thus, a problem in terms of an empty space between bumps is addressed without requiring a new solder resist process.

Abstract: Disclosed herein is a circuit board including: a core layer including a via hole; a metal film covering an inner wall of the via hole; a circuit pattern connected to the metal film on the core layer; and a plug surrounded by the metal film in the via hole and having a thickness thinner than a thickness of the core layer.

Abstract: A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor.

Abstract: An object of the invention is to provide a method for fabricating a printed wiring board that can suppress warping of the printed wiring board and can improve the yield of semiconductor chip mounting and enhance the reliability of a semiconductor package. The printed wiring board fabrication method according to the invention is a method for fabricating a printed wiring board having a through-hole in a core layer, wherein the printed wiring board fabrication method includes the step of applying a laser from one side of the core layer to a position where the through-hole is to be formed in the core layer and the step of applying a laser to the same position from the opposite side of the core layer.

Abstract: A wiring board includes a substrate, a first conductor layer, a second conductor layer, and a through-via conductor. The substrate has a first surface, a second surface, and at least one through-via. The first conductor layer is formed on the first surface, and the second conductor layer is formed on the second surface. The through-via conductor is formed in the through-via for electrically connecting to the first conductor layer and the second conductor layer. The through-via has a first depressed portion exposed in the first surface, a second depressed portion exposed in the second surface, and a tunnel portion between the first depressed portion and the second depressed portion for connecting the first depressed portion and the second depressed portion. The first depressed portion and the second depressed, portion are non-coaxial.

Abstract: There is provided a printed circuit board, including: a core layer, a conductive via formed in a via hole of the core layer, an upper land formed on an upper surface of the conductive via, and a lower land formed on a lower surface of the conductive via, wherein a center of the upper land and a center of the lower land do not coincide with each other on a plane, so that the center of the upper land and the center of the lower land formed in the printed circuit board are arranged so as not to coincide with each other, thereby increasing durability of an insulating region against pressure in a wet process, and thus damage to the printed circuit board can be reduced.

Abstract: A substrate structure is provided. The substrate structure includes a number of traces, a substrate core, a number of first metal tiles, a number of second metal tiles, a number of first electrically-functioning circuits, and a number of second electrically-functioning circuits. The substrate core has a first surface and a second surface opposite to the first surface. The traces, the first metal tiles, and the first electrically-functioning circuits are disposed on the first surface and add up to a first metal structure proportion, and the second metal tiles and the second electrically-functioning circuits are disposed on the second surface and add up to a second metal structure proportion. The difference between the first metal structure proportion and the second metal structure proportion is within 15%.

Abstract: A circuit board includes at least one core substrate, at least one insulating layer and at least one dielectric sheet. An opening is defined in the insulating layer corresponding to the core substrate. An area of cross-section of the opening is larger than that of the core substrate. The core substrate is received in the opening. The dielectric sheet is positioned on one side surface of the core substrate and the insulating layer. A cavity is defined in the circuit board. A number of pads of the core substrate are exposed via the cavity. The present disclosure also provides a method for manufacturing the circuit board and package structure.

Abstract: A Z-directed signal delay line component for insertion into a printed circuit board while allowing electrical connection to internal conductive planes contained with the PCB. In one embodiment the Z-directed delay line component is housed within the thickness of the PCB allowing other components to be mounted over it. The delay line embodiments include a W-like line and a plurality of spaced apart, semi-circular line segment connected such that current flow direction alternates in direction between adjacent semi-circular line segments, each of which in other embodiments can be varied by use of shorting bars. Several Z-directed delay line components may be mounted into a PCB and serially connected to provide for longer delays. The body may contain one or more conductors and may include one or more surface channels or wells extending along at least a portion of the length of the body. Methods for mounting Z-directed components are also provided.

Abstract: A circuit board comprises a substrate; a through hole penetrating the substrate along with a direction of a thickness thereof; and a through hole conductor covering an inner wall of the through hole. The substrate comprises a first fiber layer, a second fiber layer, and a resin layer arranged between the first fiber layer and the second fiber layer. Each of the first fiber layer and the second fiber layer has a plurality of fibers and a resin arranged among the plurality of the fibers. The resin layer contains a resin and doesn't contain a fiber. The inner wall of the through hole, in a cross-section view along with the direction of the thickness of the substrate, comprises a curved depression in the resin layer.

Abstract: Disclosed is a wiring board with a built-in component and a method for manufacturing the same, the wiring board including: a wiring pattern; an electric/electronic component electrically and mechanically connected with a surface of said wiring pattern; and an insulating layer formed on the same surface of said wiring pattern as said electric/electronic component is connected and configured so as to embed said electric/electronic component, said insulating layer having an insulating resin and a reinforcing material included in the insulating resin, wherein the reinforcing material of said insulating layer exists in the insulating resin without reaching a region of said electric/electronic component in a lateral direction, and wherein the insulating resin of said insulating layer reaches said electric/electronic component so as to adhere to said electric/electronic component.

Abstract: This wiring board is provided with an insulating core substrate, a first conductor pattern, a second conductor pattern, and a conductive material. The first conductor pattern and the second conductor pattern are adhered to the insulating core substrate. The second conductor pattern has a first surface and a second surface. The second conductor pattern has a concavity and a through-hole. The opening of the concavity that opens to the first surface and the opening of the through hole that opens to the first surface are interconnected to each other. The first conductor pattern is positioned at the opening of the concavity. The first conductor pattern and the second conductor pattern are electrically connected by means of the conductive material, which fills from the opening of the through hole that opens to the second surface.

Abstract: A printed wiring board wiring board including a substrate having a first penetrating hole and multiple second penetrating holes formed around the first penetrating hole, a first conductive portion and a second conductive portion formed on one surface of the substrate, a third conductive portion and a fourth conductive portion formed on the opposite surface of the substrate, a first through-hole conductor formed in the first penetrating hole and connecting the first conductive portion and the third conductive portion, and multiple second through-hole conductors formed in the second penetrating holes and connecting the second conductive portion and the fourth conductive portion. The first through-hole conductor and the second through-hole conductors are made of conductive material filled in the first penetrating hole or the second penetrating holes.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

Abstract: A wiring substrate includes a body including first and second surfaces, a trench having an opening on the first surface and including, a bottom surface, a side surface, and a slope surface that connects a peripheral part of the bottom surface to a one end part of the side surface and widens from the peripheral part to the one end part, the one end part being an end part opposite from the first surface, a hole including an end communicating with the bottom surface and another end being open on the second surface, a first layer filling at least a portion of the hole and including a top surface toward the trench, a second layer covering the top surface and formed on at least a portion of the trench except for a part of the side surface, and a third layer covering the second layer and filling the trench.

Abstract: In some embodiments, a system includes a conductor on a first layer of a laminated composite assembly. The laminated composite assembly has an input, an output, a first electrical interconnect which couples the conductor on the first layer of the laminated composite assembly with a second conductor on a second layer of the laminated composite assembly, and a second electrical interconnect which electrically couples the first conductor with the second conductor. A width of the second electrical interconnect is greater than a width of the first electrical interconnect. A resistance of the laminated composite assembly as measured between the electrical input and the electrical output is less than the resistance of the laminated composite assembly as measured between the electrical input and the electrical output if the width of the first electrical interconnect were substantially equal to the width of the second electrical interconnect.

Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.

Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

Abstract: An exemplary multilayer printed circuit board includes a first circuit substrate, a third circuit substrate, a second circuit substrate between the first and third circuit substrates, a first anisotropically conductive adhesive layer between the first and second circuit substrates, and a second anisotropically conductive adhesive layer between the second and third circuit substrates. The first circuit substrate includes a first conductive terminal and a first through hole. The second circuit substrate includes a second conductive terminal and two through holes (i.e. second and third through holes). The third circuit substrate includes a third conductive terminal and a fourth through hole. The first anisotropically conductive adhesive layer fills the first and third through holes to electrically connect the first and second conductive terminals. The second anisotropically conductive adhesive layer fills the second and fourth through holes to electrically connect the second and third conductive terminals.