With Single Conductive Plane (e.g., Tape, Cable) Patents (Class 174/268)
  • Publication number: 20080302564
    Abstract: A substrate for an electronic device package includes an electrically conductive core shaped to define a cavity for receiving an electronic device, a first insulating layer positioned on a first side of the core, and a first contact positioned adjacent to a surface within the cavity. Method of fabricating the substrates is also provided.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Applicant: PPG INDUSTRIES OHIO, INC.
    Inventors: Kevin C. Olson, Thomas W. Goodman, Peter Elenius
  • Publication number: 20080283289
    Abstract: The present invention relates to a printed circuit board. In one embodiment, a printed circuit board includes a dielectric layer and a conductive trace formed on the dielectric layer. The conductive layer includes a first conductive portion, a connecting portion and a second conductive portion. The connecting portion includes a first end and a second end. The first end is connected to the first conductive portion; the second end is connected to the second conductive portion. A width of the connecting portion gradually decreases from the first end to the second end. Reflection and cross talk of signals transmitted in the presented printed circuit board can be reduced.
    Type: Application
    Filed: March 12, 2008
    Publication date: November 20, 2008
    Applicants: FuKui Precision Component (Shenzhen) Co., Ltd., FOXCONN ADVANCED TECHNOLOGY INC.
    Inventors: Dong-Qing He, Ming Wang, Chih-Yi Tu, Cheng-Hsien Lin
  • Patent number: 7435914
    Abstract: A tape substrate having hole(s) formed discontinuously along a bent portion thereof and configured to dissipate stress applied to the bent portion. A tape package using the tape substrate may be connected to a panel and a printed circuit board using an ACF. The tape package may be bent and located behind at least one side of the panel.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: October 14, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ye Cheng Cheng
  • Publication number: 20080186687
    Abstract: A printed circuit board includes a base formed from a plurality of woven fibers, and signal traces laid on the base. Each of the signal traces includes at least a straight line segment. The signal traces are laid on the base in such a manner that the line segments of the signal traces mapped on the base cross the fibers at angles not equal to zero degrees.
    Type: Application
    Filed: June 20, 2007
    Publication date: August 7, 2008
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YU-HSU LIN, CHAN-FEI TAI, JENG-DA WU, CHIH-HANG CHAO
  • Patent number: 7408119
    Abstract: Wire bonds connect current-carrying edges of high-frequency planar conductors to other electrical devices. In one embodiment, planar transmission lines are interconnected using two wire bonds. One bond wire extends from an edge of a first center conductor to a corresponding edge of a second center conductor, and a second bond wire extends from the other edge of the first center conductor to the other edge of the second center conductor. Embodiments include center conductors at different heights and having different widths, and different electrical devices, such as semiconductor integrated circuits. In a particular embodiment, ball bonding is used. In some embodiments, a tack bond is included after a ball bond to allow closer attachment of the bond wire to the edge of the conductor.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: August 5, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Xiaohui Qin, Deji Akinwande, James P. Stephens, Robin Zinsmaster, Jim Clatterbaugh
  • Patent number: 7385829
    Abstract: In one non-limiting aspect thereof this invention provides a structure having a generally planar quadrilateral shape that includes a bottom portion defining a mounting section; a vertical wall portion that extends upwards from the bottom portion and a top-most portion having a generally triangular shape in cross-section and forming along widest portion thereof a lip having a lower surface. The lower surface has a generally rectangular shape characterized by a concave cut-out along a middle portion of an outer edge for reducing an amount of force that is required to be applied to the top-most portion to bend the top-most portion about a central axis thereof.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: June 10, 2008
    Assignee: International Business Machines Corporation
    Inventors: Karl Klaus Dittus, James Goode, Aubrey Lamond Hodges, Timothy Andreas Meserth
  • Patent number: 7371975
    Abstract: A package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Thomas S. Dory, Michael Walk
  • Publication number: 20080054491
    Abstract: A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate.
    Type: Application
    Filed: September 6, 2007
    Publication date: March 6, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Makino, Shigeo Ohshima, Naohisa Okumura
  • Patent number: 7336499
    Abstract: An object of the present invention is to provide a flexible printed wiring board which relaxes stress concentration in the flexible printed wiring board during production steps, thereby preventing wire breakage in inner lead portions and cracking in solder resist which would otherwise be caused during mounting of devices such as IC chips and LSI chips. The flexible printed wiring board of the present invention includes an insulating layer; a wiring pattern formed of a plurality of wirings being juxtaposed, which wiring pattern is formed through patterning a conductor layer stacked on at least one surface of the insulating layer and on which wiring pattern a semiconductor chip is to be mounted; and grid-like dummy patterns formed in a blank area where the wiring pattern is not provided, wherein the dummy patterns are formed in a width direction generally symmetrically with respect to the longitudinal direction of the flexible printed wiring board.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: February 26, 2008
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Kota Hagiwara
  • Patent number: 7324352
    Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: January 29, 2008
    Assignee: Staktek Group L.P.
    Inventor: Paul Goodwin
  • Patent number: 7323642
    Abstract: Provided is a thin printed circuit board (PCB) for manufacturing a chip scale package (CSP). The thin printed circuit board includes a plurality of unit printed circuit boards, each of which is comprised of a circuit pattern, to which a semiconductor chip is adhered, and a substrate surrounding the circuit pattern. The unit printed boards are arranged in a row and includes a support molding, which is spaced a predetermined interval apart from the circuit pattern of each unit printed circuit board on the substrate of each unit printed circuit board and formed in a ring shape along the edge of the thin printed circuit board.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yi-Sung Hwang, Ho-Tae Jin, Hwan-young Jang
  • Patent number: 7307293
    Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: December 11, 2007
    Assignee: Silicon Pipe, Inc.
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Belgacem Haba
  • Patent number: 7292449
    Abstract: A digital apparatus having a cable comprising a plurality of high-speed and low-speed signal carrying conductors, the conductors carrying the low-speed signals are bypassed to a signal ground with selected values of capacitance so as to become virtual signal ground return conductors for the high-speed signal conductors. The selected values of capacitance have a lower impedance then the characteristic impedance of the conductors in the cable. The cable may be a multi conductor cable, a ribbon cable, a flex cable, a twisted pair cable, etc. In a similar fashion, signal conductors on a printed circuit board, not having a separate ground plane layer, may create virtual signal ground returns from the low-speed signal carrying conductors that are proximate to the high-speed signal carrying conductors for reduction of radiated electromagnetic radio frequency interference.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: November 6, 2007
    Assignee: Lexmark International, Inc.
    Inventors: Paul Kevin Hall, Keith Bryan Hardin, Brandon Robert Shields
  • Patent number: 7285729
    Abstract: A printed circuit board includes circuit lines having different transmission characteristics. In the printed circuit board, mounted components are connected to each other at a plurality of points by an anisotropic conductive film (ACF) adhesion by using a flexible circuit board (FPC) which includes transmission lines formed of circuit line patterns having transmission characteristics optimal to signals. This structure enables the printed circuit board to be easily designed, and be also made smaller.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hajime Gushiken
  • Patent number: 7164229
    Abstract: An organic light-emitting display is provided. The organic light-emitting display has a power line divided into multiple sets with a voltage terminal attached to the center of each power line set. Furthermore, all the voltage terminals are coupled to a power supply through a low resistance conductive material medium. With this setup, brightness imbalance between neighboring pixels is minimized.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: January 16, 2007
    Assignee: Au Optronics Corporation
    Inventors: Wei-Chih Lai, Chun-Huai Li
  • Patent number: 7058365
    Abstract: A disposable cellular telephone and business card combination. The cellular telephone circuit is printed on a paper substrate with a conductive ink. A paper microphone diaphragm is attached to one end of the business card and a paper speaker diaphragm is attached to an opposite end of the business card. The microphone and speaker diaphragms are electrically coupled to the circuit, and are attached to the paper substrate in any suitable manner that allows them to vibrate relative thereto. A thin flexible battery cell is formed in the paper substrate at any suitable location so that it doesn't interfere with the position of the circuit, microphone or speaker. A filament antenna is formed in the business card so that it can be extracted therefrom when using the card as a cellular telephone. A switch is provided on the business card that when activated causes a predetermined number to be dialed associated with the text on the business card.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: June 6, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Brett E. Kugler
  • Patent number: 6977347
    Abstract: A flexible printed circuit board. The board includes a first circuit layer, a second circuit layer, a first adhesive layer, a second adhesive layer and an intermediate layer. The second circuit layer face the first circuit layer, and the first adhesive layer is disposed on the first circuit layer. The second adhesive layer, facing the first adhesive layer, is disposed on the second circuit layer. The intermediate layer, having a plurality of first through holes, is disposed between the first circuit layer and the second circuit layer. The first adhesive layer adheres directly to the second adhesive layer through the first through holes.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: December 20, 2005
    Assignee: Darfon Electronics Corp
    Inventor: Chih-Hsiang Chiang
  • Patent number: 6914196
    Abstract: A reel-deployed printed circuit board for chip-on-board (COB) packages and a method for manufacturing COB packages using the reel printed circuit board are disclosed. The novel circuit board comprises an elongated, flexible base board and a plurality of unit boards defined within it by a plurality of slits cut through it. Each unit board comprises a plurality of bonding pads on its top surface, a plurality of contacts on its bottom surface, and a plurality of via holes that electrically connect the contacts to the bonding pads. The circuit board further comprises connection bars that connect the unit boards to the flexible base board. The method for manufacturing COB packages using the reel-deployed printed circuit board comprises the steps of forming the reel printed circuit board, attaching a semiconductor chip to it, connecting the semiconductor chip to the bonding pads, encapsulating the semiconductor chip, and separating the COB packages from the reel printed circuit board.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung Dae Cho
  • Patent number: 6885549
    Abstract: A flexible printed circuit improves data transfer rates by disposing ground wires in a ground plane proximate to signal wires disposed in a signal channel plane. One or more ground wires is associated with each signal wire pair or each signal wire for imaging of the return currents of the signal pairs. An overlapping alignment minimizes loop area between a ground wire and its associated signal wire. An offset alignment provides a reduced loop area and reduced breakage risk since movement of the flexible circuit does result in compression of the signal wire and its associated ground wire. A combination of overlapping and offset alignment balances signal transfer effectiveness with breakage risk by offsetting ground and signal wires is stress sensitive regions and overlapping ground and signal wires in stress tolerant regions.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 26, 2005
    Assignee: Dell Products L.P.
    Inventor: Gary S. Thomason
  • Patent number: 6797891
    Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure, a microstrip structure, a stripline structure, or the like. The cable can be coupled to destination components using a variety of connection techniques, e.g., direct bonding to a circuit substrate, direct soldering to a flip chip, mechanical attachment to a component, or integration with a circuit substrate. The cable can also be terminated with any number of known or standardized connector packages, e.g., SMA, GPPO, or V connectors.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: September 28, 2004
    Assignee: Applied Micro Circuits Corporation
    Inventors: James Leroy Blair, Oswin M. Schreiber, Jeffrey Thomas Smith
  • Patent number: 6756663
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Publication number: 20040045737
    Abstract: A process for manufacturing a flexible wiring board according to the present invention comprises growing metal bumps 16 using a mask film patterned by photolithography. Fine openings can be formed with good precision, therefore, fine metal bumps 16 can be formed with good precision because laser beam is not used to form openings in a polyimide film. After metal bumps 16 have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to expose the tops of metal bumps 16.
    Type: Application
    Filed: August 14, 2003
    Publication date: March 11, 2004
    Applicant: SONY CHEMICALS CORP.
    Inventors: Hiroyuki Hishinuma, Hideyuki Kurita, Ryo Ito, Masayuki Nakamura
  • Publication number: 20040045157
    Abstract: A flexible wiring board according to the present invention comprising growing metal bumps 16 using a mask film patterned by photolithography. Fine openings can be formed with good precision, therefore, fine metal bumps 16 can be formed with good precision because laser beam is not used to form opening in a polyimide film. After metal bumps 16 have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to exposed the tops of metal bumps 16.
    Type: Application
    Filed: August 14, 2003
    Publication date: March 11, 2004
    Applicant: SONY CHEMICALS CORP.
    Inventors: Hiroyuki Hishinuma, Hideyuki Kurita, Ryo Ito, Masayuki Nakamura
  • Patent number: 6700079
    Abstract: Upper and lower planar circuit boards are connected in spaced apart parallel relationship by a plurality of contacts each made of a conductive pin, insulative collar and solder ball. The upper ends of the pins are inserted in plated though holes in the upper circuit board and soldered thereto by wave soldering or re-flow. The pins have shoulders to establish the penetration of the pins into the upper circuit board. The lower ends of the pins are bonded to conductive pads on the lower circuit board via the solder balls that are maintained in substantially spherical configuration by the insulative collars and accommodate variations in board co-planarity or pin length. Where the lower ends of the pins do not contact their corresponding conductive pads the volume of solder in the solder balls allows reliable fillet solder joints to be formed.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: March 2, 2004
    Assignee: Autosplice, Inc.
    Inventors: Robert M. Bogursky, Craig M. Kennedy, Kenneth Krone, Joseph J. Lynch
  • Patent number: 6683260
    Abstract: Transmission line structure is composed of a pair of signal conductors which are embedded in one wiring region of a dielectric layer and a thickness in height of the signal conductor is larger than a width, and is constituted so that a coupling impedance between the adjacent signal conductors is lower than a coupling impedance between the signal conductor and another conductor formed in another wiring region, and thus to provide a multi-layer wiring board having a transmission line structure of high wiring density and excellent transmission characteristic.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: January 27, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Shimamoto, Kazufumi Yamaguchi, Masahide Tsukamoto, Fumikazu Tateishii, Yutaka Taguchi
  • Publication number: 20040007383
    Abstract: A package for mounting a semiconductor device has a surface exposed to an atmosphere. The exposed surface is covered with a covering material such as a paint, a tape or a seal.
    Type: Application
    Filed: April 10, 2003
    Publication date: January 15, 2004
    Inventors: Morihiko Mouri, Sadayuki Okuma, Yasushi Takahashi, Takao Ono, Yosihiro Sakaguchi, Atsushi Nakamura, Toshio Miyazawa
  • Patent number: 6627824
    Abstract: A support circuit is adapted to be mechanically and electrically coupled to a semiconductor chip such that the support circuit and the chip in combination form a semiconductor chip assembly. The support circuit includes an insulative base and a conductive trace embedded in the insulative base. The conductive trace is a single continuous piece of metal, the conductive trace includes a pillar that extends above the insulative base and a routing line that is substantially covered by and extends below the insulative base, and an opening in the routing line has tapered sidewalls and a diameter that increases as height increases.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: September 30, 2003
    Inventor: Charles W. C. Lin
  • Publication number: 20030136576
    Abstract: A printed circuit support comprises a substrate made of an insulating material, at least one electric current conveying path consisting of a metallization of the substrate, and at least one connection arrangement contiguous with the conveying path. The connection arrangement comprises at least one strip of metallized flexible plastic that forms a section of conductor and is electrically connected to the conveying path.
    Type: Application
    Filed: November 8, 2002
    Publication date: July 24, 2003
    Applicant: NEXANS
    Inventor: Bertrand Joly
  • Patent number: 6576992
    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CSPs are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: June 10, 2003
    Assignee: Staktek Group L.P.
    Inventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Jr., Julian Dowden, Jeff Buchle
  • Patent number: 6498309
    Abstract: The present invention provides a circuit board, which can reduce a conduction loss and generate no trouble in electric/electronic apparatuses in the case of being mounted to electric/electronic apparatuses adapting a high frequency current. A circuit board 1 is formed a manner that a copper foil layer 2 and a copper layer 3 are laminated on a base material 5 made of polytetrafluoroethylene so as to form a predetermined circuit, and further, a tin plating layer 4 is laminated on these copper layers.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: December 24, 2002
    Assignee: Maspro Denkoh Co., LTD
    Inventor: Takehito Kuno
  • Patent number: 6495768
    Abstract: A tape carrier package that is capable of preventing a short between adjacent pads in boning the tape carrier package mounted with an integrated circuit onto a liquid crystal panel and a print wiring substrate. In the package, a base film is mounted with an integrated circuit. Input pads are connected to the integrated circuit to input an external input signal to the integrated circuit. Each of output pads has a first portion extended to the integrated circuit, and a second portion extended to the first portion to have a narrower line width than the first portion.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: December 17, 2002
    Assignee: LG. Philips LCD Co., LTD
    Inventor: Hyoung Soo Cho
  • Publication number: 20020171140
    Abstract: A package for mounting a plurality of semiconductor chips on one package and minimizing a mounted area, and a method of manufacturing the same is provided. The package includes a film on which a plurality of semiconductor chips are mounted, and the film is folded in a predetermined direction so as to package the plurality of semiconductor chips in one package. The method of manufacturing the package includes mounting a plurality of semiconductor chips on a film and folding the film in a predetermined direction and packaging the plurality of semiconductor chips in one package. The film is folded two or more times such that at least one semiconductor chip is interposed between surfaces of the film. The package can be a tape carrier package (TCP) or a chip-on-film (COF) package.
    Type: Application
    Filed: January 14, 2002
    Publication date: November 21, 2002
    Applicant: Samsung Electronics Co. Ltd.
    Inventor: Bum-Yeul Park
  • Patent number: 6469261
    Abstract: A wiring unit is provided, by which the cost of the manufacture and assembly thereof can be prevented from raising and the miniaturization thereof can be attained. The wiring unit 1 includes a first flexible insulating sheet 2, a plurality of flexible band-shaped conductors 3 and a plurality of enameled wires 4. The band-shaped conductors 3 are arranged in parallel with each other on the surface 2a of the first insulating sheet 2. Wires 16 are connected to both ends of the band-shaped conductor 3. The enameled wire 4 electrically connects a plurality of the band-shaped conductors 3 with each other. The first insulating sheet 2 is rolled up around an axis P parallel to the band-shaped conductor 3 from one end 5 to the other end 6 of the first insulating sheet 2. The first insulating sheet 2 is rolled up into a roll, thereby the wiring unit 1 is produced.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: October 22, 2002
    Assignee: Yazaki Corporation
    Inventors: Makoto Yamanashi, Takao Murakami, Hiroyuki Suzuki
  • Patent number: 6469903
    Abstract: A semiconductor device of the present invention comprises a flexible printed circuit having a first area part located in the center thereof, a second area part provided continuous thereto, and a third area part provided continuous to the first area part; a wiring pattern formed on a surface of the above-described flexible printed circuit; a semiconductor element mounted on a surface of the second area part; and a second semiconductor element mounted on a surface of the third area part, wherein the second area part is folded to a face side of a center area part, and the third area part is folded to a rear side of the second area part.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: October 22, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Yoichiro Kondo
  • Patent number: 6462955
    Abstract: A component alignment casing system for connecting circuits, and a method for making or assembling the component alignment casing system is disclosed. The system has at least one surface mountable component which has a plurality of exposed leads, a prepared component which has a plurality of exposed traces, an alignment base onto which the prepared component and the surface mountable component are laid, and a compressive cover that attaches to said alignment base. The alignment base has a plurality of alignment ribs to isolate and align the exposed traces of the prepared component. The prepared component and surface mountable components are electrically connected and attached together, preferably by soldering.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: October 8, 2002
    Assignee: Miraco, Inc.
    Inventor: Jonathan F. Roberts
  • Patent number: 6444923
    Abstract: At one end of a printed wiring board, there is formed a narrow-pitched electrode pattern and engagement patterns made of the same material as that of the electrode pattern. At one end of an FPC which is to be connected with the printed circuit board, there is formed a narrow-pitched electrode pattern and engagement patterns made of the same material as that of the electrode pattern. The engagement patterns in the printed wiring board being engageable with the engagement patterns in the FPC. When the two engagement patterns are engaged with each other, the electrode pattern of the printed wiring board is electrically connected with the electrode pattern of the FPC.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: September 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Shigeo Iriguchi, Satoshi Watanabe, Yoshitaka Muraoka
  • Publication number: 20020092678
    Abstract: The invention relates to a method and an arrangement implementing the method for installing a connector and a cable, in which method the connector is fastened at its middle part with a fastening agent, the rest of the connector is fastened with fastening means and the cable is connected to the connector. Further, in the method, the middle part of the connector separate from the rest of the connector is fastened with a fastening agent, the rest of the connector is fastened to the cable, the cable is connected to the separate middle part of the connector, and the cable is fastened through the rest of the connector with fastening means.
    Type: Application
    Filed: February 5, 2002
    Publication date: July 18, 2002
    Inventors: Pasi Lehtonen, Jari Lapinlampi, Matti Lehto, Tero Saarenpaa, Arto Kuosmanen
  • Patent number: 6420659
    Abstract: A flexible wiring board piece which can prevent a short circuit because of scattering of the connecting terminal parts and facilitate cutting when cut at an intermediate connecting terminal part. A constitution wherein circuit wiring patterns 13 [131-134] are coated with insulating films 11 and 14; connecting terminal parts 17 of the circuit wiring patterns 13 and cut parts 18 of the circuit wiring patterns 13, which are located apart form the connecting terminal parts 17, are exposed in both faces via openings 20a, 20b, 21a and 21b formed in insulating films 11 and 14; and narrow parts for cutting are formed in the cut parts 18 facing the openings 20b and 20b.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: July 16, 2002
    Assignee: Sony Chemicals Corporation
    Inventors: Akira Tsutsumi, Hideyuki Kurita
  • Patent number: 6388888
    Abstract: A semiconductor device comprising a patterned wiring including a connector for external connection formed on an elongate base film, a semiconductor element or the semiconductor element and a component other than the semiconductor element mounted on and electrically connected with a portion for connection of the patterned wiring, an elongate reinforcement member provided on a surface of the base film opposite to a surface on which the patterned wiring is formed, the reinforcement member having sprocket holes at positions corresponding to the lengthwise sides of the base film, wherein the reinforcement member is further provided on said opposite base film surface in a region corresponding with a region on which the connector for external connection is formed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: May 14, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiharu Seko, Kenji Toyosawa
  • Patent number: 6353188
    Abstract: A circuit assembly having a plurality of tracks formed from a conductive material secured to a flexible substrate by an adhesive. The adhesive is selected to withstand high temperatures and strains caused by folding the flexible substrate.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: March 5, 2002
    Assignee: Lear Corporation
    Inventor: Salvador Gomez Fernandez
  • Publication number: 20020023774
    Abstract: A circuit board substrate assembly includes a generally planar circuit board substrate material having a longitudinal axis extending along a length of the substrate material between a first end and a second end thereof. The circuit board substrate material further has a first edge and a second edge extending along the length of the circuit board substrate material between the first end and the second end. A plurality of openings are defined in the substrate material. Each opening extends between a first distance from the first edge of the circuit board substrate and a second distance from the second edge of the circuit board substrate. Further, each opening separates adjacent circuit forming regions lying along the longitudinal axis and has first and second opposing end portions.
    Type: Application
    Filed: May 25, 2001
    Publication date: February 28, 2002
    Inventors: Zane Drussel, Derek Hinkle
  • Patent number: 6344613
    Abstract: The present invention provides an automotive circuit assembly having a plurality of circuit segments. Each circuit segment has one or more conductive buses operatively positioned between a dielectric substrate and a protective cover. The protective cover selectively exposes a portion of the one or more conductive buses. The one or more conductive buses of one circuit segment is selectively joined to one or more conductive buses of another circuit segment to cooperatively form an electrical circuit assembly.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: February 5, 2002
    Assignee: Visteon Global Technologies, Inc.
    Inventor: Michael M. Kolodziej
  • Publication number: 20010050184
    Abstract: In a connecting structure, an end portion (11A) of a FFC (11), including a plurality of parallel conductors (12) held between base films (13 and 14), is joined by soldering to wiring terminal patterns (16) formed on a surface of a wiring board (15). The lower covering film (13), which is to be joined to the wiring terminal patterns (16) at the end portion (11A) of the FFC (11), is removed over a length corresponding to a region of soldering levelers (18) formed respectively on the wiring terminal patterns (16). The upper covering film (14) is removed at the end portion (11A) over a region closer to the end of the flat circuit member (11) than an end of the lower covering film (13), and covers part of the wiring terminal patterns (16).
    Type: Application
    Filed: June 12, 2001
    Publication date: December 13, 2001
    Applicant: Yazaki Corporation
    Inventor: Hideki Adachi
  • Patent number: 6326553
    Abstract: A flexible circuit board which can be assembled into a head gimbal assembly of a hard disk drive. The flexible circuit board may have a conductive tab that is electrically connected to a pre-amp pad and a head pad of the circuit board. The head pad may be connected to a head. The conductive tab may be grounded during handling of the flexible circuit board. Any electrostatic discharge on the head may be grounded through the conductive tab.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: December 4, 2001
    Assignee: Samsung Electronics, Co., Ltd
    Inventors: Pyongwon Yim, Andrew S. Kao, Hyung Jai Lee
  • Publication number: 20010025726
    Abstract: The present invention provides a circuit board, which can reduce a conduction loss and generate no trouble in electric/electronic apparatuses in the case of being mounted to electric/electronic apparatuses adapting a high frequency current.
    Type: Application
    Filed: February 7, 2001
    Publication date: October 4, 2001
    Inventor: Takehito Kuno
  • Publication number: 20010017765
    Abstract: An improved bonding strip for a printed circuit to facilitate quality inspection. The bonding strip has functional regions and non-functional regions. A functional region is indicated by an area of the bonding strip having a first dimension in width. A non-functional region is indicated by an area of the bonding strip having a second dimension in width. The first dimension may be either wider or narrower than the second dimension.
    Type: Application
    Filed: January 10, 2001
    Publication date: August 30, 2001
    Inventors: Marshall L. Brown, James A. Busby, Raymond A. Phillips, John A. Potenza, Jirina D. Shupp, J. Robert Young
  • Patent number: 6281451
    Abstract: An improved flexible cable construction is provided which includes two layers of conductor traces arranged alternately with three layers of dielectric material in a flattened configuration between ground plane outside metal surfaces. Each of the conductor layers includes alternating signal traces and ground traces. In an exemplary embodiment, vias are arranged in first and second planes through the cable. Longitudinal vias maintain the potential of ground planes at the same level as well as improving shielding effectiveness along an edge or thickness cross-section of the cable. Transverse vias are implemented to minimize antenna effects due to large openings at the point of cable entry into a sheet metal box containing high frequency electronics.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: August 28, 2001
    Assignee: International Business Machines Corporation
    Inventors: Hong H. Chan, Qinglun Chen, Emile Joseph Tayar
  • Patent number: 6281449
    Abstract: A printed board (5) for mounting electronic component, a method for making the same, and an arrangement for connecting a conductive elements (8, 8′) to the printed board are provided. The printed board includes an insulating substrate (50), and at least one metal terminal (53, 54). The substrate is formed with at least one opening (51, 52) penetrating the substrate. The metal terminal is fixed to the substrate so as to bridge the opening, without projecting out of the substrate.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: August 28, 2001
    Assignee: Rohm Co., Ltd.
    Inventors: Satoshi Nakamura, Masaharu Tanaka
  • Publication number: 20010010270
    Abstract: A flexible circuit board with specific shielding planes is used for low voltage differential transmission mode circuits. Both the impedance and the transmission time for the transmission line in the circuit board are controlled by shielding planes with varied void opening patterns. Capacitance and slow wave effects related to the combination of void opening patterns and the location configuration related to locations of void opening patterns are used to improve the impedance and transmission timing for the transmission line in the circuit board.
    Type: Application
    Filed: February 5, 2001
    Publication date: August 2, 2001
    Inventors: Gwun-Jin Lin, Chi-Kuang Hwang, Ching-Cheng Tien
  • Publication number: 20010010271
    Abstract: A flexible circuit board with specific shielding planes is used for low voltage differential transmission mode circuits. Both the impedance and the transmission time for the transmission line in the circuit board are controlled by shielding planes with varied void opening patterns. Capacitance and slow wave effects related to the combination of void opening patterns and the location configuration related to locations of void opening patterns are used to improve the impedance and transmission timing for the transmission line in the circuit board.
    Type: Application
    Filed: February 5, 2001
    Publication date: August 2, 2001
    Inventors: Gwun-Jin Lin, Chi-Kuang Hwang, Ching-Cheng Tien