On Lead Frame Patents (Class 174/529)
  • Patent number: 8593817
    Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Thilo Stolze
  • Patent number: 8513542
    Abstract: An integrated circuit leaded stacked package system includes forming a no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 20, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano
  • Patent number: 8383962
    Abstract: A packaged semiconductor is disclosed. The packaged semiconductor comprises a conductive integral frame that includes an inner portion and a ring portion encircling the inner portion, a semiconductor die that is mounted to a first surface of the inner portion of the conductive frame, and a casing that supports the conductive frame and covers the semiconductor die. Sections of the conductive frame that connect the inner portion to the ring portion are removed after the casing is applied to the conductive frame.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: February 26, 2013
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8253041
    Abstract: An electronic element packaging module including a lead frame, an insulating layer and at least one electronic element is provided. The lead frame is a patterned metal sheet and has a first surface, a second surface opposite thereto and a through trench passing from the first surface to the second surface. A substrate portion and a plurality of lead portions around the substrate portion of the lead frame are defined by the through trench. The second surface of the lead frame is exposed outside the electronic element packaging module. The insulating layer disposed in the through trench has a third surface and a forth surface substantially coplanar with the first and the second surfaces, respectively. The electronic element disposed on the first surface is coupled to the lead frame.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: August 28, 2012
    Assignee: Cyntec Co., Ltd.
    Inventors: Da-Jung Chen, Chi-Feng Huang, Yi-Tsung Chen, Huei-Ren You, Jeng-Jen Li
  • Patent number: 8240029
    Abstract: A method for forming an isolated inner lead from a leadframe is revealed. The leadframe primarily comprises a plurality of leads, the isolated inner lead, and an external lead. Each lead has an inner portion having a finger. The isolated inner lead having two fingers is completely formed inside a molding area and is made of the same metal leadframe as the leads. One finger of the isolated inner lead and the fingers of the leads are linearly arranged. The other finger of the isolated inner lead is adjacent to a finger of the external lead. At least one of the inner portions divides the isolated inner lead from the external lead. The isolated inner lead is integrally connected to an adjacent one of the inner portions by a connecting block. A tape-attaching step is performed to mechanically connect the isolated inner lead where two insulating tapes are attached in a manner that the connecting block can be removed.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: August 14, 2012
    Assignee: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Yu-Mei Hsu
  • Publication number: 20120112333
    Abstract: A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.
    Type: Application
    Filed: August 16, 2011
    Publication date: May 10, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Qiang Liu, Qingchun He, Zhaojun Tian
  • Publication number: 20120103682
    Abstract: A lead frame includes an insulative housing defining a cavity, a plurality of leads mounted with the housing and a metal cup mounted within the housing. Each lead includes contacting section exposed in the cavity. The metal cup includes a bottom plate and an inclined cup wall. The bottom plate is formed with a flange extending outwardly therefrom such that a slot is defined between the flange and the cup wall to receive the resin material of the housing.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 3, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YEN-CHIH CHANG, CHIH-PI CHENG
  • Patent number: 8157415
    Abstract: A method for making a light emitting diode lighting module includes steps of: (a) packaging a plurality of light emitting diode dies respectively on a plurality of die-mounting parts of a metal lead frame to form a plurality of light emitting diodes, respectively; and (b) cutting off supporting parts of the lead frame so as to form a connecting structure through which the light emitting diodes are connected to each other in one of serial, parallel, and serial-and-parallel connecting manners.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: April 17, 2012
    Assignee: Bright LED Electronics Corp.
    Inventors: Ching-Lin Tseng, Yu-Shen Chen, Ming-Li Chang
  • Patent number: 8116102
    Abstract: An electronic device which comprises a lead frame comprising at least one clip, a capacitor comprising at least one terminal, the at least one terminal being received in the at least one clip, and a semiconductor chip attached to the lead frame.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: February 14, 2012
    Assignee: Infineon Technologies AG
    Inventors: Chee Peng Wong, Tiam Sen Ong, Guan Choon Tee
  • Patent number: 7993092
    Abstract: Provided are a moving carrier for a lead frame, and a method of moving a lead frame using the moving carrier. The moving carrier includes a base which supports the lead frame including a body and a chip attach pad on which a chip is disposed. The moving carrier includes a groove portion which is integrated with a part of the base and contains the chip attach pad of the lead frame. The lead frame is inserted or withdrawn into or out from a magazine using the moving carrier and thus without deformation of the lead frame or damage to the chip.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: August 9, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yibo Liu, Qiang Chen
  • Patent number: 7968807
    Abstract: A package apparatus has a base coupled with a lid to form a leadframe package. The package has first and second exterior surfaces with respective first and second contact patterns. The first and second contact patterns are substantially electrically identical to permit the package to be either vertically or horizontally mounted to an underlying apparatus.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 28, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Timothy R. Spooner, Nelson Kuan
  • Patent number: 7935899
    Abstract: Provided is a circuit device in which an electronic circuit to be incorporated therein operates stably. A hybrid integrated circuit device includes multiple circuit boards which are disposed on approximately the same plane. An electronic circuit including a conductive pattern and a circuit element is formed on each top surface of the circuit boards. Furthermore, these circuit boards are integrally supported by a sealing resin. Moreover, a lead connected to the electronic circuit formed on the surface of the circuit board is led out from the sealing resin to the outside.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takukusaki, Noriaki Sakamoto
  • Publication number: 20100319987
    Abstract: An electronic device package 100 comprising a lead frame having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 23, 2010
    Applicant: LSI Corporation
    Inventors: Larry W. Golick, Qwai Hoong Low, John W. Osenbach, Matthew E. Stahley
  • Patent number: 7739791
    Abstract: A method of producing an overmolded electronic assembly including a circuit board and a flexible circuit interconnect by fixturing the assembly in a mold cavity such that a portion of the flexible circuit protrudes from the mold, and providing a compressible elastomeric interface between the mold and the flexible circuit to seal off the mold cavity and protect the flexible circuit from damage due to the clamping force of the mold. The portion of the flexible circuit within the mold cavity is pre-coated with a material that ensures good adhesion with the molding compound, and a heat exchanger thermally coupled to the portion of the flexible circuit that protrudes from the mold protects the flexible circuit from damage due to thermal conduction from the mold and mold compound.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: June 22, 2010
    Assignee: Delphi Technologies, Inc.
    Inventors: Scott D. Brandenburg, David A Laudick, Gary E. Oberlin
  • Patent number: 7504281
    Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: March 17, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Rajeev Joshi
  • Patent number: 7497011
    Abstract: A hoop molding method comprises forming, in the frame portions, connection portions that link, to the frame portions, at least one molded portion of the at least one bent molded portion or at least another molded portion other than the at least one bent molded portion such that it is displaceable in a direction toward another molded portion along the width direction of the parent material, and displacing the at least one molded portion of the at least one bent molded portion or the at least another molded portion other than the at least one bent molded portion toward the another molded portion after the bending.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho
    Inventors: Koji Suzuki, Fusatomo Miyake
  • Patent number: 7439452
    Abstract: In a transfer-mold configuration of an automotive electronic control unit, the thermal expansion coefficient of the circuit board is made apparently equal to that of the base member to suppress excessive stresses between them. The circuit board and the base member are placed in the center of the transfer-mold structure to make thermal stresses symmetrical and thus suppress strains.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: October 21, 2008
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuhiro Masuda