Semiconductor Patents (Class 204/192.25)
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Patent number: 7146722Abstract: A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad structure are provided. Each of the bond pads comprise stacked metal layers, at least one lower metal layer and an upper metal layer. When the two pads are connected by a conductive material, they function as a single pad. The lower metal layer of one of the bond pads forms an extension that extends beneath the upper metal layer of the other of the bond pad. The lower metal extension functions to block the etching of a dielectric layer that is put down over the upper metal layers and the underlying substrate, for example, during a passivation etch to form the bond pad opening, to protect the substrate from damage.Type: GrantFiled: March 14, 2003Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventor: Guy Perry
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Patent number: 7037595Abstract: A thin layer of hafnium oxide or stacking of thin layers comprising hafnium oxide layers for producing surface treatments of optical components, or optical components, in which at least one layer of hafnium oxide is in amorphous form and has a density less than 8 gm/cm3. The layer is formed by depositing on a substrate without energy input to the substrate.Type: GrantFiled: November 15, 1999Date of Patent: May 2, 2006Assignee: Commissariat a l'Energie AtomiqueInventors: Bernard Andre, Jean Dijon, Brigitte Rafin
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Patent number: 6887353Abstract: Disclosed herein is a barrier layer structure useful in forming copper interconnects and electrical contacts of semiconductor devices. The barrier layer structure comprises a first layer of TaNx which is applied directly over the substrate, followed by a second layer of Ta. The TaNx/Ta barrier layer structure provides both a barrier to the diffusion of a copper layer deposited thereover, and enables the formation of a copper layer having a high <111> crystallographic content so that the electromigration resistance of the copper is increased. The TaNx layer, where x ranges from about 0.1 to about 1.5, is sufficiently amorphous to prevent the diffusion of copper into the underlying substrate, which is typically silicon or a dielectric such as silicon dioxide.Type: GrantFiled: December 19, 1997Date of Patent: May 3, 2005Assignee: Applied Materials, Inc.Inventors: Peijun Ding, Tony Chiang, Barry L. Chin
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Patent number: 6758947Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.Type: GrantFiled: June 20, 2001Date of Patent: July 6, 2004Assignee: Applied Materials, Inc.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
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Patent number: 6756160Abstract: An ion-beam deposition process for fabricating attenuating phase shift photomask blanks, capable of producing a phase shift of 180°, and which can provide tunable optical transmission at selected lithographic wavelengths <400 nm, comprising at least one layer of material of general formulae MzSiOxNy or MzAlOxNy, is described.Type: GrantFiled: April 16, 2002Date of Patent: June 29, 2004Assignee: E.I. du Pont de Nemours. and CompanyInventor: Peter Francis Carcia
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Patent number: 6756161Abstract: An ion-beam film deposition process is described for fabricating binary photomask blanks for selected lithographic wavelengths <400 nm, the said film essentially consisting of the MOxCyNz compound where M is selected from chromium, molybdenum, tungsten, or tantalum or combination thereof in a single layer or a multiple layer configuration.Type: GrantFiled: April 16, 2002Date of Patent: June 29, 2004Assignee: E. I. du Pont de Nemours and CompanyInventors: Peter Francis Carcia, Laurent Dieu
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Patent number: 6746960Abstract: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (1810) is sensed by sensors (1820) that output electrical signals in response to the analyte. The electrical signals are preprocessed (1830) by filtering and amplification. In an embodiment, this preprocessing includes adapting the sensor and electronics to the environment in which the analyte exists. The electrical signals are further processed (1840) to classify and identify the analyte, which may be by a neural network.Type: GrantFiled: January 18, 2002Date of Patent: June 8, 2004Assignee: California Institute of TechnologyInventor: Rodney M. Goodman
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Patent number: 6726812Abstract: An ion beam sputtering apparatus comprising: a first means for generating an ion beam and directing said ion beam in a prescribed direction, a second means for supporting a target at a position where said target is capable of exposing said ion beam irradiated in said prescribed direction and of being sputtered by said ion beam, a third means for supporting an electrically conductive substrate having a semiconductor layer on which a component sputtered from said target is to be deposited, and a fourth means for making said electrically conductive substrate have a non-earth potential. A method for forming a transparent and electrically conductive film on an electrically conductive substrate having a semiconductor layer, which is based on said ion beam sputtering apparatus. A process for producing a semiconductor device by forming a transparent and electrically conductive film on a semiconductor layer for said semiconductor device, which is based on said ion beam sputtering apparatus.Type: GrantFiled: March 4, 1998Date of Patent: April 27, 2004Assignee: Canon Kabushiki KaishaInventor: Noboru Toyama
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Patent number: 6722942Abstract: Various embodiments of a planarization device and methods of using the same are provided. In one aspect, a device for planarizing a surface of a semiconductor workpiece is provided that includes a table for holding a quantity of an electrically conducting solution thereon. A member is included for holding the semiconductor workpiece such that the surface is in contact with the solution and operates as a working electrode. The member has a first conductor for establishing electrical connection with the semiconductor workpiece. A counter electrode is provided for making electrical connection with the solution and a reference electrode is provided for making electrical connection with the solution with a known electrode potential. A power source is operable to control the electric potential between the working electrode and the counter electrode. Slurry consumption may be dramatically reduced and static etch rate due to aborts may be virtually eliminated.Type: GrantFiled: May 21, 2001Date of Patent: April 20, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Christopher H. Lansford, Jeremy S. Lansford, Bradley J. Yellitz
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Publication number: 20040040835Abstract: A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventors: Jiutao Li, Keith Hampton, Allen McTeer
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Patent number: 6652717Abstract: Variable reactances in an impedance-matching box for an RF coil, in a plasma deposition system for depositing a film of sputtered target material on a substrate, can be varied during the deposition process so that the RF coil and substrate heating, and the film deposition, are more uniform due to “time-averaging” of the RF voltage distributions along the RF coil.Type: GrantFiled: May 16, 1997Date of Patent: November 25, 2003Assignee: Applied Materials, Inc.Inventor: Liubo Hong
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Patent number: 6632583Abstract: The present invention relates to an optical recording medium having a protective layer and a phase-change recording layer on a substrate, said protective layer containing a metallic oxysulfide and an optical recording medium having a protective layer and a phase-change recording layer, said protective layer being formed by sputtering using a target comprising a metallic oxysulfide.Type: GrantFiled: December 5, 2000Date of Patent: October 14, 2003Assignee: Mitsubishi Chemical CorporationInventors: Haruo Kunitomo, Takashi Ohno
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Patent number: 6599399Abstract: A deposition system in a semiconductor fabrication system provides at least one electron gun which injects energetic electrons into a semiconductor fabrication chamber to initiate and sustain a relatively high density plasma at extremely low pressures. In addition to ionizing atoms of the extremely low pressure gas, such as an argon gas at 100 microTorr, for example, the energetic electrons are also believed to collide with target material atoms sputtered from a target positioned above a substrate, thereby ionizing the target material atoms and losing energy as a result of the collisions. Preferably, the electrons are injected substantially tangentially to the walls of a chamber shield surrounding the plasma in a magnetic field generally parallel to a central axis of the semiconductor fabrication chamber connecting the target to and the substrate.Type: GrantFiled: March 7, 1997Date of Patent: July 29, 2003Assignee: Applied Materials, Inc.Inventors: Zheng Xu, Seshadri Ramaswami
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Patent number: 6579426Abstract: Capacitances in an impedance-matching box for an RF coil, in a plasma deposition system for depositing a film of sputtered target material on a substrate, can be varied during the deposition process so that the RF coil and substrate heating, and the film deposition, are more uniform due to “time-averaging” of the RF voltage distributions along the RF coil.Type: GrantFiled: May 16, 1997Date of Patent: June 17, 2003Assignee: Applied Materials, Inc.Inventors: James van Gogh, John C. Forster
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Publication number: 20030096098Abstract: A non-single crystalline semiconductor material includes coordinatively irregular structures characterized by distorted chemical bonding, reduced dimensionality and novel electronic properties. A process for forming the material permits variation of the size, concentration and spatial distribution of coordinatively irregular structures. The electronic properties of the material can be changed by controlling the characteristics of the coordinatively irregular structures.Type: ApplicationFiled: October 5, 2001Publication date: May 22, 2003Inventors: Stanford R. Ovshinsky, Boil Pashmakov, David V. Tsu
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Patent number: 6555221Abstract: A method for forming an ultra microparticle-structure composed of ultra microparticles including the steps of: forming on a substrate higher wettability parts and lower wettability parts to a material to be deposited, depositing on the substrate the material to be deposited to form particles made of the material on the substrate, and accumulating the particles in the higher wettability parts to form the ultra microparticle-structure composed of the ultra microparticles.Type: GrantFiled: October 25, 1999Date of Patent: April 29, 2003Assignee: The University of TokyoInventors: Hiroshi Komiyama, Hiroaki Shirakawa, Toshio Osawa
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Patent number: 6537429Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber includes a diamond containing surface and process for manufacture thereof.Type: GrantFiled: December 29, 2000Date of Patent: March 25, 2003Assignee: Lam Research CorporationInventors: Robert J. O'Donnell, John E. Daugherty, Christopher C. Chang
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Patent number: 6533907Abstract: A specialized physical vapor deposition process provides dense amorphous semiconducting material with exceptionally smooth morphology. In particular, the process provides dense, smooth amorphous silicon useful as a hard mask for etching optical and semiconductor devices and as a high refractive index material in optical devices. DC sputtering of a planar target of intrinsic crystalline semiconducting material in the presence of a sputtering gas under a condition of uniform target erosion is used to deposit amorphous semiconducting material on a substrate. DC power that is modulated by AC power is applied to the target. The process provides dense, smooth amorphous silicon at high deposition rates. A method of patterning a material layer including forming a hard mask layer of amorphous silicon on a material layer according to the present DC sputtering process is also provided.Type: GrantFiled: January 19, 2001Date of Patent: March 18, 2003Assignee: Symmorphix, Inc.Inventors: Richard E. Demaray, Jesse Shan, Kai-An Wang, Ravi B. Mullapudi
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Publication number: 20030039866Abstract: A Group III nitride compound semiconductor thin film which can be deposited on any given substrate to have uniform film quality and excellent crystalline, and a deposition method thereof. A semiconductor device and a manufacturing method thereof. A poly-crystalline Group III nitride compound thin film is deposited on a substrate by sputtering at a deposition rate of 15 to 200 nm/hour using a Group III nitride compound target in a plazma atmosphere of gas comprising 10 mole % or more nitrogen. Then, the poly-crystalline Group III nitride compound semiconductor thin film deposited on the substrate is irradiated with an excimer pulsed laser with an energy density of about 200 mJ/cm2, in an atmosphere of gas with an oxygen content of 2 mole % or less. Thereby, lattice defects such as grain boundaries or dislocations which occur in the thin film are removed.Type: ApplicationFiled: July 31, 2002Publication date: February 27, 2003Inventor: Satoshi Mitamura
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Patent number: 6500314Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: July 3, 1996Date of Patent: December 31, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
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Publication number: 20020134671Abstract: A specialized physical vapor deposition process provides dense amorphous semiconducting material with exceptionally smooth morphology. In particular, the process provides dense, smooth amorphous silicon useful as a hard mask for etching optical and semiconductor devices and as a high refractive index material in optical devices. DC sputtering of a planar target of intrinsic crystalline semiconducting material in the presence of a sputtering gas under a condition of uniform target erosion is used to deposit amorphous semiconducting material on a substrate. DC power that is modulated by AC power is applied to the target. The process provides dense, smooth amorphous silicon at high deposition rates. A method of patterning a material layer including forming a hard mask layer of amorphous silicon on a material layer according to the present DC sputtering process is also provided.Type: ApplicationFiled: January 19, 2001Publication date: September 26, 2002Inventors: Richard E. Demaray, Jesse Shan, Kai-An Wang, Ravi B. Mullapudi
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Patent number: 6451179Abstract: Increased sidewall coverage in a wetting layer for a substrate via or trench is achieved in an inductively coupled plasma chamber by sputtering relatively pure aluminum.Type: GrantFiled: January 30, 1997Date of Patent: September 17, 2002Assignee: Applied Materials, Inc.Inventors: Zheng Xu, Gongda Yao
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Patent number: 6440276Abstract: A process for making a stoichiometric and crystalline thin film CuO catalytic layer atop a gas sensing layer for the detection of dilute sulfur compound gases. The sensing layer is made using dual ion beam sputtering, where an argon ion beam sputters targets comprising Sn or its oxides, and a pure or highly concentrated oxygen ion beam is simultaneously deposited on a substrate. The catalytic layer is made using dual ion beam sputtering, where an argon ion beam sputters targets comprising CU or its oxides, and a pure or highly concentrated oxygen ion beam is simultaneously deposited on a substrate.Type: GrantFiled: January 16, 2001Date of Patent: August 27, 2002Assignee: Tong Yang Moolsan Co., Ltd.Inventors: Yong Sahm Choe, Jae Ho Chung, Dae Seung Kim
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Patent number: 6398925Abstract: Methods are presented for depositing an infrared reflective, e.g., silver, containing multi-layer coating onto a substrate to form a coated article. One or more ceramic cathodes are used to deposit a protective layer over the silver layer. The use of the ceramic cathodes eliminates the need for the metal primer layers common in the prior art. Both the infrared reflective layer and a ceramic layer can be deposited in the same coating zone, this coating zone containing sufficient oxygen to provide a substantially oxidized ceramic coating layer without adversely impacting upon the properties of the infrared reflective layer.Type: GrantFiled: December 18, 1998Date of Patent: June 4, 2002Assignee: PPG Industries Ohio, Inc.Inventors: Mehran Arbab, James J. Finley
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Patent number: 6358378Abstract: An economical method of fabricating a high quality ZnO thin film with only NBE and without any deep-level emission at room temperature in order to replace conventional III-V group compounds such as GaN, and an apparatus therefor. The method comprises the steps of introducing argon (Ar) and oxygen (O2) into a vacuum chamber while maintaining a vacuum level of 1-100 mTorr in the vacuum chamber, preheating a substrate, depositing a ZnO monocrystal thin film on the substrate by RF magnetron sputtering while introducing carbon(C) or nitrogen (N) atoms from an atomic radical source installed over the substrate, and slowly cooling the substrate while maintaining a partial pressure of oxygen in the vacuum chamber at a partial pressure level used while depositing the ZnO thin film.Type: GrantFiled: January 24, 2001Date of Patent: March 19, 2002Assignee: Korea Institute of Science and TechnologyInventors: Won Kook Choi, Hyung Jin Jung, Kyeong Kook Kim, Young Soo Yoon, Jong Han Song
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Publication number: 20020029958Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper.Type: ApplicationFiled: June 20, 2001Publication date: March 14, 2002Applicant: Applied Materials, Inc.Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
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Publication number: 20020029093Abstract: A method of forming a tantalum-containing layer on a substrate is described. The tantalum-containing layer is formed using a physical vapor deposition technique wherein a magnetic field in conjunction with an electric field function to confine material sputtered from a tantalum-containing target within a reaction zone of a deposition chamber. The electric field is generated by applying a power of at least 8 kilowatts to the tantalum-containing target. The magnetic field is generated from a magnetron including a first magnetic pole of a first magnetic polarity surrounded by a second magnetic pole of a second magnetic polarity opposite the first magnetic polarity. The first magnetic pole preferably has a magnetic flux at least about 30% greater than a magnetic flux of the second magnetic pole. The tantalum-containing layer deposition method is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, an interconnect structure is formed.Type: ApplicationFiled: July 26, 2001Publication date: March 7, 2002Applicant: Applied Materials, Inc.Inventors: Michael Andrew Miller, Peijun Ding, Howard Tang, Tony Chiang, Jianming Fu
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Patent number: 6333111Abstract: The present invention provides a method for producing layered aluminum fine particles, and applications to single electron tunneling quantum devices, and the present invention further relates to a method for producing spherical metallic aluminum fine particles (layered aluminum fine particles), characterized in that metallic aluminum is supplied into a mixed gas of helium and 1×10−7 to 3×10−7 torr water vapor by sputtering induced by argon gas discharge to generate aggregates, after which this product is released into a vacuum to generate single crystals in which the surface layer is covered with alumina.Type: GrantFiled: March 13, 2000Date of Patent: December 25, 2001Assignee: Agency of Industrial Science and TechnologyInventors: Junichi Murakami, Yutaka Tai, Kazuki Yoshimura, Kazuo Igarashi, Sakae Tanemura, Masahiro Goto
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Patent number: 6323417Abstract: Provided is a method for making layers of I-III-VI semiconductor materials for use in photovoltaic cells, and particularly for making CIS and variations on CIS, such as CIGS and CIGSS. The method includes formation of a plurality of precursor films of the elemental components and at least one final heat treatment step in which the final semiconductor material is formed, with the precursor film for at least one III component being deposited prior to any precursor film including the I component.Type: GrantFiled: September 28, 1999Date of Patent: November 27, 2001Assignee: Lockheed Martin CorporationInventors: Timothy J. Gillespie, Craig H. Marshall, Bruce R. Lanning
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Publication number: 20010037939Abstract: A sample table for holding a silicon substrate into which an impurity is introduced is provided in the lower portion of a vacuum chamber. A high frequency power source is connected to the sample table through a coupling capacitor. The high frequency power source has a self-bias of 500 V, for example. Gas introducing means for introducing a sputtering gas such as an argon gas is provided on the bottom of the vacuum chamber. A solid target which contains an impurity which should be introduced, for example, boron is provided in the upper portion of the vacuum chamber.Type: ApplicationFiled: August 7, 1996Publication date: November 8, 2001Applicant: Hiroaki NakaokaInventors: HIROAKI NAKAOKA, BUNJI MIZUNO, MICHIHIKO TAKASE, ICHIROU NAKAYAMA
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Patent number: 6309515Abstract: There is provided a method for manufacturing a semiconductor device for forming a silicide layer of metal of high melting point, wherein the metal of high melting point is processed in sputtering under a condition in which no deterioration is produced by the sputtering apparatus. There is also provided a sputtering apparatus for manufacturing semiconductor device. In the method of the present invention, a high melting point metal is accumulated on a silicon substrate formed with a gate electrode of a semiconductor element to form a metallic film of high melting point, thereafter it is heat treated to form a silicide layer of the high melting point metal at an interface layer with the metallic film with high melting point, and in this case, the metallic film of high melting point is accumulated in sputtering by a magnetron sputtering device under a condition in which an electrical load amount Q reaching to the gate electrode is less than 5 C/cm2.Type: GrantFiled: October 29, 1998Date of Patent: October 30, 2001Assignee: NEC CorporationInventors: Ken Inoue, Hitoshi Abiko, Minoru Higuchi
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Patent number: 6306267Abstract: The sputtering method of the present invention comprises the steps of forming a plurality of tunnel-like magnetic fluxes on a target, forming an electric field between the target and a belt-like substrate, and conveying the belt-like substrate while reciprocating the plurality of tunnel-like magnetic fluxes at least in the direction of conveying the belt-like substrate, wherein the speed v of conveying the substrate, the distance L in the direction of conveying the belt-like substrate between two adjacent points where the magnetic field of the plurality of tunnel-like magnetic fluxes and the electric field cross each other at a right angle, and the period T of the reciprocating motion of the plurality of tunnel-like magnetic fluxes are controlled so as to L/v=(n+½)T wherein n is z−{fraction (1/16)}<n<z+{fraction (1/16)} and z is an integer equal to or greater than 0.Type: GrantFiled: June 7, 2000Date of Patent: October 23, 2001Assignee: Canon Kabushiki KaishaInventors: Hideo Tamura, Yasushi Fujioka, Masahiro Kanai, Akira Sakai
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Publication number: 20010017257Abstract: An economical method of fabricating a high quality ZnO thin film with only NBE and without any deep-level emission at room temperature in order to replace conventional III-V group compounds such as GaN, and an apparatus therefor. The method comprises the steps of introducing argon (Ar) and oxygen (O2) into a vacuum chamber while maintaining a vacuum level of 1-100 mTorr in the vacuum chamber, preheating a substrate, depositing a ZnO monocrystal thin film on the substrate by RF magnetron sputtering while introducing carbon(C) or nitrogen (N) atoms from an atomic radical source installed over the substrate, and slowly cooling the substrate while maintaining a partial pressure of oxygen in the vacuum chamber at a partial pressure level used while depositing the ZnO thin film.Type: ApplicationFiled: January 24, 2001Publication date: August 30, 2001Applicant: Korea Institute of Science and TechnologyInventors: Won Kook Choi, Hyung Jin Jung, Kyeong Kook Kim, Young Soo Yoon, Jong Han Song
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Patent number: 6254740Abstract: Disclosed is a method of producing an electroluminescent (EL) device having a CaGa2S4:Ce luminescent layer. The ratio of the X-ray diffraction peak intensity I2 for the (200) reflection of CaS to the X-ray diffraction peak intensity I1 for the (400) reflection of CaGa2S4 as appearing in the X-ray diffraction spectrum for the luminescent layer, I2/I1, is 0.1 or less. The amount of the impurity CaS in the luminescent layer is reduced. The EL device produces blue emission with high purity.Type: GrantFiled: April 13, 1998Date of Patent: July 3, 2001Assignee: Nippondenso Co., Ltd.Inventors: Akira Kato, Masayuki Katayama, Nobuei Ito, Tadashi Hattori
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Patent number: 6238527Abstract: A film forming apparatus for forming a minute thin film at a high depositing rate, which comprises a substrate holding means for holding a substrate, a target holding means for holding a target, a gas supply means for supplying a sputtering gas for sputtering the target into a reaction chamber, and an electric power supply means for supplying an electric power for causing an electric discharge between the target and the substrate, wherein a partition member having a plurality of openings provided between the target and the substrate, and wherein means for supplying a reaction gas and a microwave are provided in a space between the partition member and the substrate.Type: GrantFiled: September 30, 1998Date of Patent: May 29, 2001Assignee: Canon Kabushiki KaishaInventors: Kazuho Sone, Nobumasa Suzuki
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Patent number: 6238808Abstract: Provided are a substrate with a zinc oxide layer, in which at least a zinc oxide layer is provided on a support substrate, wherein the zinc oxide layer comprises a zinc oxide layer having the c axis perpendicular to the support substrate and a zinc oxide layer having the c axis slantindicular to the support substrate in the order from the side of the support substrate; and a photovoltaic device in which a semiconductor layer is formed on the substrate with the zinc oxide layer. Thus provided is the inexpensive photovoltaic device with excellent reflective performance and optical confinement effect and with high photoelectric conversion efficiency.Type: GrantFiled: January 20, 1999Date of Patent: May 29, 2001Assignee: Canon Kabushiki KaishaInventors: Kozo Arao, Hideo Tamura, Noboru Toyama, Yuichi Sonoda, Yusuke Miyamoto
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Patent number: 6228228Abstract: A display as for images and/or information comprises a plurality of light-emitting fibers disposed in side-by-side arrangement to define a viewing surface. Each light-emitting fiber includes a plurality of light-emitting elements disposed along its length, each having two electrodes between which are applied electrical signals to cause the light-emitting element to emit light to display a pixel or sub-pixel of the image and/or information. The light-emitting fiber includes an electrical conductor disposed along its length to serve as a first electrode, a layer of light-emissive material disposed thereon, and a plurality of electrical contacts disposed on the light-emissive material to serve as the second electrodes of the light-emitting elements, and are formed in a continuous process wherein a transparent fiber passes through a plurality of processing chambers for receiving the electrical conductor, the light-emissive layer and the plurality of electrical contacts thereon.Type: GrantFiled: October 15, 1999Date of Patent: May 8, 2001Assignee: Sarnoff CorporationInventors: Bawa Singh, William Ronald Roach, William Chiang
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Patent number: 6176983Abstract: The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural sidewalls joining a bottom surface at respective plural corners; first sputtering a process layer upon at least a portion of the bottom surface using ionized metal plasma physical vapor deposition; and following the sputtering of the process layer, second sputtering at least some of the process layer towards the corners within the via.Type: GrantFiled: September 3, 1997Date of Patent: January 23, 2001Assignee: VLSI Technology, Inc.Inventors: Subhas Bothra, Dipankar Pramanik, Samit Sengupta
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Patent number: 6171453Abstract: A mark shielding ring for use in a physical vapor deposition chamber and a method for using such ring are disclosed. The mark shielding ring may be suitably used for shielding alignment marks or any other marks provided on the top surface of a wafer along a peripheral region. The novel mark shielding ring includes an alignment means for mechanically joining a shielding ring to a wafer pedestal on which the ring is positioned. Any up-and-down motion of the wafer pedestal therefore does not change the alignment between the shielding ring and the pedestal and therefore the function of the shielding ring for protecting an alignment mark can be insured.Type: GrantFiled: December 2, 1998Date of Patent: January 9, 2001Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chen Fang Chung, Shuang Ming Jeng