Specified Deposition Material Or Use Patents (Class 204/192.15)
  • Patent number: 11503886
    Abstract: Provided is a jewelry ring comprising a substrate, a first coating of a metallic nitride or a metallic boride, and an external metallic coating. Also provided is a metallic article comprising a substrate comprising tungsten carbide, cobalt, tungsten, titanium, titanium carbide, zirconium, tantalum or aluminum; a first coating of a metallic nitride or a metallic boride; and an external metallic coating.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 22, 2022
    Assignee: Frederick Goldman, Inc.
    Inventor: Andrew Derrig
  • Patent number: 11499242
    Abstract: A method for producing metal decorations on a curved dial made of insulating material includes forming, by a method of the LIGA-UV type, a mould made of photosensitive resin and of galvanically depositing a layer of at least one metal from the conductive layer in order to form a block substantially reaching the upper surface of the photosensitive resin.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 15, 2022
    Assignee: The Swatch Group Research and Development Ltd
    Inventors: Elias Laforge, Simon Springer
  • Patent number: 11495557
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jhao-Cheng Chen, Huang-Hsien Chang, Wen-Long Lu, Shao Hsuan Chuang, Ching-Ju Chen, Tse-Chuan Chou
  • Patent number: 11490501
    Abstract: In an aspect, a plasma focus apparatus produces pulsed high temperature plasma that emits multi-radiation including ion beams, electron beams, fast plasma streams, x-rays and nuclear fusion neutrons. This plasma focus apparatus includes an electrode assembly including an inner and at least one outer electrode, as well as a plurality of capacitors connected to the electrode assembly in parallel to form the high energy density, high current density plasma, where the arrangement and shape of the capacitors and other elements of the circuitry and electrode assembly provide a system with low stray inductance.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: November 1, 2022
    Inventors: Janak H. Handa, Hossam Gaber
  • Patent number: 11462399
    Abstract: A sputtering target including an oxide that includes an indium element (In), a tin element (Sn), a zinc element (Zn) and an aluminum element (Al), and including a homologous structure compound represented by InAlO3(ZnO)m (m is 0.1 to 10), wherein the atomic ratio of the indium element, the tin element, the zinc element and the aluminum element satisfies specific requirements.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 4, 2022
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuaki Ebata, Mami Nishimura, Nozomi Tajima
  • Patent number: 11393686
    Abstract: A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: July 19, 2022
    Assignee: HEXAGEM AB
    Inventors: Jonas Ohlsson, Lars Samuelson, Kristian Storm, Rafal Ciechonski, Bart Markus
  • Patent number: 11338554
    Abstract: A decorative laminated glass includes a first glass sheet, a second glass sheet, and a colored lamination interlayer between the first glass sheet and the second glass sheet. A coating is positioned between the first glass sheet and the lamination interlayer, and in direct contact with the first glass sheet. The coating is formed by the series of the following layers, starting from the surface of the first glass sheet: optionally, a first stack of dielectric layers; a layer based on titanium oxide having a thickness of from 5 to 70 nm; and optionally, a second stack of dielectric layers.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: May 24, 2022
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventor: Carole Braley
  • Patent number: 11335720
    Abstract: To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 17, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takushi Shigetoshi
  • Patent number: 11313030
    Abstract: A method for forming a low-resistivity tantalum thin film having the following steps: depositing a tantalum layer on a substrate, the tantalum of the layer having a ? phase, treating the deposited tantalum layer by exposure to a radio frequency hydrogen plasma, such that the layer has tantalum in a mixed ?-? phase, at least partially desorbing the hydrogen by carrying out at least one of the following steps: exposure to a radio frequency inert gas plasma, and thermal annealing. The treatment step being configured such that the tantalum layer is subjected to temperatures of less than or equal to 300° C.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 26, 2022
    Assignee: X-FAB FRANCE
    Inventors: Faiz Dahmani, Jean-Pierre Cornier, Philippe Becquet, Yannick Legall, Marc Cotto
  • Patent number: 11280007
    Abstract: The invention relates to a method for mattifying a turbine engine part (10) comprising a metal material, the method comprising a step of immersing said part in a chemical bath (14) for mattifying said metal part (10), the bath (14) comprising at least sodium fluoride (NaF) and hydrofluoric (HF) acid, characterised in that the immersion step lasts between 2 and 15 minutes.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 22, 2022
    Assignee: SAFRAN AIRCRAFT ENGINES
    Inventor: Pierre-Joseph Xavier Hervé Saget
  • Patent number: 11230024
    Abstract: A razor blade including a substrate with a cutting edge portion ending in a sharpened tip. The substrate having a thickness of between 1.55 and 1.97 micrometers measured at a distance of five micrometers from the tip, a thickness of between 4.6 and 6.34 micrometers measured at a distance of twenty micrometers from the tip, and a thickness of between 19.8 and 27.12 micrometers measured at a distance of one hundred micrometers from the tip.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: January 25, 2022
    Assignee: BIC-VIOLEX SA
    Inventors: Ioannis Papatriantafyllou, Taxiarchis Terlilis, Labros Kontokostas
  • Patent number: 11227770
    Abstract: A laser system includes a nonlinear optical (NLO) crystal, wherein the NLO crystal is annealed within a selected temperature range. The NLO crystal is passivated with at least one of hydrogen, deuterium, a hydrogen-containing compound or a deuterium-containing compound to a selected passivation level. The system further includes at least one light source, wherein at least one light source is configured to generate light of a selected wavelength and at least one light source is configured to transmit light through the NLO crystal. The system further includes a crystal housing unit configured to house the NLO crystal.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: January 18, 2022
    Assignee: KLA Corporation
    Inventors: Yung-Ho Alex Chuang, Vladimir Dribinski
  • Patent number: 11222785
    Abstract: A method for depositing a metal layer on a wafer is disclosed. A PVD chamber is provide having therein a wafer chuck for holding a wafer to be processed, a target situated above the wafer chuck, a magnet positioned on a backside of the target, and a DC power supply for supplying a DC voltage to the target. The target is a metal or a metal alloy having ferromagnetism property. A paste process is performed to the PVD chamber. The paste process includes sequential steps of: admitting a working gas into the PVD chamber; and igniting the working gas in cascade stages. The wafer is then loaded into the PVD chamber and positioned onto the wafer chuck. A deposition process is then performed to deposit a metal layer sputtered from the target onto the wafer.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 11, 2022
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Xijun Guo, Jianhua Chen, Haipeng Zhu, Xianlei Zhang, Min-Hsien Chen, Ching-Ning Yang, Wen Yi Tan
  • Patent number: 11195735
    Abstract: A load lock for a substrate container for receiving flat substrates, wherein the load lock has a load chamber for receiving the substrate container that has a bottom, a ceiling, a rear wall, a front wall, a first side wall and a second side wall that connect the rear wall to the front wall, and wherein a carrier unit for receiving the substrate container is arranged in the load chamber. Here, it is provided that the load chamber can be divided into a first part and a second part along a dividing plane to open the load chamber, wherein the dividing plane extends toward the rear wall offset from the front wall through the first side wall, the second side wall, the bottom and the ceiling of the load chamber.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: December 7, 2021
    Inventor: Uwe Beier
  • Patent number: 11152325
    Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 19, 2021
    Assignee: Cree, Inc.
    Inventors: Alexander Komposch, Kevin Schneider, Scott Sheppard
  • Patent number: 11150211
    Abstract: Provided is a fabrication method for a composite planar pH sensor modified by graphene film including: slotting into substrate, setting copper foil on both sides, and setting leads on the copper foil; coating graphene film on the copper foils using micro mechanical stripping method to form the first graphene film and the second graphene film; depositing Sb layer and Sb2O3 layer successively on the first graphene film by magnetron sputtering method, and coating Nafion™ perfluorinated sulfonic acid membrane on the Sb2O3 layer by spin-coating method to fabricate pH working electrode; depositing Ag layer on the second graphene film and dipping in FeCl3 solution to form AgCl layer; coating the third graphene film on the AgCl layer to fabricate reference electrode. The composite planar pH sensor modified by graphene film may be used in pH measurement for solid, semisolid, mash and solution samples.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 19, 2021
    Assignee: Jiangsu University
    Inventors: Xiliang Zhang, Kun Xu, Shoujuan Cui, Miaomiao Geng, Pingping Li, Shiqing Zhang
  • Patent number: 11101116
    Abstract: A target includes a target plate and a stabilizing layer which is joined to the rear side of the target plate. The stabilizing layer was produced by high-kinetic-energy spraying of stabilizing material onto the target plate. A process for producing a target is also provided.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: August 24, 2021
    Assignees: Plansee SE, Plansee Composite Materials GmbH
    Inventors: Rudolf Gradinger, Martin Kathrein, Szilard Kolozsvari, Peter Polcik
  • Patent number: 11078718
    Abstract: A coated article includes a substrate, a first dielectric layer, a first metallic layer, a second dielectric layer, a second metallic layer, a third dielectric layer, a third metallic layer, a fourth dielectric layer, a fourth metallic layer and a fifth dielectric layer. At least one of the metallic layers is a discontinuous metallic layer having discontinuous metallic regions. An optional primer is positioned over any one of the metallic layers. Optionally a protective layer is provided as the outer most layer over the fifth dielectric layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 3, 2021
    Assignee: VITRO FLAT GLASS LLC
    Inventors: Patrick Fisher, Paul A. Medwick, Adam D. Polcyn, Andrew V. Wagner
  • Patent number: 11072853
    Abstract: The disclosure provides a metal protective layer, sequentially comprising an organic powder coating, a high-gloss organic coating, a ductile periodic variable alloy protective film and a transparent powder coating, wherein the base powder layer is an epoxy resin or pure polyester powder coating; the high-gloss organic coating is an epoxy resin powder coating, a polyester powder coating, or a polybutadiene organic coating; the ductile periodic variable alloy protective film is formed by direct current magnetron sputtering with two targets in a high vacuum environment, and the material of the targets is composed of a Ni—Cr alloy layer and pure Cr; and the transparent powder layer is an acrylic powder coating or a polyester transparent powder coating.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 27, 2021
    Assignee: CITIC DICASTAL CO., LTD
    Inventors: Zuo Xu, Guoyuan Xiong, Zaide Wang, Huanming Ma, Shengchao Zhang, Shuai Li, Qingwang Wei, Chuanming Li
  • Patent number: 11066739
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Patent number: 11004665
    Abstract: A plasma processing apparatus includes a vacuum container, a conveyance unit including a rotator and circulating and carrying a workpiece through the conveyance path, a cylindrical member having an opening at one end extended in the direction toward the conveyance path, a window member provided at the cylindrical member, and dividing a gas space from the exterior thereof, a supply unit supplying the process gas in the gas space, and an antenna generating inductive coupling plasma on the workpiece. The supply unit supplies the process gas from plural locations where a passing time at which the surface of the rotator passes through a process region is different, and the plasma processing apparatus further includes an adjusting unit individually adjusting the supply amounts of the process gas from the plural locations of the supply unit per a unit time in accordance with the passing time.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 11, 2021
    Assignee: SHIBAURA MECHATRONICS CORPORATION
    Inventors: Yoshio Kawamata, Daisuke Ono
  • Patent number: 10975465
    Abstract: A method of forming an internal stress control film on one surface of an object to be processed by a sputtering method, includes selecting a pressure of a process gas at the time of forming the internal stress control film from a pressure region higher than a threshold value of 5 (Pa) so that stress of the object to be processed when a bias is applied to the object to be processed becomes larger stress on a tensile side and the internal stress control film has higher density, as compared with stress in a case in which a bias is not applied thereto.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 13, 2021
    Assignee: ULVAC, INC.
    Inventors: Katsuaki Nakano, Daisuke Hiramatsu, Yukinobu Numata
  • Patent number: 10964590
    Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Pei Chou, Ken-Yu Chang, Sheng-Hsuan Lin, Yueh-Ching Pai, Yu-Ting Lin
  • Patent number: 10923690
    Abstract: A refined microcrystalline electrode manufacturing method is provided. The refined microcrystalline electrode manufacturing method includes the following step. First, an active material electrode layer is subjected to a conventional thermal annealing (CTA) process in an oxygen-containing environment at a first temperature interval to form an active material crystallization precursor; the active material crystallization precursor is subjected to a rapid thermal annealing (RTA) process in the oxygen-containing environment at a second temperature interval to form an active material coating layer with uniformly distributed fine microcrystal grains, wherein the temperature range of the second temperature interval is greater than the temperature range of the first temperature interval. In addition, a thin film battery and a thin film battery manufacturing method are also provided.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: February 16, 2021
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C
    Inventors: Tien-Hsiang Hsueh, Yuh-Jenq Yu, Chi-Hung Su, Der-Jun Jan
  • Patent number: 10921392
    Abstract: A stacked structure is positioned on a nonmagnetic metal layer. The stacked structure includes a ferromagnetic layer and an intermediate layer interposed between the nonmagnetic metal layer and the ferromagnetic layer. The intermediate layer includes a NiAlX alloy layer represented by Formula (1): Ni?1Al?2X?3 . . . (1), [X indicates one or more elements selected from the group consisting of Si, Sc, Ti, Cr, Mn, Fe, Co, Cu, Zr, Nb, and Ta, and satisfies an expression of 0<?<0.5 in a case of ?=?3/(?1+?2+?3)].
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 16, 2021
    Assignee: TDK CORPORATION
    Inventors: Kazuumi Inubushi, Katsuyuki Nakada
  • Patent number: 10903086
    Abstract: A titanium silicide region forming method includes: performing a pretreatment to expose a clean surface of a silicon layer of a workpiece; forming a titanium-containing region and a titanium silicide region on the silicon layer after performing the pretreatment; and supplying a fluorine-containing gas to the workpiece including the titanium-containing region and the titanium silicide region so as to selectively etch the titanium-containing region with respect to the titanium silicide region.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: January 26, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hideaki Yamasaki, Kensaku Tanaka, Yuji Kobayashi
  • Patent number: 10870904
    Abstract: BMG parts having an uniform and consistently thick metal oxide layer. The metal oxide layer, also known as an interference layer, exhibits a consistent color and durability over the entire surface of the part. Methods and devices involved in forming the BMG parts with uniformly thick interference layers are also provided.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 22, 2020
    Assignee: Crucible Intellectual Property, LLC
    Inventors: Joseph W. Stevick, Adrian Lopez
  • Patent number: 10861685
    Abstract: The fluoro-based polymer composite target for sputtering according to the present invention is excellent in adhesion with a metal electrode to which a voltage is applied, can prevent bending, and is capable of stably forming plasma by imparting conductivity even with industrially widely used DC and MF power supply systems, thereby allowing a fluorinated polymer to be effectively deposited on an adherend by sputtering.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: December 8, 2020
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Sang Jin Lee, Jae Heung Lee, Woo Jin Choi, Cheol Hwan Kim, Sung Hyun Kim, Seong Geun Cho, Dong Seok Ham, Kwang Je Kim, Dong Soon Park, Jae Seong Park
  • Patent number: 10830933
    Abstract: Certain example embodiments of this invention relate to coated articles having a metamaterial-inclusive layer, coatings having a metamaterial-inclusive layer, and/or methods of making the same. Metamaterial-inclusive coatings may be used, for example, in low-emissivity applications, providing for more true color rendering, low angular color dependence, and/or high light-to-solar gain. The metamaterial material may be a noble metal or other material, and the layer may be made to self-assemble by virtue of surface tensions associated with the noble metal or other material, and the material selected for use as a matrix. An Ag-based metamaterial layer may be provided below a plurality (e.g., 2, 3, or more) continuous and uninterrupted layers comprising Ag in certain example embodiments. In certain example embodiments, barrier layers comprising TiZrOx may be provided between adjacent layers comprising Ag, as a lower-most layer in a low-E coating, and/or as an upper-most layer in a low-E coating.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: November 10, 2020
    Assignee: Guardian Glass, LLC
    Inventors: Brent Boyce, Patricia Tucker, Shashi Shah, Cesar Clavero
  • Patent number: 10816615
    Abstract: To more improve detection accuracy of a magnetic sensor. A magnetic sensor includes a substrate; an element part in which a free layer, a non-magnetic layer, and a pinned layer are stacked on the substrate; and a magnetic flux concentrator, wherein an area of the free layer is larger than an area of the pinned layer in a top view, and the free layer and the magnetic flux concentrator have a first overlap region in which the free layer and the magnetic flux concentrator at least partially overlap in the top view.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 27, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Masanori Masuda
  • Patent number: 10808319
    Abstract: A deposition system includes a system housing having a housing interior, a fixture transfer assembly having a generally sloped fixture transfer rail extending through the housing interior, a plurality of sequentially ordered deposition chambers connected by the fixture transfer rail, a controller interfacing with the processing chambers and at least one fixture carrier assembly carried by the fixture transfer rail and adapted to contain at least one substrate. The fixture carrier assembly travels along the fixture transfer rail under influence of gravity. A substrate fixture contains a substrate. The substrate fixture comprises a fixture frame. The fixture frame is defined by multiple circular members adjacently joined in a circular arrangement. Each circular member has a fixture frame opening sized to receive the substrate. Lens support arms may integrate into the circular members, extending in a curved disposition into the fixture frame opening to retain the substrate. A deposition method is also disclosed.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 20, 2020
    Assignee: Quantum Innovations, Inc.
    Inventors: Norman L. Kester, Cliff J. Leidecker, John B. Glarum, Wade E. Nielson, Briant D. Walton
  • Patent number: 10808325
    Abstract: In one aspect, coated cutting tools are described herein comprising a substrate and a coating comprising a refractory layer deposited by physical vapor deposition adhered to the substrate, the refractory layer comprising M1?xAlxN wherein x?0.68 and M is titanium, chromium or zirconium, the refractory layer including a cubic crystalline phase and having hardness of at least 25 GPa.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 20, 2020
    Assignee: KENNAMETAL INC.
    Inventors: Vineet Kumar, Ronald Penich, Yixiong Liu
  • Patent number: 10797301
    Abstract: In a method of manufacturing an electrochemical cell, a porous or non-porous electrically conductive metal substrate may be provided. A conformal metal chalcogenide layer may be formed on a surface of the metal substrate. The metal substrate with the conformal metal chalcogenide layer may be immersed in a nonaqueous liquid electrolyte solution comprising a lithium salt dissolved in a polar aprotic organic solvent. An electrical potential may be established between the metal substrate and a counter electrode immersed in the nonaqueous liquid electrolyte solution such that lithium ions in the electrolyte solution are reduced to metallic lithium and deposited on the surface of the metal substrate over the metal chalcogenide layer to form a conformal lithium metal layer on the surface of the metal substrate over the metal chalcogenide layer.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 6, 2020
    Assignee: GM Global Technology Operations LLC
    Inventors: Fang Dai, Shuru Chen, Meinan He, Mei Cai
  • Patent number: 10797353
    Abstract: A method of manufacturing an electrochemical cell may comprise exposing a surface of a metal substrate to a chalcogen in gas phase such that a metal chalcogenide layer forms on the surface of the metal substrate. A lithium metal foil may be laminated onto the metal chalcogenide layer on the surface of the metal substrate such that a surface of the lithium metal foil physically and chemically bonds to the metal chalcogenide layer on the surface of the metal substrate.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 6, 2020
    Assignee: GM Global Technology Operations LLC
    Inventors: Keegan Adair, Fang Dai, Mei Cai
  • Patent number: 10782427
    Abstract: A radiation detector has a structure enabling suppression of polarization in a thallium bromide crystalline body and suppression of corrosion of an electrode in the air. The radiation detector comprises a first electrode, a second electrode, and a thallium bromide crystalline body provided between the first and second electrodes. At least one of the first electrode and the second electrode includes an alloy layer. The alloy layer is comprised of an alloy of metallic thallium and another metal different from the metallic thallium.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 22, 2020
    Assignee: HAMAMATSU PHOTONIX K.K.
    Inventors: Masanori Kinpara, Toshiyuki Onodera, Keitaro Hitomi
  • Patent number: 10752998
    Abstract: Disclosed herein is an aging resistance coating film for a hub, sequentially comprising an aluminum alloy matrix, a silane conversion film, a high-gloss organic resin coating, a periodic variable alloy black chromium coating film and a transparent resin coating. In the coating film, the thickness of the black chromium coating film is increased and the blackness thereof is adjusted according to different content of C. The residual stress of the deposited metal layer is reduced, the problem of cracking during heating and rapid cooling of the coating film is solved, and the binding force between the coating film and the underlying high-gloss resin material is improved. Also disclosed herein is a method for forming an aging resistance coating film for a hub, comprising: (1) silane pretreatment, (2) spraying of high-gloss medium powder, (3) PVD coating, and (4) spraying of transparent powder.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 25, 2020
    Assignee: CITIC Dicastal Co., Ltd.
    Inventors: Zaide Wang, Huanming Ma, Junfu Li, Shengchao Zhang, Guangcai Chen, Meng Liu
  • Patent number: 10703673
    Abstract: An architectural transparency includes a substrate; a first dielectric layer over at least a portion of the substrate, a first metallic layer over the first dielectric layer, a first primer layer over the first metallic layer, a second dielectric layer over the first primer layer, a second metallic layer over the second dielectric layer, a second primer layer over the second metallic layer, a third dielectric layer over the second primer layer, a third metallic layer over the third dielectric layer, a third primer layer over the third dielectric layer, and a fourth dielectric layer over the third primer layer. At least one of the metallic layers is a subcritical metallic layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 7, 2020
    Assignee: Vitro Flat Glass LLC
    Inventors: Adam D. Polcyn, Andrew V. Wagner, Harry Buhay, Abhinav Bhandari, James J. Finley, Paul R. Ohodnicki, Jr., Dennis J. O'Shaughnessy, Jeffrey A. Benigni, Paul A. Medwick, James P. Thiel
  • Patent number: 10689748
    Abstract: At least one layer in a coating located on a surface of a substrate is a domain structure layer constituted of two or more domains different in composition. The average value of the size of each of first domains, defined as the diameter of a virtual circumcircle in contact with each first domain, is 1 nm to 10 nm. The average value of the nearest neighbor distance of each first domain, defined as the length of the shortest straight line connecting the center of the circumcircle with the center of another circumcircle adjacent to the circumcircle, is 1 nm to 12 nm. 95% or more of the first domains has a size within ±25% of the average value of the size, and 95% or more of the first domains has a nearest neighbor distance within ±25% of the average value of the nearest neighbor distance.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: June 23, 2020
    Assignees: Sumitomo Electric Industries, Ltd., Mimsi Materials AB
    Inventors: Yoshiharu Utsumi, Paer Christoffer Arumskog, Keiichi Tsuda, Konstantinos Sarakinos, Daniel Gunnar Magnfaelt
  • Patent number: 10669620
    Abstract: A vapor deposition apparatus disclosed by an embodiment comprises: a vacuum chamber (8); a mask holder (15) for holding a deposition mask 1; a substrate holder (29) for holding a substrate for vapor deposition (2); an electromagnet (3) disposed above a surface; a vapor deposition source 5 for vaporizing or sublimating a vapor deposition material; and a heat pipe (7) including at least a heat absorption part (71) and a heat dissipation part (72), the heat absorption part being in contact with the electromagnet (3), and the heat dissipation part being derived to an outside of the vacuum chamber (8). The heat pipe (7) and the electromagnet (3) are in intimate contact with each other at an area of a contact part between the heat pipe (7) and the electromagnet (3), the area being equal to or more than a cross-sectional area within an inner perimeter of a coil (32).
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 2, 2020
    Assignee: Sakai Display Products Corporation
    Inventors: Susumu Sakio, Katsuhiko Kishimoto
  • Patent number: 10665543
    Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 26, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
  • Patent number: 10654747
    Abstract: A coated article includes a substrate, a first dielectric layer, a subcritical metallic layer having discontinuous metallic regions, a primer over the subcritical layer, and a second dielectric layer over the primer layer. The primer can be a nickel-chromium alloy. The primer can be a multilayer primer having a first layer of a nickel-chromium alloy and a second layer of titania.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 19, 2020
    Assignee: Vitro Flat Glass LLC
    Inventors: Adam D. Polcyn, Paul A. Medwick, Andrew V. Wagner, Paul R. Ohodnicki, James P. Thiel, Dennis J. O'Shaughnessy, Benjamin Lucci
  • Patent number: 10643843
    Abstract: The present disclosure provides a film forming method and an aluminum nitride film forming method for a semiconductor device. The film forming method for a semiconductor device includes performing multiple sputtering routes sequentially. Each sputtering routes includes: loading a substrate into a chamber; moving a shielding plate between a target and the substrate; introducing an inert gas into the chamber to perform a surface modification process on the target; performing a pre-sputtering to pre-treat a surface of the target; moving the shielding plate away from the substrate, and performing a main sputtering on the substrate to form a film on the substrate; and moving the substrate out of the chamber.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 5, 2020
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Jun Wang, Boyu Dong, Bingliang Guo, Yujie Geng, Huaichao Ma
  • Patent number: 10636670
    Abstract: A method of planarizing a semiconductor device includes forming a first region and a second region on a semiconductor substrate. The first region has a larger thickness than a thickness of the second region. An interlayer dielectric layer is conformally deposited on the first region and the second region. A photoresist is formed on the second region. A bottom anti-reflective coating layer is formed on the photoresist, first region and second region. A planarization process is performed to the semiconductor substrate. The planarization process to the first region and the second region includes removing portions of the interlayer dielectric layer, the photoresist and the BARC layer.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jen Tsai, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10636635
    Abstract: A device for cooling a target, having a component that includes a cooling duct and having an additional thermally conductive plate that is detachably fastened to the cooling side of the component, the cooling side being the side on which the cooling duct exerts its cooling action, characterized in that between the additional thermally conductive plate and the cooling side of the component, a first self-adhesive carbon film is provided, which is extensively and self-adhesively glued to the one side of the additional thermally conductive plate that faces the cooling side.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 28, 2020
    Assignee: Oerlikon Surface Solutions AG, Pfäffikon
    Inventors: Denis Kurapov, Siegfried Krassnitzer
  • Patent number: 10593931
    Abstract: An electrochemical cell comprising a lithium metal negative electrode layer physically and chemically bonded to a surface of a negative electrode current collector via an intermediate metal chalcogenide layer. The intermediate metal chalcogenide layer may comprise a metal oxide, a metal sulfide, a metal selenide, or a combination thereof. The intermediate metal chalcogenide layer may be formed on the surface of the negative electrode current collector by exposing the surface to a chalcogen in gas phase. Then, the lithium metal negative electrode layer may be formed on the surface of the negative electrode current collector over the intermediate metal chalcogenide layer by contacting at least a portion of the metal chalcogenide layer with a source of lithium such that the lithium actively wets the metal chalcogenide layer and forms a conformal lithium metal layer on the surface of the negative electrode current collector over the metal chalcogenide layer.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 17, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Keegan Adair, Fang Dai, Mei Cai
  • Patent number: 10553780
    Abstract: The invention relates to a method for producing a polycrystalline ceramic film on a surface (12) of a substrate (10), in which a particle stream is directed onto the surface (12) and the ceramic film is formed by deposition of the particles onto the surface (12), wherein the particle stream is directed by means of a diaphragm onto the surface (12) along a preferred direction until a first specified layer thickness is reached, the preferred direction and a surface normal of the surface (12) enclosing a specified angle of incidence. According to the invention, the diaphragm is removed from the particle stream after the specified layer thickness has been reached, and additional particles are directed onto the surface (12) until a specified second layer thickness has been reached.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 4, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventors: Matthias Schreiter, Wolfram Wersing
  • Patent number: 10526695
    Abstract: A sputter unit is introduced comprising a housing, a gas inlet, an interface for removable connecting the sputter unit to a vacuum chamber, a gas outlet arranged for supplying a process gas received via the gas inlet to the vacuum chamber, an interface for removable connecting the sputter unit to a base unit comprising a vacuum pump for generating a vacuum in the vacuum chamber, and a transformer arranged in the housing for increasing a supply voltage into an ionisation voltage for ionising the process gas supplied via the gas outlet to the vacuum chamber.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: January 7, 2020
    Assignee: safematic GmbH
    Inventors: Walter Colleoni, Patrick Capeder, Christof Graf
  • Patent number: 10522695
    Abstract: A multilayer stack is described. The multilayer stack includes: (i) one or more inorganic barrier layers for reducing transport of gas or vapor molecules therethrough; (ii) an inorganic reactive layer disposed adjacent to one or more of the inorganic barrier layers, and the reactive layer capable of reacting with the gas or the vapor molecules; and (iii) wherein, in an operational state of the multilayer stack, the vapor or the gas molecules that diffuse through one or more of the inorganic barrier layers react with the inorganic reactive layer, and thereby allow said multilayer stack to be substantially impervious to the gas or the vapor molecules.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: December 31, 2019
    Assignee: VITRIFLEX, INC.
    Inventors: Ravi Prasad, Dennis R. Hollars
  • Patent number: 10511021
    Abstract: A nonaqueous electrolyte secondary battery has both high capacity and high regeneration. A nonaqueous electrolyte secondary battery includes a positive electrode, a negative electrode, and a nonaqueous electrolyte. The positive electrode contains a Ni-containing lithium transition metal oxide having a layered structure and also contains a tungsten compound and/or a molybdenum compound. The percentage of Ni is greater than 90 mole percent with respect to the molar amount of the lithium transition metal oxide. The amount of the compound is 0.1 mole percent to 1.5 mole percent with respect to the molar amount of the lithium transition metal oxide in terms of tungsten element and/or molybdenum element.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 17, 2019
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Takaaki Oka, Kaoru Nagata, Manabu Takijiri, Takeshi Ogasawara
  • Patent number: 10502878
    Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels. In some embodiments, a partially fabricated panel may be provided that includes a substrate, a reflective layer formed over the substrate, and a barrier layer formed over the reflective layer such that the reflective layer is formed between the substrate and the barrier layer. The barrier layer may include a partially oxidized alloy of three or more metals. A first interface layer may be formed over the barrier layer. A top dielectric layer may be formed over the first interface layer. The top dielectric layer may be formed using reactive sputtering in an oxygen containing environment. The first interface layer may prevent further oxidation of the partially oxidized alloy of the three or more metals when forming the top dielectric layer. A second interface layer may be formed over the top dielectric layer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 10, 2019
    Assignee: GUARDIAN GLASS, LLC
    Inventors: Guowen Ding, Jeremy Cheng, Muhammad Imran, Minh Huu Le, Daniel Schweigert, Yongli Xu, Guizhen Zhang