Predominantly Nonmetal Electrolytic Coating (e.g., Anodic Oxide, Etc.) Patents (Class 205/124)
  • Patent number: 11170190
    Abstract: The disclosure features dendritic tags, and methods and systems for fabricating and using such tags. The methods can include obtaining at least one image of a dendritic tag attached to an article, analyzing the at least one image to identify a set of features associated with the dendritic tag, and comparing the set of features to stored information to identify the article.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: November 9, 2021
    Assignee: ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventor: Michael N. Kozicki
  • Patent number: 11107678
    Abstract: An apparatus is provided. The apparatus has a chuck having a first side configured to retain a superstrate or a template and a second side, an array of image sensors disposed at the second side of the chuck and spaced from the chuck, and an array of light sources disposed between the transparent chuck and the array of image sensors.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 31, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Byung-Jin Choi
  • Patent number: 10811197
    Abstract: Various examples are provided for hydrothermally grown BaTiO3, SrTiO3, and BaxSr1?xTiO3 on TiO2 nanotube layers, which can be used in ultra-high charge density capacitors. In one example, a method includes forming a first anodized titanium oxide (ATO) layer on a layer of titanium by anodization, the first ATO layer having a nanotubular morphology; removing the first ATO layer from the layer of titanium; forming a second ATO layer having a nanotubular morphology on the layer of titanium by anodization; and hydrothermally growing a layer of MTiO3 on a surface of the second ATO layer, where M is Ba, Sr, or BaxSr1?x. In another example, an ultra-high density charge capacitor includes a first electrode layer; an ATO layer disposed on the first electrode layer; a layer of MTiO3 on a surface of the ATO layer; and a second electrode layer disposed on the layer of MTiO3.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 20, 2020
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Kyoung Tae Kim, Yong-Kyu Yoon, Dongsu Kim
  • Patent number: 10644098
    Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Poornika Fernandes, Luigi Colombo, Haowen Bu
  • Patent number: 10085351
    Abstract: A coating composition, a composite prepared by using the coating composition, and a method for preparing the composite are provided. The coating composition includes a solvent, an adhesive, and a catalyst precursor including at least one chosen from SnO2, ZnSnO3 and ZnTiO3.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 25, 2018
    Assignee: BYD COMPANY LIMITED
    Inventors: Qing Gong, Wei Zhou, Xinping Lin, Weifeng Miao, Xiaofang Chen
  • Patent number: 9929044
    Abstract: To provide a semiconductor device with low parasitic capacitance, a semiconductor device with low power consumption, a semiconductor device having favorable frequency characteristics, or a highly integrated semiconductor device. In a method of manufacturing a semiconductor device including a semiconductor, a first conductor, a second conductor, a third conductor, and an insulator, the semiconductor includes a first region in contact with the first conductor, a second region in contact with the second conductor, and a third region in contact with the insulator. The third conductor includes a region in which the third conductor and the semiconductor overlap with each other with the insulator interposed therebetween. The first region, the second region, and the third region do not overlap with each other. The first conductor is selectively grown over the first region, and the second conductor is selectively grown over the second region.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuhiro Tanaka
  • Patent number: 9841676
    Abstract: A method for manufacturing a display device includes forming a plurality of light blocking patterns on a first surface of a transparent substrate, wherein a first light blocking pattern of the plurality of light blocking patterns has a different line width than a second light blocking pattern of the plurality of light blocking patterns. An insulating layer is formed on the first surface of the transparent substrate and the light blocking patterns. A conductive layer is formed on the insulating layer. A photo-resist layer is formed on the conductive layer. The photo-resist layer is exposed with ultraviolet rays through a second surface of the transparent substrate, wherein the first and second surfaces of the transparent substrate are opposite to each other. The photo-resist layer is developed. The conductive layer is etched using the photo-resist layer as a mask. The photo-resist layer is removed.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hoon Kang, Bum Soo Kam, Se Yoon Oh, Chong Sup Chang
  • Patent number: 9741862
    Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 22, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Chih-Lung Lee, Hsin-Hua Lin, Kuo-Lung Fang
  • Patent number: 9583275
    Abstract: There is provided a solid electrolytic capacitor which can increase an electrostatic capacitance and reduce ESR characteristics, and a method of manufacturing the solid electrolytic capacitor. The solid electrolytic capacitor has: a dielectric oxide film formed on a surface of an anode body having fine pores; a cathode body opposing to the anode body; and conductive polymer layers formed inside the fine pores and including amines and water-soluble self-doped conductive polymers having sulfonic acid groups. The self-doped conductive polymers are held in a good state inside fine pores such as etching pits, so that the electrostatic capacitance increases and ESR characteristics are reduced.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: February 28, 2017
    Assignee: NIPPON CHEMI-CON CORPORATION
    Inventor: Shunsuke Endo
  • Patent number: 9470710
    Abstract: A packaged capacitive MEMS sensor device includes at least one capacitive MEMS sensor element with at least one capacitive MEMS sensor cell including a first substrate having a thick and a thin dielectric region. A second substrate with a membrane layer is bonded to the thick dielectric region and over the thin dielectric region to provide a MEMS cavity. The membrane layer provides a fixed electrode and a released MEMS electrode over the MEMS cavity. A first through-substrate via (TSV) extends through a top side of the MEMS electrode and a second TSV through a top side of the fixed electrode. A metal cap is on top of the first TSV and second TSV. A third substrate including an inner cavity and outer protruding portions framing the inner cavity is bonded to the thick dielectric regions. The third substrate together with the first substrate seals the MEMS electrode.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 18, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ira Oaktree Wygant, Peter B. Johnson
  • Patent number: 9023186
    Abstract: A method of manufacturing an electrode includes: providing a metal foil; depositing titanium metal on the metal foil; masking the titanium metal surface to control the density of sites where anodization will occur; and anodizing the Ti/metal foil so as to produce a nano-porous titania dielectric on the surface of the anode. The process may be on only one surface of the metal foil or on both sides simultaneously. The metal foil may be an aluminum foil. The porous titania dielectric may comprise titania nanotubes. An electrode structure may be fabricated using a linear process tool for reel-to-reel processing of a metal foil, the tool may include: a titanium deposition station for depositing a uniform thin film of titanium on the surface of the metal foil; a masking station for modifying the titanium surface to control the density of sites where anodization will occur; and an anodization station for transforming the Ti thin film into a porous titania dielectric film.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Nag B. Patibandla, Lu Yang
  • Patent number: 8939752
    Abstract: A mold comprising alumina having a microscopic pattern, in which distances between adjacent recesses or salients therein are not longer than wavelength of visible light, formed by anodic oxidation on a surface of an aluminum pre-mold without a rolling mark, wherein height or depth difference at a crystal grain boundary is 300 nm or less.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 27, 2015
    Assignees: Mitsubishi Rayon Co., Ltd., Kanagawa Academy of Science and Technology
    Inventors: Yoshihiro Uozu, Eiko Okamoto, Katsuhiro Kojima, Satoshi Sakuma, Hideki Masuda, Takashi Yanagishita
  • Patent number: 8877571
    Abstract: Methods of anodizing aluminum using a hard mask and related embodiments of semiconductor devices are disclosed herein. Other methods and related embodiments are also disclosed herein.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: November 4, 2014
    Assignee: Arizona Board of Regents, a Body Corporate of the State of Arizona Acting for and on Behalf of Arizona State University
    Inventors: Jovan Trujillo, Curtis Moyer
  • Patent number: 8826528
    Abstract: Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: September 9, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Michael A. Haase
  • Patent number: 8828151
    Abstract: Disclosed is an easily handleable composition for metal surface treatment which enables to achieve foundation surface concealment, coating adhesion and corrosion resistance equal to or higher than those obtained by the conventional metal surface treatment compositions. This composition for metal surface treatment places no burden on the environment. Also disclosed are a method for treating the surface of a metal material wherein such a composition for metal surface treatment is used, and a metal material treated by such a metal surface treatment method. Specifically disclosed is a metal surface treatment composition used for a treatment of a metal surface, which composition contains a zirconium compound and/or titanium compound substantially not containing fluorine, and an inorganic acid and/or a salt thereof. This metal surface treatment composition has a pH of not less than 1.5 but not more than 6.5.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: September 9, 2014
    Assignee: Chemetall GmbH
    Inventors: Toshio Inbe, Thomas Kolberg
  • Publication number: 20140209471
    Abstract: A method and apparatus for electrochemically forming an oxide layer on a flat conductive surface which involves positioning a working electrode bearing the flat conductive surface in opposed parallel spaced apart relation to a flat conductive surface of a counter electrode such that the flat conductive surface of the working electrode and the flat conductive surface of the counter electrode are generally opposed, horizontally oriented, and define a space therebetween.
    Type: Application
    Filed: September 8, 2011
    Publication date: July 31, 2014
    Applicant: CLEAR METALS, INC.
    Inventors: Leonid Borisovich Rubin, Alexander Sergeyevich Osipov, Elena Borisovna Neburchilova
  • Publication number: 20130061920
    Abstract: A photovoltaic cell (100) is proposed. The photovoltaic cell includes a substrate (105; 105?) of semiconductor material, and a plurality of contact terminals (Tf,Tb) each one arranged on a corresponding contact area (122) of the substrate for collecting electric charges being generated in the substrate by the light. For at least one of the contact areas, the substrate includes at least one porous semiconductor region (125) extending from the contact area into the substrate for anchoring the whole corresponding contact terminal on the substrate. In the solution according to an embodiment of the invention, each porous semiconductor region has a porosity decreasing moving away from the contact area inwards the substrate. An etching module (400) and an electrolytic module (700;700?;800;800?) for processing photovoltaic cells, a production line (900) for producing photovoltaic cells, and a process for producing photovoltaic cells are also proposed.
    Type: Application
    Filed: March 12, 2011
    Publication date: March 14, 2013
    Applicant: RISE TECHNOLOGY S.R.L.
    Inventor: Marco Balucani
  • Patent number: 8313632
    Abstract: A semiconductor substrate is anodized to be shaped into an optical lens. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired lens profile. Upon completion of the anodization, the semiconductor substrate is shaped into the lens by etching out the porous layer and the anode pattern from the substrate.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: November 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshiaki Honda, Takayuki Nishikawa
  • Patent number: 8262809
    Abstract: An easily handleable composition for metal surface treatment is provided which achieves foundation surface concealment, coating adhesion and corrosion resistance equal to or higher than those obtained by the conventional metal surface treatment compositions. This composition for metal surface treatment places no burden on the environment. A method for treating the surface of a metal material in which such a composition for metal surface treatment is used, and a metal material treated by such a metal surface treatment method, are also provided. Specifically disclosed is a metal surface treatment composition used for a treatment of a metal surface, which composition contains a zirconium compound and/or titanium compound substantially not containing fluorine, and an inorganic acid and/or a salt thereof. This metal surface treatment composition has a pH of not less than 1.5 but not more than 6.5.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: September 11, 2012
    Assignee: Chemetall GmbH
    Inventors: Toshio Inbe, Thomas Kolberg
  • Publication number: 20120097961
    Abstract: Methods of anodizing aluminum using a hard mask and related embodiments of semiconductor devices are disclosed herein. Other methods and related embodiments are also disclosed herein.
    Type: Application
    Filed: December 7, 2011
    Publication date: April 26, 2012
    Applicants: Arizona State University
    Inventors: Jovan Trujillo, Curtis Moyer
  • Publication number: 20110242778
    Abstract: Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier.
    Type: Application
    Filed: December 3, 2009
    Publication date: October 6, 2011
    Inventors: Steven D. Theiss, Michael A. Haase
  • Patent number: 7651736
    Abstract: The present invention provides a method of producing a structure, which is capable of easily obtaining a structure of the nanometer scale by using an anodic oxidation method. A method of producing a structure with a hole includes: forming first projected structures regularly arranged on a substrate; forming a first anodic oxidating layer on the substrate having the first projected structures, thereby forming first recessed structures at center portions of cells formed by the projected structures on the anodic oxidating layer; removing the first projected structures to form holes; and subjecting the first anodic oxidating layer to anodic oxidation to form holes at positions of the first recessed structures.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: January 26, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aya Imada, Toru Den
  • Publication number: 20090258188
    Abstract: Disclosed herein is a composition for forming an inorganic pattern, comprising an inorganic precursor, at least one stabilizer selected from ?-diketone and ?-ketoester, and a solvent. Use of the composition enables efficient and inexpensive formation of an inorganic micropattern.
    Type: Application
    Filed: August 28, 2008
    Publication date: October 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Nam CHA, Dae Joon KANG, Byong Gwon SONG
  • Patent number: 7534337
    Abstract: A substrate before an insulation process, which is provided with a protection film to prevent a part of a surface area, which has electrical conductivity from being insulated, the substrate comprises: a base including the surface area, which has electrical conductivity; a protection film covering over the part of the surface area, which has electrical conductivity, and being formed on the base; the protection film including; a first protection layer having a circumferential partition wall and a second protection layer placed and embedded in an area, which is surrounded by the circumferential partition wall.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: May 19, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Hironori Hasei
  • Publication number: 20090056991
    Abstract: The present invention generally relates to methods of treating a surface of a substrate, and to the use of the method and resulting films, coatings and devices formed therefrom in various applications including but not limited to electronics manufacturing, printed circuit board manufacturing, metal electroplating, the protection of surfaces against chemical attack, the manufacture of localized conductive coatings, the manufacture of chemical sensors, for example in the fields of chemistry and molecular biology, the manufacture of biomedical equipment, and the like. In another aspect, the present invention provides a printed circuit board, a printed circuit board, comprising: at least one metal layer; a layer of organic molecules attached to the at least one metal layer; and an epoxy layer atop said layer of organic molecules.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 5, 2009
    Inventors: Werner G. Kuhr, Steven Z. SHI, Jen-Chieh WEI, Zhiming LIU, Lingyun WEI
  • Patent number: 7422629
    Abstract: Electrolysis using a suitable electrolyte provides a completely nonsludging zinc phosphate conversion coating process that produces a high quality conversion coating in a very short time. The suitable electrolyte contains at least water, dissolved nitric acid, and dissolved zinc cations and optionally also contains m chemically distinct species of cations other than zinc and n chemically distinct species of anions other than anions derivable by ionization of phosphoric and nitric acids, each of m and n independently being zero or a positive integer.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: September 9, 2008
    Assignee: Henkel Kommanditgesellschaft Auf Aktien
    Inventors: Jun Kawaguchi, Kazuhiro Ishikura, Tomoyuki Manmi
  • Patent number: 7282131
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7204014
    Abstract: A method for fabricating a magnetic head wherein a read head portion of the magnetic head includes a second gap insulation layer that includes a first portion that is fabricated upon the electrical leads of the read head and a second portion that is fabricated upon both a sensor portion of the read head and the first portion of the insulation layer. Both the first portion and the second portion of the insulation layer are made up of multi-layered laminations. Each said lamination is fabricated by depositing a thin film of metal, followed by the oxidation of that metallic thin film.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: April 17, 2007
    Assignee: Interntional Business Machines Corporation
    Inventors: Hardayal Singh Gill, Douglas Johnson Werner
  • Patent number: 7014748
    Abstract: This invention is to reduce the influence of a gas generated by an anodizing reaction. A silicon substrate (101) to be processed is horizontally held. A negative electrode (129) is arranged on the upper side of the silicon substrate (101), and a positive electrode (114) is brought into contact with the lower surface of the silicon substrate (101). The space between the negative electrode (129) and the silicon substrate (101) is filled with an HF solution (132). The negative electrode (129) has a number of degassing holes (130) to prevent a gas generated by the anodizing reaction from staying on the lower side of the negative electrode (129).
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: March 21, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Matsumura, Kenji Yamagata
  • Patent number: 6823693
    Abstract: A controller is used with an anodic bonding system that has a charge flowpath for supplying charge to bond materials together. The controller includes a switch and a circuit. The switch is configured to control a flow of the charge through the charge flowpath. The circuit is configured to monitor a rate of the flow, use the rate to determine an amount of the charge supplied for bonding, and based on the amount or rate, operate the switch to control the flow.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: November 30, 2004
    Assignee: Micron Technology, Inc.
    Inventors: James J. Hofmann, Glenn W. Piper
  • Patent number: 6814849
    Abstract: A porous silicon structure is stabilized by anodically oxidizing the structure and then subjecting it to chemical functionalization to protect non-oxidized surface regions, preferably in the presence of 1-decene under thermal conditions. This process creates a protective organic monolayer on the surface of the structure, rendering it highly stable.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: November 9, 2004
    Assignee: National Research Council
    Inventors: David John Lockwood, Rabah Boukherroub, Danial D. M. Wayner, Nobuyoshi Koshida
  • Publication number: 20040124088
    Abstract: Openings are formed at the bottom of an anodizing container. A shower-type current path forming mechanism is arranged at the lower portion of the anodizing container. The mechanism has a pressure vessel. A shower head is arranged at the upper portion of the pressure vessel. A conductive solution in a shower form is injected or discharged from the shower head to form a liquid electrode under the lower surface of a substrate. Accordingly, a current flows between a cathode and an anode to anodize the substrate. The apparatus also has a mechanism which makes a chemical solution overflow from a chemical solution container to form a flow of the chemical solution near the lower surface of the substrate.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 1, 2004
    Applicant: Canon Kabushiki Kaisha
    Inventors: Takashi Tsuboi, Kenji Yamagata, Kiyofumi Sakaguchi, Kazutaka Yanagita, Takashi Sugai, Kazuhito Takanashi
  • Patent number: 6736952
    Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: May 18, 2004
    Assignee: SpeedFam-IPEC Corporation
    Inventors: Ismail Emesh, Saket Chadda, Nikolay N. Korovin, Brian L. Mueller
  • Publication number: 20040086697
    Abstract: The present invention provides inter alia electroplating compositions, methods for use of the compositions and products formed by the compositions. Electroplating compositions of the invention are characterized in significant part by a grain refiner/stabilizer additive comprising one or more non-aromatic compounds having &pgr; electrons that can be delocalized, e.g., an &agr;, &pgr; unsaturated system or other conjugated system that contains a proximate electron-withdrawing group. Compositions of the invention provide enhanced grain refinement and increased stability in metal plating solutions, particularly in tin and tin alloy plating formulations.
    Type: Application
    Filed: July 16, 2003
    Publication date: May 6, 2004
    Applicant: Shipley Company, L.L.C.
    Inventors: Andre Egli, Anja Vinckier, Jochen Heber, Wan Zhang
  • Patent number: 6663760
    Abstract: A non-aqueous electrolyte comprises an organic solvent and a solute, and also has an electrolytic conductivity that is greater than or equal to 1 mS/cm but less than or equal to 100 mS/cm. This solute preferably includes at least one of a carboxylate and a salt of inorganic oxoacid. In addition, the non-aqueous electrolyte preferably comprises water in a proportion of 1 to 10 wt %. In an MIM nonlinear element (20), an insulated film (24) is formed by anodic oxidation using the above non-aqueous electrolyte. In addition, the insulated film comprises at least one of carbon atoms and atoms of families 3 to 7 that were originally the central atoms of the salt of inorganic oxoacid, and has a relative permittivity of 10 to 25. With this MIM nonlinear element, the capacitance is sufficiently small, the steepness of the voltage-current characteristic is sufficiently large, and also the resistance is sufficiently uniform over a wide area.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: December 16, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Inoue, Takeyoshi Ushiki, Takumi Seki, Makoto Ue, Fumikazu Mizutani, Sachie Takeuchi
  • Patent number: 6576112
    Abstract: The present invention provides a method of forming a zinc oxide film on a conductive substrate, which comprises dipping the conductive substrate and a counter electrode in an aqueous solution containing at least nitric acid ion and zinc ion and supplying a current between these electrodes to form a zinc oxide film, wherein the aqueous solution further contains polycarboxylic acid in which a carboxyl radical is bonded to each of carbon having sp2 hybrid orbital, or its ester with a concentration of 0.5 &mgr;mol/L to 500 &mgr;mol/L. Thereby, it is possible to form in a short time a thin film having texture structure exhibiting an optical confinement effect, to prevent abnormal growth of a deposited film, and to obtain a zinc oxide thin film having excellent uniformity and adhesion on a surface thereof where the film is formed. Also, by applying the photovoltaic device to a stacked structure, it is possible to enhance the photoelectric characteristics and mass producibility.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: June 10, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuichi Sonoda, Noboru Toyama, Yusuke Miyamoto, Hidetoshi Tsuzuki
  • Patent number: 6464853
    Abstract: A method of producing a structure having narrow pores includes a first step of bringing pore-guiding members into contact with upper and lower surfaces of a member comprising aluminum as a principal ingredient and a second step of anodizing the member comprising aluminum as the principal ingredient to form narrow pores. The pore-guiding members contain the same material as a principal ingredient. The second step includes preferably a step of transforming the member comprising aluminum as the principal ingredient into a porous body comprising alumina having narrow pores oriented substantially parallel to the interfaces between the pore-guiding members and the member comprising aluminum as the principal ingredient.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: October 15, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Tohru Den
  • Patent number: 6436591
    Abstract: Disclosed is a method for manufacturing conductive color filters having a fine, complicated pixel pattern, a high resolution, high surface smoothness, and a high, uniform conductivity. The method comprises the selective formation of a black matrix on a light-transmitted photoconductive thin film of a light-transmitting substrate, which comprises the light-transmitting conductive film stacked upon a photoconductive thin film and allowing at least the photoconductive thin film of the substrate to be in contact with an electrolyte containing a conductive electrodeposition material containing a coloring material. The photoconductive thin film is then irradiated with light, and the electrodeposition material is then selectively deposited in a light-irradiated area of the photoconductive thin film, thereby forming a conductive colored electrodeposition film.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: August 20, 2002
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigemi Ohtsu, Keishi Shimizu, Takao Tomono, Eiichi Akutsu
  • Publication number: 20020108861
    Abstract: An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a polishing pad and a platen. The platen is formed of conductive material, is disposed proximate to the polishing pad and is configured to have a negative charge during at least a portion of a planarization process. At least one electrical conductor is positioned within the platen. The electrical conductor has a first end connected to a power source. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing pad. The power source applies a positive charge to the workpiece via the electrical conductor so that an electric potential difference between the metallized surface of the workpiece and the platen is created to remove at least a portion of the metallized surface from the workpiece.
    Type: Application
    Filed: February 12, 2001
    Publication date: August 15, 2002
    Inventors: Ismail Emesh, Saket Chadda, Nikolay Korovin, Brian L. Mueller
  • Patent number: 6387771
    Abstract: A method for forming a valve metal oxide for semiconductor fabrication in accordance with the present invention is disclosed and claimed. The method includes the steps of providing a semiconductor wafer, depositing a valve metal on the wafer, placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the valve metal to form a metal oxide when a potential difference is provided between the valve metal and the solution and processing the wafer using the metal oxide layer.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: May 14, 2002
    Assignee: Infineon Technologies AG
    Inventors: Oliver Genz, Alexander Michaelis
  • Patent number: 6340544
    Abstract: To provide a process for recording an image using a photoelectrodeposition method having high general-purpose properties that require no restriction on the selection of a material used as a substrate, a process for recording an image having (A) arranging a substrate 10 comprising a support 11, a conductive film 12 and a photosemiconductor thin film 13 laminated in this order, in such a manner that at least the photosemiconductor thin film 13 comes in contact with an electrodeposition solution 20; (B) applying an electric current or a voltage to the conductive film 12, and simultaneously irradiating the substrate 10 with light from the side of the photosemiconductor thin film 13 through the electrodeposition solution 20, and (C) generating a photoelectromotive force on a light irradiated part, so as to form an electrodeposition film 21 on the light irradiated part.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: January 22, 2002
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Eiichi Akutsu, Shigemi Ohtsu, Lyong Sun Pu
  • Patent number: 6312581
    Abstract: A process for fabricating a silica-based optical device on a silicon substrate is disclosed. The device has a cladding formed in a silicon substrate. The device also has an active region, and that active region is formed on the cladding. The cladding is fabricated by forming a region of porous silicon in the silicon substrate. The porous silicon is then oxidized and densified. After densification, the active region of the device is formed on the cladding.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: November 6, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Allan James Bruce, Alexei Glebov, Joseph Shmulovich, Ya-Hong Xie
  • Patent number: 6309782
    Abstract: A method for manufacturing a color filter having a high resolution and excellent controllability, in few steps without using a photolithographic process is disclosed.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: October 30, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigemi Ohtsu, Eiichi Akutsu, Lyong Sun Pu, Motohiko Tsuchiya
  • Publication number: 20010011637
    Abstract: A compliant wafer chuck for supporting a substrate in which an upper body of the chuck is allowed to tilt relative to the base.
    Type: Application
    Filed: April 4, 2001
    Publication date: August 9, 2001
    Inventor: Joseph Wytman
  • Patent number: 6258240
    Abstract: It is an object of the present invention to provide an anodizing apparatus capable of efficiently performing anodizing. In order to achieve this object, an anodizing apparatus for anodizing a substrate to be processed in an electrolytic solution includes a process tank for storing the electrolytic solution, the process tank having an opening in a wall, a negative electrode arranged in the process tank to oppose the opening, and a positive electrode contacting a surface of the substrate to be processed which is arranged to close the opening from an inside of the process tank, the surface being open outside the process tank through the opening.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: July 10, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Matsumura, Kenji Yamagata
  • Patent number: 6197654
    Abstract: A method of anodizing a lightly doped wafer wherein there is provided a lightly p-typed doped silicon wafer having a frontside and a backside. A p-type region is formed on the backside doped sufficiently to avoid inversion to n-type when a later applied current density of predetermined maximum value is applied to the backside. The wafer is placed in the electrolyte of a chamber having an electrolyte and having a pair of electrodes, preferably platinum, on opposite sides of the wafer and in the electrolyte. The current of predetermined value is passed between the electrodes and through the wafer, the current being sufficient to cause pores to form on the frontside of the wafer. The chamber preferably has first and second regions, one of the electrodes being disposed in one of the regions and the other electrode being disposed in the other regions with the wafer hermetically sealing the first region from the second region.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: March 6, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Leland S. Swanson
  • Patent number: 6187165
    Abstract: Novel arrays of nanowires made of semi-metallic Bismuth (Bi) is disclosed made by unique electrodeposition techniques. Because of the unusual electronic properties of the semi-metallic Bi and the nanowire geometry, strong finite size effects in transport properties are achieved. In addition, very large positive magnetoresistance, 300% at low temperatures and 70% at room temperature, with quasilinear field dependence have been attained.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: February 13, 2001
    Assignee: The John Hopkins University
    Inventors: Chia-Ling Chien, Peter C. Searson, Kai Liu
  • Patent number: 6149792
    Abstract: A structure and method for forming an anodized row electrode for a field emission display device. In one embodiment, the present invention comprises depositing a resistor layer over portions of a row electrode. Next, an inter-metal dielectric layer is deposited over the row electrode. In the present embodiment, the inter-metal dielectric layer deposited over portions of the resistor layer and over pad areas of the row electrode. After the deposition of the inter-metal dielectric layer, the row electrode is subjected to an anodization process such that exposed regions of the row electrode are anodized. In so doing, the present invention provides a row electrode structure which is resistant to row to column electrode shorts and which is protected from subsequent processing steps.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: November 21, 2000
    Assignee: Candescent Technologies Corporation
    Inventor: Kishore K. Chakravorty
  • Patent number: 6132585
    Abstract: The present invention aims to provide a highly reliable semiconductor element with high performance, and a fabrication method for such highly reliable semiconductor with excellent mass producibility. The photovoltaic elements comprise an electric conductor, semiconductor regions and a transparent conductor layer, which are sequentially formed on a substrate. The shunt resistance in the semiconductor element is rendered in the range from 1.times.10.sup.3 .OMEGA.cm.sup.2 to 1.times.10.sup.6 .OMEGA.cm.sup.2 by performing a forming treatment and a short circuit passivation treatment after forming the transparent conductor layer, and then selectively covering with insulation the defective portions with a cationic or anionic electrodeposited resin, or performing a forming treatment, after forming the semiconductor layers, then selectively covering with insulation the defective portions with a cationic or anionic electrodeposited resin, and then forming the transparent conductor layer.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: October 17, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takafumi Midorikawa, Tsutomu Murakami, Takahiro Mori, Hirofumi Ichinose
  • Patent number: 6123824
    Abstract: A photo-electricity generating device is produced through the steps of: immersing an electrode and an electroconductive substrate in an aqueous solution comprising nitrate ions and zinc ions, supplying a current passing through a gap between the electrode and the electroconductive substrate to form a first zinc oxide layer on the electroconductive substrate, etching the first zinc oxide layer, and forming a semiconductor layer on the zinc oxide layer. The zinc oxide layer may preferably be formed in two zinc oxide layers under different electrudeposition conditions. In this case, the etching step may preferably be performed between steps for forming these zinc oxide layers. The zinc oxide layer is provided with an unevenness at its surface suitable for constituting a light-confining layer of a resultant photo-electricity generating device.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: September 26, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masafumi Sano, Toshimitsu Kariya