Product Is Semiconductor Or Includes Semiconductor Patents (Class 205/123)
  • Patent number: 10672656
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
  • Patent number: 10605771
    Abstract: An electroplating solution analyzer includes an analysis container for housing an electroplating solution containing additives including an accelerator and a suppressor, a working electrode that is immersed in the electroplating solution housed in the analysis container to exchange electrons therewith, a reference electrode immersed in the electroplating solution and serves as a reference for determining a potential of the working electrode, a counter electrode immersed in the electroplating solution, a rotation drive unit for rotating the working electrode at a constant speed, a current-generating unit for supplying a current with a constant current density between the working electrode and the counter electrode, a potential measuring unit for measuring a potential between the working electrode and the reference electrode, and an analyzing unit for determining a condition of the electroplating solution in one or more measurement sections at an elapsed time after the current starts to be supplied.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 31, 2020
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Masahiro Kosugi, Toshikazu Okubo
  • Patent number: 10592796
    Abstract: A chip card manufacturing method. A module includes a substrate supporting contacts on one surface and conductive paths and a chip on another; and an antenna on a holder, the antenna including a contact pad for respectively connecting to each of the ends thereof. A solder drop is placed on each of the contact pads of the antenna. The holder of the antenna is inserted between plastic layers. A cavity is provided, in which the module can be accommodated and the solder drops remain accessible. The height of the solder drops before heating is suitable for projecting into the cavity. A module is placed in each cavity. The areas of the module that are located on the solder drops are heated to melt the solder and to solder the contact pads of the antenna to conductive paths of the module.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: March 17, 2020
    Assignee: Linxens Holding
    Inventors: Eric Eymard, Cyril Proye, Nicolas Guerineau, Christophe Paul
  • Patent number: 10522505
    Abstract: A surface mount structure includes a substrate, a sensor, an electrical contact and a package body. The substrate has a first surface and a second surface opposite to the first surface. The sensor is disposed adjacent to the second surface of the substrate. The electrical contact is disposed on the first surface of the substrate. The package body covers the first surface and the second surface of the substrate, a portion of the sensor and a first portion of the electrical contact.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 31, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Ming Hung, Meng-Jen Wang, Tsung-Yueh Tsai, Jen-Kai Ou
  • Patent number: 10515932
    Abstract: This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: December 24, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Daisuke Tsuji
  • Patent number: 10407791
    Abstract: A method provides a structure that includes a substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer. The method further includes immersing the structure in a plating bath contained in an electroplating cell, the plating bath containing a selected solder material; applying a voltage potential to the structure, where the structure functions as a working electrode in combination with a reference electrode and a counter electrode that are also immersed in the plating bath; and maintaining the voltage potential at a predetermined value to deposit the selected solder material selectively only on the metal feature and not on the metal layer. An apparatus configured to practice the method is also disclosed.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qianwen Chen, Bing Dang, Yu Luo, Joana Sofia Branquinho Teresa Maria
  • Patent number: 10403589
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 3, 2019
    Assignee: ATI Technologies ULC
    Inventor: Roden R. Topacio
  • Patent number: 10276436
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
  • Patent number: 10214826
    Abstract: Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: February 26, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Jian Zhou, Jon Reid
  • Patent number: 10217806
    Abstract: A display apparatus includes a display panel including a display substrate on which a plurality of pad terminals is disposed, and a driving unit including a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoungyong Kim, Seunghwa Ha, Seungsoo Ryu, Sanghyeon Song, Jeongdo Yang, Jungyun Jo, Jeongho Hwang
  • Patent number: 10211115
    Abstract: A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: February 19, 2019
    Assignee: MATERION CORPORATION
    Inventor: Ramesh Kothandapani
  • Patent number: 10128348
    Abstract: A metal bump structure for use in a driver IC includes a metal bump disposed on a matrix, an optional capping layer disposed on the metal bump to completely cover the metal bump and a protective layer disposed on the metal bump to completely cover and protect the metal bump or the optional capping layer and so that the metal bump is not exposed to an ambient atmosphere. The protective layer or the optional capping layer may have a fringe disposed on the matrix.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: November 13, 2018
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Chiu-Shun Lin
  • Patent number: 10111336
    Abstract: A flexible printed circuit board with reduced ion migration from signal-carrying elements which are coated against corrosion includes an insulating layer, a wiring area, a copper electroplating layer, a nickel electroplating layer, a cover film, and a gold chemical-plating layer. The wiring area is formed on the insulating layer. The copper electroplating layer formed on the wiring area has a first portion and a second portion. The nickel electroplating layer is formed on at least the first portion and exposes sidewalls of the first portion. The cover film is formed on the second portion and fills in gaps of the copper electroplating layer. The gold chemical-plating layer is formed on top surface of the nickel electroplating layer and the sidewalls of the first portion.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 23, 2018
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co
    Inventors: Lei Zhou, Rui-Wu Liu, Qiong Zhou
  • Patent number: 10084060
    Abstract: The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Kuo Hui Chang, Che-Cheng Chang, Mu-Tsang Lin
  • Patent number: 10000860
    Abstract: A method of electroplating on a workpiece having at least one sub-30 nm feature includes applying a first electrolyte chemistry to the workpiece, the chemistry including a metal cation solute species having a concentration in the range of about 50 mM to about 250 mM and a suppressor resulting in polarization greater than 0.75 V and reaching 0.75 V of polarization at a rate greater than 0.25 V/s, and applying an electric waveform, wherein the electric waveform includes a period of ramping up of current followed by a period of partial ramping down of current.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: APPLIED Materials, Inc.
    Inventors: Serdar Aksu, Jung Gu Lee, Bart Sakry, Roey Shaviv
  • Patent number: 9931813
    Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 3, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Kuan-Neng Chen, Wei-Chung Lo, Cheng-Ta Ko
  • Patent number: 9893262
    Abstract: In some aspects, a quantum information processing circuit includes a lumped-element device on the surface of a dielectric substrate. The lumped-element device can include a capacitor pad and an inductive transmission line. The capacitor pad can be capacitively coupled to another capacitor pad. The inductive transmission line can reside in an interior clearance area defined by an inner boundary of the capacitor pad. The lumped-element device can be, for example, a resonator device or a filter device. The inductive transmission line can be, for example, a meander inductor.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: February 13, 2018
    Assignee: Rigetti & Co., Inc.
    Inventors: Dane Christoffer Thompson, Chad Tyler Rigetti
  • Patent number: 9844794
    Abstract: A substrate plating apparatus is disclosed. The apparatus includes a substrate holder; a plating bath configured to plate a surface of the substrate in a plating solution; a cleaning bath configured to clean the substrate holder and the substrate with a cleaning liquid; an inner shell disposed in the cleaning bath and configured to house the substrate holder holding the substrate therein; and a cleaning liquid supply conduit configured to supply a cleaning liquid into the inner shell to clean the substrate, together with the substrate holder, with the cleaning liquid. The inner shell has an inner surface having an uneven configuration that follows an uneven exterior configuration of the substrate holder holding the substrate.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: December 19, 2017
    Assignee: EBARA CORPORATION
    Inventors: Yoshio Minami, Masaaki Kimura
  • Patent number: 9842909
    Abstract: A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Shigenobu Maeda, Tsukasa Matsuda, Hidenobu Fukutome
  • Patent number: 9758893
    Abstract: A non-uniform initial metal film is non-uniformly deplated to provide a more uniform metal film on a substrate. Electrochemical deplating may be performed by placing the substrate in a deplating bath formulated specifically for deplating, rather than for plating. The deplating bath may have a throwing power of 0.3 or less; or a bath conductivity of 1 mS/cm to 250 mS/cm. Reverse electrical current conducted through the deplating bath non-uniformly. electro-etches or deplates the metal film.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: September 12, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Sam K. Lee, Charles Sharbono
  • Patent number: 9728518
    Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 8, 2017
    Assignee: ATI Technologies ULC
    Inventor: Roden R. Topacio
  • Patent number: 9512538
    Abstract: Disclosed herein are cups for engaging wafers during electroplating in clamshell assemblies and supplying electrical current to the wafers during electroplating. The cup can comprise an elastomeric seal disposed on the cup and configured to engage the wafer during electroplating, where upon engagement the elastomeric seal substantially excludes plating solution from a peripheral region of the wafer, and where the elastomeric seal and the cup are annular in shape, and comprise one or more contact elements for supplying electrical current to the wafer during electroplating, the one or more contact elements attached to and extending inwardly towards a center of the cup from a metal strip disposed over the elastomeric seal. A notch area of the cup can have a protrusion or an insulated portion on a portion of a bottom surface of the cup where the notch area is aligned with a notch in the wafer.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 6, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Zhian He, Jingbin Feng, Shantinath Ghongadi, Frederick D. Wilmot
  • Patent number: 9496326
    Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, John E. Sheets, II
  • Patent number: 9475144
    Abstract: A machine for the electrochemical marking treatment of metallic surfaces, includes an electrode placed in sliding movement on the metallic surface to be treated, a buffer impregnated with etching solution for the specific metal in treatment, and an electric current circuit, suitable for electro-marking treatment of said metal, with a conductor connected to the electrode and the other conductor connected to the metallic surface in treatment; and presents to treat large metallic surfaces on plates, metal canvas or on metallic sheet in coil.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 25, 2016
    Assignee: METALY S.R.L.
    Inventors: Michele Lapelosa, Stefano Muratori
  • Patent number: 9476135
    Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yi Chang, Liang-Yueh Ou Yang, Chen-Yuan Kao, Hung-Wen Su
  • Patent number: 9379198
    Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chih-Chao Yang, David V. Horak, Charles W. Koburger, Shom Ponoth
  • Patent number: 9215810
    Abstract: In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventor: Ken Hasegawa
  • Patent number: 9153555
    Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
    Type: Grant
    Filed: February 25, 2007
    Date of Patent: October 6, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jin-Yuan Lee, Ying-Chih Chen, Mou-Shiung Lin
  • Patent number: 9120846
    Abstract: A process for separating organic compounds from a mixture by reverse-phase displacement chromatography, including providing a hydrophobic stationary phase; applying to the hydrophobic stationary phase a mixture comprising organic compounds to be separated; displacing the organic compounds from the hydrophobic stationary phase by applying thereto an aqueous composition comprising a non-surface active hydrophobic neutral zwitterionic displacer molecule and optionally an organic solvent; and collecting a plurality of fractions eluted from the hydrophobic stationary phase containing the separated organic compounds; in which the non-surface active hydrophobic neutral zwitterionic displacer molecule comprises a hydrophobic zwitterion having the general formula, as defined in the disclosure: [CM-R*—CM?].
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: September 1, 2015
    Assignee: Sachem, Inc.
    Inventor: Barry L. Haymore
  • Patent number: 9040407
    Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Publication number: 20150140814
    Abstract: Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (TSVs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a pH of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as NiB and NiP. The pre-wetting liquid is preferably degassed prior to contact with the wafer substrate. The pretreatment is preferably performed under subatmospheric pressure to prevent bubble formation within the recessed features. After the wafer is pretreated, a metal, such as copper, is electrodeposited from an acidic electroplating solution to fill the recessed features on the wafer. The described pretreatment minimizes corrosion of seed layer during electroplating and reduces plating defects.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: Lam Research Corporation
    Inventor: Matthew Thorum
  • Publication number: 20150137356
    Abstract: The present invention provides a non-cyanogen type electrolytic gold plating solution, which can form a plating film capable of maintaining a high hardness even when the plating film is subjected to a heat treatment. A non-cyanogen type electrolytic gold plating solution of the present invention includes: a gold source including an alkaline salt of gold sulfite or ammonium of gold sulfite; and a conductive salt including sulfite and sulfate. The non-cyanogen type electrolytic gold plating solution includes a salt of at least one of iridium, ruthenium, and rhodium in a metal concentration of 1 to 3000 mg/L. Further, the non-cyanogen type electrolytic gold plating solution preferably includes a crystal adjuster. The crystal adjuster is particularly preferably thallium.
    Type: Application
    Filed: September 19, 2013
    Publication date: May 21, 2015
    Applicant: ELECTROPLATING ENGINEERS OF JAPAN LIMITED
    Inventors: Junko Tsuyuki, Masahiro Ito
  • Publication number: 20150132473
    Abstract: Solid state thermoelectric energy conversion devices can provide electrical energy from heat flow, creating energy, or inversely, provide cooling through applying energy. Thick film methods are applied to fabricate thermoelectric device structures using microstructures formed through deposition and subsequent thermal processing conditions. An advantageous coincidence of material properties makes possible a wide variety of unique microstructures that are easily applied for the fabrication of device structures in general. As an example, a direct bond process is applied to fabricate thermoelectric semiconductor thick films on substrates by printing and subsequent thermal processing to form unique microstructures which can be densified. Bismuth and antimony telluride are directly bonded to flexible nickel substrates.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 14, 2015
    Inventor: Ronald R. Petkie
  • Patent number: 9017539
    Abstract: A method for fabricating a heat sink may include: providing a carbon fiber fabric having carbon fibers and openings, the openings leading from a first side to a second side of the fabric; and electroplating the fabric with metal, wherein metal is deposited with a higher rate at the first side than at the second side of the fabric. Another method for fabricating a heat sink may include: providing a carbon metal composite having metal-coated carbon fibers and openings, the openings leading from a first side to a second side of the carbon metal composite; disposing the composite over a semiconductor element such that the first side of the composite faces the semiconductor element; and bonding the composite to the semiconductor element by means of an electroplating process, wherein metal electrolyte is supplied to an interface between the carbon metal composite and the semiconductor element via the openings.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventor: Friedrich Kroener
  • Publication number: 20150096790
    Abstract: A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: INVENSAS CORPORATION
    Inventors: Cyprian Emeka Uzoh, Sitaram Arkalgud
  • Patent number: 8962085
    Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: February 24, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Mark J. Willey
  • Publication number: 20140318975
    Abstract: The invention relates to a machine (1) adapted to metallise a cavity of a semi-conductive or conductive substrate such as a structure of the through silicon via type, according to a metallisation process comprising the steps consisting of: a) depositing an insulating dielectric layer in the cavity, b) depositing a barrier layer to diffusion of the filling metal, c) filling the cavity by electrodeposition of metal, preferably copper, and d) carrying out annealing of the substrate, characterised in that it comprises a series of wet-processing modules (10-60) configured to conduct steps a), b) and c) by wet-processing in a chemical bath (B) and at least one additional module (70) adapted to conduct annealing step d) of the substrate (S) such that the machine (1) is capable of executing the entire metallisation process of the cavity.
    Type: Application
    Filed: November 19, 2012
    Publication date: October 30, 2014
    Applicant: ALCHIMER
    Inventor: Frederic Raynal
  • Patent number: 8871076
    Abstract: Solar cells are produced using a method for producing solar cells, wherein silicon containing vitreous substrates is provided, wherein each substrate is provided with an electrically conductive material on at least one side thereof. In the method, at least a portion of each substrate is successively transported through an electrolytic solution that is present in an electrolytic bath, and the electrically conductive material as the cathode is connected during the transport of the substrates through the electrolytic bath for the purpose of electrodepositing material from the electrolytic solution onto the electrically conductive material during said transport, wherein the substrates are suspended from a conveyor element during transport and extend in the transport direction.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: October 28, 2014
    Assignee: Meco Equipment Engineers B.V.
    Inventors: Ronald Langereis, Gregorius Johannes Bertens
  • Publication number: 20140312003
    Abstract: A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base.
    Type: Application
    Filed: August 20, 2013
    Publication date: October 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Hongbo Peng, Stephen M. Rossnagel, Ajay K. Royyuru, Gustavo A. Stolovitzky, Deqiang Wang
  • Publication number: 20140305802
    Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.
    Type: Application
    Filed: March 11, 2014
    Publication date: October 16, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Peijun DING, Rong TAO, Zheng XU, Daniel C. LUBBEN, Suraj RENGARAJAN, Michael A. MILLER, Arvind SUNDARRAJAN, Xianmin TANG, John C. FORSTER, Jianming FU, Roderick C. MOSELY, Fusen CHEN, Praburam GOPALRAJA
  • Patent number: 8852417
    Abstract: Processes and systems for electrolytically processing a microfeature workpiece with a first processing fluid and a counter electrode are described. Microfeature workpieces are electrolytically processed using a first processing fluid, a counter electrode, a second processing fluid, and an anion permeable barrier layer. The anion permeable barrier layer separates the first processing fluid from the second processing fluid while allowing certain anionic species to transfer between the two fluids. Some of the described processes produce deposits over repeated plating cycles that exhibit resistivity values within desired ranges.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 7, 2014
    Assignee: APPLIED Materials, Inc.
    Inventors: Rajesh Baskaran, Robert W. Batz, Jr., Bioh Kim, Tom L. Ritzdorf, John Lee Klocke, Kyle M. Hanson
  • Patent number: 8826528
    Abstract: Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: September 9, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Steven D. Theiss, Michael A. Haase
  • Publication number: 20140231265
    Abstract: Microelectronic packages may be formed using the co-deposition of carbon nanotubes. The carbon nanotubes may be functionalized to have an appropriate charge so they can be combined with other materials to give suitable properties. The other materials that are co-deposited may include metals, ceramics, and polymers. The electronic package components may be formed including thermal interface materials, vias, trenches, capacitors, memories, substrates, and substrate cores, as a few examples.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Inventors: Vijay S. Wakharkar, Nachiket R. Raravikar
  • Publication number: 20140217612
    Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Erdem Kaltalioglu, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8795502
    Abstract: A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Harold J. Hovel, Devendra K. Sadana, Xiaoyan Shao, Steven Erik Steen
  • Patent number: 8795505
    Abstract: A copper electroplating method including dipping a substrate in a copper electroplating solution, the substrate including a seed layer; and forming a copper electroplating layer on the seed layer, wherein the copper electroplating solution includes water, a copper supply source, an electrolytic material, and a first additive, the first additive includes a compound represented by Formula 1, below:
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 5, 2014
    Assignees: Samsung Electronics Co., Ltd., Adeka Corporation
    Inventors: Myung-Beom Park, Jung-Sik Choi, Ki-Hyeon Kim, Yuji Morishima, Shin-ichi Tanaka, Takashi Yamada, Takehiro Zushi
  • Publication number: 20140209476
    Abstract: Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point.
    Type: Application
    Filed: January 29, 2013
    Publication date: July 31, 2014
    Inventors: Jian Zhou, Jon Reid
  • Patent number: 8791005
    Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 8790504
    Abstract: There is provided a method of manufacturing a wiring substrate. The method includes: (a) forming a first resist layer having first openings therein on a first surface of a support plate, forming first plated films in the first openings by an electrolytic plating method, and removing the first resist layer; (b) forming a second resist layer having second openings therein on the first surface of the support plate, forming second plated films in the second openings by an electrolytic plating method, and removing the second resist layer; (c) forming a wiring layer and an insulating layer such that the wiring layer is electrically connected to the first and second plated films; and (d) removing the support plate to expose the first and second plated films.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: July 29, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Kotaro Kodani
  • Patent number: 8771495
    Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: July 8, 2014
    Assignee: Enthone Inc.
    Inventors: Vincent Paneccasio, Jr., Xuan Lin, Richard Hurtubise, Qingyun Chen