Abstract: A redistribution layer structure and the manufacturing method thereof are provided. The redistribution layer structure includes a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer. The first dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the second metal layer. A chemical resistance of the first dielectric layer is greater than a chemical resistance of the second dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.

Abstract: A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.

Abstract: An aqueous composition for use in activating surface of polymers.

Abstract: A method for locating a faulty photovoltaic (PV) panel includes controlling an unmanned aerial vehicle (UAV) to fly and perform image capturing, obtaining image information of the PV panel captured by a camera carried by the UAV, obtaining global positioning (GPS) information of the UAV and attitude information of the camera at a shooting time when the camera captures the image information, and, in response to determining that the image information includes fault information of the PV panel, determining a position of the PV panel according to the GPS information of the UAV and the attitude information of the camera at the shooting time.

Abstract: The present disclosure illustrates a vertical electroplating module and an electroplating method for a fan-out panel level chip. The vertical electroplating module has an electroplating tank module, an exhaust tank module and a clamping module. A first box of the electroplating tank module has a first receiving chamber, a second receiving chamber and a third receiving chamber, the first receiving chamber is communicated with a bottom of the second receiving chamber, and a top of the second receiving chamber is communicated with the third receiving chamber. The exhaust tank module is communicated with the first receiving chamber and the third receiving chamber respectively via a first pump and a second pump. The clamping module is disposed around the opening on a wall of the second receiving chamber. The production made by the vertical electroplating module can meet a single-side production, without immersing the entire product in the chemical medicine.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 ?m to 30 ?m; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

Abstract: Exemplary substrate locking system, device, apparatus and method for chemical and/or electrolytic surface treatment of a substrate in a process fluid can be provided. For example, it is possible to provide a first element, a second element and a locking unit. The first element and the second element can be configured to hold the substrate between each other. The locking unit can be configured to lock the first element and the second element with each other. The locking unit can comprise a magnet control device and a magnet. The magnet can be arranged at or near the first element and/or the second element. The magnet control device can be configured to control a magnetic force between the first element and the second element.

Abstract: A substrate processing system includes a first processing block, a second processing block, and a reversing device. The first processing block includes a first processing unit configured to perform a process on a substrate with a first surface of the substrate facing upward, and a first transfer device configured to carry the substrate into/from the first processing unit. The second processing block includes a second processing unit configured to perform a process on the substrate with a second surface of the substrate, which is opposite to the first surface, facing upward, and a second transfer device configured to carry the substrate into/from the second processing unit. The reversing device is provided on a transfer path of the substrate from the first processing block to the second processing block, and is configured to reverse the substrate.

Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a compound thin film, which includes configuring an electrodeposition circuit by connecting an electrolytic solution, which is manufactured by mixing a predetermined precursor with a solvent, and an electrochemical cell, which includes a working electrode in a form of an electrode at which a specific pattern is patterned on a predetermined substrate, to a voltage application device or a current application device, and applying a reduction voltage or current to the working electrode using the voltage application device or the current application device, and selectively electrodepositing a thin film in some region of the electrode along a shape of the electrode at which the specific pattern is patterned.

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

Abstract: The present invention relates to an electrolytic copper foil for a secondary battery and a method of producing the same. The electrolytic copper foil for a secondary battery, in which a burr and curl of a negative electrode plate are inhibited from being formed after an electrolytic copper foil is coated with a negative electrode active material, thereby increasing the loading volume of a negative electrode and increasing a capacity. The electrolytic copper foil for a secondary battery is produced from a plating solution containing Total Organic Carbon (TOC) by using a drum, in which the electrolytic copper foil is formed of one surface that is in direct contact with the drum and the other surface that is an opposite surface of the one surface, and an average cross-sectional grain size of the one surface is 80% or less of an average cross-sectional grain size of the other surface.

Abstract: An apparatus for electroplating metal on a semiconductor substrate with improved plating uniformity includes in one aspect: a plating chamber configured to contain an electrolyte and an anode; a substrate holder configured to hold the semiconductor substrate; and an ionically resistive ionically permeable element comprising a substantially planar substrate-facing surface and an opposing surface, wherein the element allows for flow of ionic current towards the substrate during electroplating, and wherein the element comprises a region having varied local resistivity. In one example the resistivity of the element is varied by varying the thickness of the element. In some embodiments the thickness of the element is gradually reduced in a radial direction from the edge of the element to the center of the element. The provided apparatus and methods are particularly useful for electroplating metal in WLP recessed features.

Abstract: A plating method for plating a substrate having resist opening portions is provided. The plating method includes a resist residue removing step of removing resist residues in the resist opening portions of the substrate by spraying first process liquid to a surface of the substrate on which the resist opening portions are formed, a liquid filling step of soaking the substrate passed through the removing step in second process liquid to fill the resist opening portions of the substrate with the second process liquid, and a plating step of plating the substrate passed through the liquid filling step.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: An electroplating solution analyzer includes an analysis container for housing an electroplating solution containing additives including an accelerator and a suppressor, a working electrode that is immersed in the electroplating solution housed in the analysis container to exchange electrons therewith, a reference electrode immersed in the electroplating solution and serves as a reference for determining a potential of the working electrode, a counter electrode immersed in the electroplating solution, a rotation drive unit for rotating the working electrode at a constant speed, a current-generating unit for supplying a current with a constant current density between the working electrode and the counter electrode, a potential measuring unit for measuring a potential between the working electrode and the reference electrode, and an analyzing unit for determining a condition of the electroplating solution in one or more measurement sections at an elapsed time after the current starts to be supplied.

Abstract: A chip card manufacturing method. A module includes a substrate supporting contacts on one surface and conductive paths and a chip on another; and an antenna on a holder, the antenna including a contact pad for respectively connecting to each of the ends thereof. A solder drop is placed on each of the contact pads of the antenna. The holder of the antenna is inserted between plastic layers. A cavity is provided, in which the module can be accommodated and the solder drops remain accessible. The height of the solder drops before heating is suitable for projecting into the cavity. A module is placed in each cavity. The areas of the module that are located on the solder drops are heated to melt the solder and to solder the contact pads of the antenna to conductive paths of the module.

Abstract: A surface mount structure includes a substrate, a sensor, an electrical contact and a package body. The substrate has a first surface and a second surface opposite to the first surface. The sensor is disposed adjacent to the second surface of the substrate. The electrical contact is disposed on the first surface of the substrate. The package body covers the first surface and the second surface of the substrate, a portion of the sensor and a first portion of the electrical contact.

Abstract: This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.

Abstract: A method provides a structure that includes a substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer. The method further includes immersing the structure in a plating bath contained in an electroplating cell, the plating bath containing a selected solder material; applying a voltage potential to the structure, where the structure functions as a working electrode in combination with a reference electrode and a counter electrode that are also immersed in the plating bath; and maintaining the voltage potential at a predetermined value to deposit the selected solder material selectively only on the metal feature and not on the metal layer. An apparatus configured to practice the method is also disclosed.

Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: A display apparatus includes a display panel including a display substrate on which a plurality of pad terminals is disposed, and a driving unit including a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.

Abstract: Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point.

Abstract: A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times.

Abstract: A metal bump structure for use in a driver IC includes a metal bump disposed on a matrix, an optional capping layer disposed on the metal bump to completely cover the metal bump and a protective layer disposed on the metal bump to completely cover and protect the metal bump or the optional capping layer and so that the metal bump is not exposed to an ambient atmosphere. The protective layer or the optional capping layer may have a fringe disposed on the matrix.

Abstract: A flexible printed circuit board with reduced ion migration from signal-carrying elements which are coated against corrosion includes an insulating layer, a wiring area, a copper electroplating layer, a nickel electroplating layer, a cover film, and a gold chemical-plating layer. The wiring area is formed on the insulating layer. The copper electroplating layer formed on the wiring area has a first portion and a second portion. The nickel electroplating layer is formed on at least the first portion and exposes sidewalls of the first portion. The cover film is formed on the second portion and fills in gaps of the copper electroplating layer. The gold chemical-plating layer is formed on top surface of the nickel electroplating layer and the sidewalls of the first portion.

Abstract: The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.

Abstract: A method of electroplating on a workpiece having at least one sub-30 nm feature includes applying a first electrolyte chemistry to the workpiece, the chemistry including a metal cation solute species having a concentration in the range of about 50 mM to about 250 mM and a suppressor resulting in polarization greater than 0.75 V and reaching 0.75 V of polarization at a rate greater than 0.25 V/s, and applying an electric waveform, wherein the electric waveform includes a period of ramping up of current followed by a period of partial ramping down of current.

Abstract: A bonding structure and a method of fabricating the same are provided. A first substrate having a first bonding element and a second substrate having a second bonding element are provided, wherein at least one of the first bonding element and the second bonding element is formed with an alloy. A bonding process is performed to bond the first bonding element with the second bonding element, wherein a diffusion liner is generated at the exposed, non-bonded surface of the bonding structure.

Abstract: In some aspects, a quantum information processing circuit includes a lumped-element device on the surface of a dielectric substrate. The lumped-element device can include a capacitor pad and an inductive transmission line. The capacitor pad can be capacitively coupled to another capacitor pad. The inductive transmission line can reside in an interior clearance area defined by an inner boundary of the capacitor pad. The lumped-element device can be, for example, a resonator device or a filter device. The inductive transmission line can be, for example, a meander inductor.

Abstract: A substrate plating apparatus is disclosed. The apparatus includes a substrate holder; a plating bath configured to plate a surface of the substrate in a plating solution; a cleaning bath configured to clean the substrate holder and the substrate with a cleaning liquid; an inner shell disposed in the cleaning bath and configured to house the substrate holder holding the substrate therein; and a cleaning liquid supply conduit configured to supply a cleaning liquid into the inner shell to clean the substrate, together with the substrate holder, with the cleaning liquid. The inner shell has an inner surface having an uneven configuration that follows an uneven exterior configuration of the substrate holder holding the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

Abstract: A non-uniform initial metal film is non-uniformly deplated to provide a more uniform metal film on a substrate. Electrochemical deplating may be performed by placing the substrate in a deplating bath formulated specifically for deplating, rather than for plating. The deplating bath may have a throwing power of 0.3 or less; or a bath conductivity of 1 mS/cm to 250 mS/cm. Reverse electrical current conducted through the deplating bath non-uniformly. electro-etches or deplates the metal film.

Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

Abstract: Disclosed herein are cups for engaging wafers during electroplating in clamshell assemblies and supplying electrical current to the wafers during electroplating. The cup can comprise an elastomeric seal disposed on the cup and configured to engage the wafer during electroplating, where upon engagement the elastomeric seal substantially excludes plating solution from a peripheral region of the wafer, and where the elastomeric seal and the cup are annular in shape, and comprise one or more contact elements for supplying electrical current to the wafer during electroplating, the one or more contact elements attached to and extending inwardly towards a center of the cup from a metal strip disposed over the elastomeric seal. A notch area of the cup can have a protrusion or an insulated portion on a portion of a bottom surface of the cup where the notch area is aligned with a notch in the wafer.

Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.

Abstract: The present disclosure relates to an electro-chemical plating (ECP) process which utilizes a dummy electrode as a cathode to perform plating for sustained idle times to mitigate additive dissociation. The dummy electrode also allows for localized plating function to improve product gapfill, and decrease wafer non-uniformity. A wide range of electroplating recipes may be applied with this strategy, comprising current plating up to approximately 200 Amps, localized plating with a resolution of approximately 1 mm, and reverse plating to remove material from the dummy electrode accumulated during the dummy plating process and replenish ionic material within the electroplating solution.

Abstract: A machine for the electrochemical marking treatment of metallic surfaces, includes an electrode placed in sliding movement on the metallic surface to be treated, a buffer impregnated with etching solution for the specific metal in treatment, and an electric current circuit, suitable for electro-marking treatment of said metal, with a conductor connected to the electrode and the other conductor connected to the metallic surface in treatment; and presents to treat large metallic surfaces on plates, metal canvas or on metallic sheet in coil.

Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Abstract: In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A process for separating organic compounds from a mixture by reverse-phase displacement chromatography, including providing a hydrophobic stationary phase; applying to the hydrophobic stationary phase a mixture comprising organic compounds to be separated; displacing the organic compounds from the hydrophobic stationary phase by applying thereto an aqueous composition comprising a non-surface active hydrophobic neutral zwitterionic displacer molecule and optionally an organic solvent; and collecting a plurality of fractions eluted from the hydrophobic stationary phase containing the separated organic compounds; in which the non-surface active hydrophobic neutral zwitterionic displacer molecule comprises a hydrophobic zwitterion having the general formula, as defined in the disclosure: [CM-R*—CM?].

Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.

Abstract: Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (TSVs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a pH of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as NiB and NiP. The pre-wetting liquid is preferably degassed prior to contact with the wafer substrate. The pretreatment is preferably performed under subatmospheric pressure to prevent bubble formation within the recessed features. After the wafer is pretreated, a metal, such as copper, is electrodeposited from an acidic electroplating solution to fill the recessed features on the wafer. The described pretreatment minimizes corrosion of seed layer during electroplating and reduces plating defects.

Abstract: The present invention provides a non-cyanogen type electrolytic gold plating solution, which can form a plating film capable of maintaining a high hardness even when the plating film is subjected to a heat treatment. A non-cyanogen type electrolytic gold plating solution of the present invention includes: a gold source including an alkaline salt of gold sulfite or ammonium of gold sulfite; and a conductive salt including sulfite and sulfate. The non-cyanogen type electrolytic gold plating solution includes a salt of at least one of iridium, ruthenium, and rhodium in a metal concentration of 1 to 3000 mg/L. Further, the non-cyanogen type electrolytic gold plating solution preferably includes a crystal adjuster. The crystal adjuster is particularly preferably thallium.

Abstract: Solid state thermoelectric energy conversion devices can provide electrical energy from heat flow, creating energy, or inversely, provide cooling through applying energy. Thick film methods are applied to fabricate thermoelectric device structures using microstructures formed through deposition and subsequent thermal processing conditions. An advantageous coincidence of material properties makes possible a wide variety of unique microstructures that are easily applied for the fabrication of device structures in general. As an example, a direct bond process is applied to fabricate thermoelectric semiconductor thick films on substrates by printing and subsequent thermal processing to form unique microstructures which can be densified. Bismuth and antimony telluride are directly bonded to flexible nickel substrates.

Abstract: A method for fabricating a heat sink may include: providing a carbon fiber fabric having carbon fibers and openings, the openings leading from a first side to a second side of the fabric; and electroplating the fabric with metal, wherein metal is deposited with a higher rate at the first side than at the second side of the fabric. Another method for fabricating a heat sink may include: providing a carbon metal composite having metal-coated carbon fibers and openings, the openings leading from a first side to a second side of the carbon metal composite; disposing the composite over a semiconductor element such that the first side of the composite faces the semiconductor element; and bonding the composite to the semiconductor element by means of an electroplating process, wherein metal electrolyte is supplied to an interface between the carbon metal composite and the semiconductor element via the openings.

Abstract: A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region.

Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.