Predominantly Nonmetal Electrolytic Coating (e.g., Anodic Oxide, Etc.) Patents (Class 205/124)
  • Patent number: 6039857
    Abstract: The present invention relates to a method for forming a polyoxide film on a doped polysilicon layer, which is suitable for use as an inter-polysilicon polyoxide film between a doped polysilicon floating gate and a doped polysilicon control gate. The method includes conducting an electrolytic reaction at a room, temperature such that a polyoxide layer is formed on a doped polysilicon layer acting as an anode. The polyoxide layer is preferably further subjected with a rapid thermal processing to improve its electrical characteristics.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: March 21, 2000
    Inventors: Ching-Fa Yeh, Jeng-Shu Liu
  • Patent number: 6030517
    Abstract: Process for depositing a film of a metal oxide or of a metal hydroxide on a substrate in an electrochemical cell, wherein (i) the metal hydroxide is of formula M(OH).sub.x A.sub.y, M representing at least one metallic species in an oxidation state i chosen from the elements in Groups II and III of the Periodic Table, A being an anion whose number of charges is n, 0<x.ltoreq.i and x+ny=i,(ii) the electrochemical cell comprises (a) an electrode comprising the substrate, (b) a counterelectrode, (c) a reference electrode and (d) an electrolyte comprising a conducting solution comprising at least one salt of the metal M, the process comprising the steps of:dissolving oxygen in the electrolyte andimposing a cathode potential of less than the oxygen reduction potential and greater than the potential for deposition of the metal M in the electrolyte in question on the electrochemical cell.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: February 29, 2000
    Assignee: Centre National de la Recherche Scientifique
    Inventors: Daniel Lincot, Sophie Peulon
  • Patent number: 5997713
    Abstract: An element with elongated, high aspect ratio channels such as microchannel plate is fabricated by electrochemical etching of a p-type silicon element in a electrolyte to form channels extending through the element. The electrolyte may be an aqueous electrolyte. For use as a microchannel plate, the; the silicon surfaces of the channels can be converted to insulating silicon dioxide, and a dynode material with a high electron emissivity can be deposited onto the insulating surfaces of the channels. New dynode materials are also disclosed.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: December 7, 1999
    Assignee: NanoSciences Corporation
    Inventors: Charles P. Beetz, Jr., Robert W. Boerstler, John Steinbeck, David R. Winn
  • Patent number: 5911864
    Abstract: The present invention provides for a wet etch and method for preparing a semiconductor device structure from a silicon carbide wafer. A first embodiment of the wet etch comprises a vessel, a tetrahydrofurfuryl alcohol and potassium nitrite etching solution within the vessel, an electrode, a wafer support for positioning at least a portion of the silicon carbide wafer within the etching solution, and a voltage source coupled with the electrode and the wafer support. A second embodiment of the wet etch comprises a wafer carrier for holding at least one wafer, a polishing plate adjacent the wafer carrier, a voltage source having a first terminal electrically coupled with the wafer and a second terminal electrically coupled with the polishing plate, and an applicator adjacent the polishing plate for depositing an etching solution on a surface of the polishing plate.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: June 15, 1999
    Assignee: Northrop Grumman Corporation
    Inventor: Graeme W. Eldridge
  • Patent number: 5804466
    Abstract: A process for stably producing a zinc oxide thin film by electrolysis with excellent adhesion to a substrate is described. In particular, a zinc oxide thin film suitably used as a light confining layer of a photoelectric conversion element is formed on a conductive substrate by applying a current between a conductive substrate immersed in an aqueous solution containing at least nitrate ions, zinc ions, and a carbohydrate, and an electrode immersed in the solution.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: September 8, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kozo Arao, Katsumi Nakagawa, Takaharu Kondo, Yukiko Iwasaki
  • Patent number: 5795458
    Abstract: A thin film diode (8) between a data line (12) and a drive electrode (13), which is free from breakage in an upper layer film (4), is formed on one inner surface of a glass substrate (1) sealing a liquid crystal of a liquid crystal display device. To form such a thin film diode, a lower layer film (2) is formed on the glass substrate (1) such that the lower layer film (2) overlaps with the upper layer film (4) and the lower layer film (2) has a plurality of differences in level. An insulating film (3) is formed by oxidizing the surface of the lower layer film (2) with an anodic oxidation technique. The upper layer film (4) is formed, thereby completing the thin film diode. Alternately, an insulating film material (7,7') may be formed either on the lower layer film (2) or on the peripheral region thereof in the form of a film, and the insulating film (3) may be formed by oxidizing the insulating film material (7,7').
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: August 18, 1998
    Assignee: Citizen Watch Co., Ltd.
    Inventor: Kozo Miyoshi
  • Patent number: 5785838
    Abstract: The present invention provides a method for producing an oxide film wherein a sharp-pointed processing electrode is positioned close to the material to be processed in an oxygen-containing gas, and a voltage in the single digit range is impressed across the material and the electrode so that the surface of the material is positive and the electrode is negative thereby causing an electric current to flow across the material and the electrode. The surface of the material reacts electrochemically with oxygen adsorbed on the surface of the material to anodize the surface immediately proximate the electrode. The method makes possible the formation of a patterned oxide film with a resolution of 0.1 .mu.m or less, thus surpassing the limit of conventional oxide film production methods.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: July 28, 1998
    Assignee: Nikon Corporation by Hiroyuki Sugimura
    Inventors: Hiroyuki Sugimura, Tatsuya Uchida
  • Patent number: 5765680
    Abstract: An illumination source comprising a porous silicon having a source of electrons on the surface and/or interticies thereof having a total porosity in the range of from about 50 v/o to about 90 v/o. Also disclosed are a tritiated porous silicon and a photovoltaic device and an illumination source of tritiated porous silicon.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: June 16, 1998
    Assignee: The University of Chicago
    Inventor: Shiu-Wing Tam
  • Patent number: 5747180
    Abstract: A method of fabricating two-dimensional regimented and quasi periodic arrays of metallic and semiconductor nanostructures (quantum dots) with diameters of .about.100 .ANG.(10 nm) includes the steps of polishing and anodizing a substrate to form a regimented quasi-periodic array of nanopits. The array forms a template for metallic or semiconductor material. The desired material is deposited in the nanopits by immersing the substrate in an appropriate solution and using the substrate as one cathode and inserting a second cathode in the solution.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: May 5, 1998
    Assignee: University of Notre Dame Du Lac
    Inventors: Albert E. Miller, Supriyo Bandyopadhyay
  • Patent number: 5747355
    Abstract: A method for producing a thin-film transistor (TFT) in which the gate electrode is offset from the source and drain without detriment to the characteristics of the device or to manufacturing yield, and a structure for such a TFT, are disclosed. A gate electrode is formed using a material capable of anodic oxidation, and a mask is formed on the gate electrode. Using a comparatively low voltage, a comparatively thick, porous anodic oxide film is formed on the sides of the gate electrode. The mask is then removed and using a comparatively high voltage a dense anodic oxide film is formed at least on the top of the gate electrode. Using the gate electrode having this anodic oxide on its top and sides as a mask, an impurity is introduced into the semiconductor film and an offset structure is obtained.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: May 5, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Takahiro Tsuji
  • Patent number: 5737041
    Abstract: Improved thin film transistors to reduce defects in the devices incorporating the transistors, including active matrix displays. A first improvement is accomplished by forming a dual insulator layer over the bottom metal layer, which can be the gate line and also the row line in an active matrix display. The first insulator layer is formed by anodizing the metal layer and the second insulator layer is deposited onto the first layer. The dual insulator structure layer can be reanodized to eliminate the effect of pinholes. A second improvement includes providing an interdigitated transistor structure to increase the channel width, minimize internal shorting and minimize the drain capacitance. The interdigitated structure includes at least one source or drain finger formed between at least two drain or source fingers, respectively. A shorted source finger can be disconnected to maintain an operative transistor.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: April 7, 1998
    Assignee: Image Quest Technologies, Inc.
    Inventors: Scott H. Holmberg, Ronald L. Huff
  • Patent number: 5705027
    Abstract: The method is to selectively etch the etching residue in non-conductive state occurring in semiconductor manufacturing process. A silicon substrate cassette is used in such selective etching.In removing the etching residue in non-conductive state occurring in semiconductor manufacturing process, by applying a positive potential to part of conductive silicon substrates in an etching solution, the contact surfaces between the silicon substrates and the portion electrically connected thereto and the chemical etching solution are anodically oxidized to protect with a passive film, while only the etching residue in non-conductive state is selectively removed by isotropic etching, thereby achieving the purpose.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: January 6, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiharu Katayama, Naoko Ootani
  • Patent number: 5685968
    Abstract: In a ceramic substrate with a thin-film capacitor, having a ceramic substrate a lower electrode layer formed on the ceramic substrate, a dielectric layer formed on the lower electrode layer and made of an oxide of a material constituting the lower electrode layer, and an upper electrode layer formed on the dielectric layer, a plating layer is provided between the ceramic base and the lower electrode layer to serve as a basis for the lower electrode layer.
    Type: Grant
    Filed: October 11, 1995
    Date of Patent: November 11, 1997
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Toshitaka Hayakawa, Shinobu Yoshida, Toshikatsu Takada
  • Patent number: 5681439
    Abstract: A specially configured intermediate structure used in a stage of selective anodization during the manufacture of a circuit. The specially configured intermediate structure includes: a metal line having at least two edges; and a photoresist mask applied over a portion of the metal line that is to remain unanodized. A configuration of each of the edges of the metal line is such that the length of each edge under the mask is greater than the length of the mask. The extra length of the specially configured edge prevents a problem in later stages of the circuit manufacture due to unwanted, and practically unpreventable, seepage of the anodic oxidation chemical under the mask, along the edge, by the anodic oxidation chemical.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: October 28, 1997
    Assignee: LG Electronics, Inc.
    Inventor: Jae Kyun Lee
  • Patent number: 5679234
    Abstract: A mask layer is formed on a conductive layer covering not only a central area assigned to integrated circuits but also a vacant peripheral area of a semiconductor wafer, and an electroplating system allows metallic miniature patterns to grow on the conductive layer over the vacant peripheral area as well as extremely small areas of the conductive layer over the central area so as to make current fluctuation negligible.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: October 21, 1997
    Assignee: NEC Corporation
    Inventor: Takafumi Imamura
  • Patent number: 5656147
    Abstract: When an anodized film is to be formed, one formation-voltage input point is used. An interconnecting ring for anodization is provided between the input point and a pattern to be anodized. The interconnecting ring is in contact with and encloses the pattern. Another interconnecting ring to which the formation-voltage input point is connected is provided around the interconnecting ring. In addition, two junction points are provided at vertically symmetric positions with respect to the pattern. The junction points are connected to the interconnecting ring. The junction points are connected to upper connection terminals and lower connection terminals of the pattern by respective thin-line groups including a plurality of thin lines. The formation voltages at respective input points at the upper connection terminals and the lower connection terminals of the pattern are made equal to each other.
    Type: Grant
    Filed: July 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihisa Ishimoto, Masahiro Kishida, Toshiyuki Yoshimizu
  • Patent number: 5643435
    Abstract: The present invention encompasses a semiconductor processing device having a processing chamber in which is positioned an electrolyte oxygen pump assembly and tubing for transferring an oxygen containing gas from outside the reaction chamber to within the interior of the electrolyte oxygen pump assembly and tubing for removal of the oxygen depleted gas from within the interior of the electrolyte oxygen pump assembly. In addition, the semiconductor processing tool may further have heating elements for heating a semiconductor substrate within the processing chamber independently from heating of the electrolyte.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: July 1, 1997
    Assignee: International Business Machines Corporation
    Inventors: Glenn F. Guhman, Madhukar L. Joshi
  • Patent number: 5595638
    Abstract: An anodic oxide containing impurities at a low concentration and thereby improved in film quality, and a process for fabricating the same. The process comprises increasing the current between a metallic thin film and a cathode until a voltage therebetween reaches a predetermined value, and maintaining the voltage at the predetermined value thereafter.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: January 21, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
  • Patent number: 5580825
    Abstract: A process for forming a multilevel electronic interconnect structure, the electronic interconnect structure having level conductive paths parallel to a substrate and interlevel electrical interconnections perpendicular to the substrate, the process comprising providing a main aluminum layer over the substrate surface, defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization.
    Type: Grant
    Filed: September 20, 1993
    Date of Patent: December 3, 1996
    Assignee: International Technology Exchange Corp.
    Inventors: Vladimir A. Labunov, Vitaly A. Sokol, Vladimir M. Parkun, Alla I. Vorob'yova
  • Patent number: 5503731
    Abstract: A first pair electrodes consisting of an anode to which a plurality of wiring lines to be anodized are connected and a cathode that is opposed to the anode, and a second pair electrodes for collecting impurities in a forming solution are immersed in a forming solution. A voltage is applied to the plurality of wiring lines in such a manner that at least one of the plurality of wiring lines receives the voltage for a different period than the other wiring lines.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: April 2, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Jun Koyama, Masaaki Hiroki, Shunpei Yamazaki
  • Patent number: 5501787
    Abstract: A system for making porous silicon on blank and patterned Si substrates by "immersion scanning", particularly suitable for fabricating light-emitting Si devices and utilizing an open electrolytic cell having a cathode and an opposing anode consisting of a Si substrate on which the porous silicon is to be formed, both disposed, with their opposing surfaces in parallel, in an aqueous HF solution electrolyte contained in the cell. The substrate anode is mounted to be movable relative to the electrolyte so as to be mechanically cycled or scanned in and out of the electrolyte at a programmable rate during anodization. The uniformity, thickness and porosity of the resulting anodized layer on the substrate are determined by the scanning speed, number of cycles, current density, and HF-based electrolyte parameters of the system, and the Si substrate resistivity, conductivity type, and crystal orientation.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: March 26, 1996
    Assignee: International Business Machines Corporation
    Inventors: Ernest Bassous, Jean-Marc Halbout, Subramanian S. Iyer, Vijay P. Kesan
  • Patent number: 5470636
    Abstract: A magnetic recording medium having a substrate made of aluminum or aluminum alloy and an anodic-oxide film, e.g., alumite film, formed by effecting the anodic oxidation process, wherein the surface of the alumite film has protruding portions formed in addition to micro-irregularities which are formed in response to the cell-pore structure of the alumite film and height of the protruding portions is higher than that of the micro-irregularity, and density of the protruding portions is ranging from 10.sup.2 to 10.sup.7 per one square millimeter, these protruding portions are formed by processing the alumite film in the fluorine-contained solution (e.g., hydrofluoric acid) or in solution containing one of the acid (HCl), base (NaOH) and strong-acid salt ((NH.sub.4)SO.sub.4), Cr film and magnetic film are sequentially formed on the alumite film by the sputtering process.
    Type: Grant
    Filed: March 13, 1992
    Date of Patent: November 28, 1995
    Assignee: Yamaha Corporation
    Inventors: Yukio Wakui, Yoshiki Nishitani, Kenichi Miyazawa
  • Patent number: 5391269
    Abstract: We have found that etching of a body that comprises exposed Si as well as a Ti-comprising metal layer (e.g., a patterned Ti/Pt layer) in an amine-based anisotropic etchant for Si (e.g., 100.degree. C. EDP) frequently results in undesirable changes in the Ti-comprising metal layer. We have also found that the changes can be substantially reduced or eliminated by electrolytic means, namely, by making the metal layer the anode in an electrolytic cell that contains the etchant.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: February 21, 1995
    Assignee: AT&T Corp.
    Inventors: Jason O. Fiering, Barry Miller, Joseph Shmulovich
  • Patent number: 5296126
    Abstract: The present invention concerns a method for processing an etched surface of a semiconductive or semi-insulating substrate. It further concerns integrated circuits manufactured by this method and an anodic oxidation apparatus for implementing the method. The invention is particularly applicable to the manufacture of integrated circuits with ultrafine details (below 1.mu.) and in particular to manufacturing electro-optical devices. Anodic oxidation with controlled voltage and current is used to peel a constant thickness of oxidation off a surface of the substrate so as to improve the subsequent epitaxial growth.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: March 22, 1994
    Assignee: France Telecom
    Inventor: Alice Izrael
  • Patent number: 5277786
    Abstract: A process for producing a photoelectric conversion device comprising a substrate having a conductive surface, a semiconductor layer disposed on said conductive surface of said substrate, a transparent and conductive layer disposed on said semiconductor layer and a collecting electrode disposed on said transparent and conductive layer, wherein one or more defective portions formed at the semiconductor layer are repaired by means of electrolytic treatment using an electrolytic solution containing a material capable of providing an insulating material, wherein the conductive surface of the substrate is made an electrode, to thereby deposit an insulating material selectively at each of the defective portions.
    Type: Grant
    Filed: February 19, 1992
    Date of Patent: January 11, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Soichiro Kawakami
  • Patent number: 5240868
    Abstract: A method of fabricating a metal electrode of a semiconductor device that includes a substrate with unanodized and anodized metal layers thereon includes the steps of forming a first metal layer, which is anodizable, to a first predetermined thickness on a substrate; forming and patterning a second metal layer, which is not anodizable, to a second predetermined thickness so as to act as a mask on the first metal layer; depositing a third metal layer, that may be anodizable, to a third predetermined thickness; and forming a flat surface on the third layer by anodic oxidation. Various preferred embodiments and relationships between thickness of each layer for flattening by anodic oxidation are also given.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: August 31, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byungseong Bae, Jeongha Sohn, Insik Jang, Sangsoo Kim, Namdeog Kim, Hyungtaek Kim
  • Patent number: 5192400
    Abstract: Solar cells are formed of semi-conductor spheres of P-type interior having an N-type skin are pressed between a pair of aluminum foil members forming the electrical contacts to the P-type and N-type regions. The aluminum foils, which comprise 1.0% silicon by weight, are flexible and electrically insulated from one another. The spheres are patterned in a foil matrix forming a cell. Multiple cells can be interconnected to form a module of solar cell elements for converting sun light into electricity.
    Type: Grant
    Filed: July 31, 1989
    Date of Patent: March 9, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Sidney G. Parker, Milfred D. Hammerbacher, Jules D. Levine, Gregory B. Hotchkiss
  • Patent number: 5141603
    Abstract: Capacitor structure capable of achieving increased energy storage density is disclosed together with a fabrication sequence for the capacitor and its anodic oxide dielectric material. Soft porous aluminum oxide which has been formed in a first anodization step and has been densified or transformed to hard barrier oxide in a second anodization step is preferred for the capacitor dielectric material. The first anodization may be performed in a sulfuric acid electrolyte while the second anodization may be performed in a boric acid electrolyte. The boric acid may be diluted with ethylene glycol. The disclosed capacitor is fabricated on a silicon wafer substrate.
    Type: Grant
    Filed: October 11, 1990
    Date of Patent: August 25, 1992
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: John R. Dickey, Jimmy L. Davidson, Yonhua Tzeng