Abstract: A method for manufacturing a flexible circuit electrode array, comprising: a) depositing a metal trace layer containing a base coating layer, a conducting layer and a top coating layer on the insulator polymer base layer; b) applying a layer of photoresist on the metal trace layer and patterning the metal trace layer and forming metal traces on the insulator polymer base layer; c) activating the insulator polymer base layer and depositing a top insulator polymer layer and forming one single insulating polymer layer with the base insulator polymer layer; d) applying a thin metal layer and a layer of photoresist on the surface of the insulator polymer layer and selective etching the insulator layer and the top coating layer to obtain at least one via; and e) filling the via with electrode material. A layer of polymer is laid down. A layer of metal is applied to the polymer and patterned to create electrodes and leads for those electrodes.

Abstract: A method of etching a copper (Cu) thin film and a Cu thin film prepared therefrom, the method including patterning a hard mask layer on the Cu thin film to form a hard mask on the Cu thin film; forming a plasma of a mixed gas, the mixed gas including an inert gas and an organic chelator material including an amine group, the mixed gas not including a halogen gas or a halide gas; and etching the Cu thin film through the hard mask using the plasma generated in the forming of the plasma of the mixed gas.

Abstract: A microetching agent is an acidic aqueous solution containing an organic acid, cupric ions, and halide ions. The molar concentration of halide ion of the microetching agent is 0.005 to 0.1 mol/L. By bringing the microetching agent into contact with a copper surface, the copper surface is roughened. An average etching amount in the depth direction during roughening is preferably 0.4 ?m or less. The microetching agent can impart on copper surfaces a roughened shape having excellent adhesiveness to resins and the like, even with a low etching amount.

Abstract: In an embodiments, a coil component includes: an element body part 10 and a coil 30 of spiral shape constituted by multiple winding conductors 32 and through hole conductors 34 that interconnect the winding conductors 32; wherein each winding conductor 32 has, in a cross-sectional view in the width direction of the winding conductor 32, a flat side 40 that extends in a second direction substantially perpendicular to the coil axis of the coil 30; and the point of intersection 48 between a figure line 42 corresponding to the longest part in a first direction, and a figure line 44 corresponding to the longest part in the second direction, with respect to the coil axis, is positioned on the figure line 42 within one-quarter of the figure line away from one end 50 on the side 40 or from the other end 52 opposing the side 40.

Abstract: A ceramic and plastic composite and a method for fabricating the same are disclosed. A chemical cleaning treatment, a microetching treatment, a hole reaming treatment, and a surface activating treatment are performed on the surface of a ceramic matrix to form nanoholes with an average diameter ranging between 150 nm and 450 nm. Plastics are injected onto the surface of the baked ceramic matrix to form a plastic layer. The plastic layer more deeply fills the nanoholes to have higher adhesion. Thus, the higher combined strength and air tightness exist between the ceramic matrix and the plastic layer to improve the reliability and the using performance of the ceramic and plastic composite.

Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

Abstract: An etching solution for copper and copper alloy surfaces comprising at least one acid, at least one oxidising agent suitable to oxidise copper, at least one source of halide ions and further at least one polyamide containing at least one polymeric moiety according to formula (I) wherein each a is independently from each other selected from 1, 2 and 3; each b is an integer independently from each other ranging from 5 to 10000; each R1 is a monovalent residue independently from each other selected from the group consisting of substituted or unsubstituted C1-C8-alkyl groups and a method for its use are provided. Such etching solution is particularly useful for retaining the shape of treated copper and copper alloy lines.

Abstract: A method for making a glass dielectric capacitor may include providing a plurality of foil sheets, cutting each of the plurality of foil sheets with a laser beam by melting each of the plurality of foil sheets, forming a respective smooth foil edge on each of said plurality of foil sheets during the cutting, providing a plurality of glass sheets, and stacking the plurality of foil sheets in alternating layers with the plurality of glass sheets.

Abstract: The printed circuit board with at least one substrate layer having signal lines on a corresponding upper surface and on a corresponding lower surface has a sleeve-sized conductive layer on a circumference of at least one via hole between the upper and lower surface for a conductive connection between at least one signal line on the upper surface and at least one signal line on the lower surface. An axial enlargement of the sleeve-sized conductive layer is radially bent above a base layer of copper on the upper surface and below a base layer of copper on the lower surface.

Abstract: A method for manufacturing a flexible circuit electrode array adapted to electrically communicate with organic tissue including the following steps: a) providing a flexible polymer base layer; b) curing the base layer; c) depositing a metal layer on base layer; d) patterning the metal layer and forming metal traces on the base layer; e) roughening the surface of the base layer; f) chemically reverting the cure of the surface of the base layer; g) depositing a flexible polymer top layer on the surface of the base layer and the metal traces; h) curing the top layer and the surface of the base layer forming one single flexible polymer layer; and i) creating openings through the single layer to the metal trace layer.

Abstract: An etchant for copper includes an acid and one or more compounds selected from the group consisting of an aliphatic noncyclic compound, an aliphatic heterocyclic compound and a heteroaromatic compound. The aliphatic noncyclic compound is a saturated aliphatic noncyclic compound (A) including only two or more nitrogen atoms as heteroatoms, and 2 to 10 carbon atoms. The aliphatic heterocyclic compound is a compound (B) including a five-, six-, or seven-membered ring having one or more nitrogen atoms as one or more heteroatoms constituting the ring. The heteroaromatic compound is a compound (C) including a six-membered heteroaromatic ring having one or more nitrogen atoms as one or more heteroatoms constituting the ring.

Abstract: A fragmentation pattern is formed on a surface of a warhead using a lithographic process. A photoresistant material is coated on an interior surface of the warhead casing. A portion of the photoresistant material is selectively cured by projecting an image of the fragmentation pattern onto the photoresistant material. The uncured portion of the photoresistant material is removed and an etchant is applied to the exposed portion of the warhead casing surface thereby etching the fragmentation pattern. Alternatively, a protective coating is applied over the entire surface thereby creating the fragmentation pattern.

Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Abstract: A PCB includes a base layer, a wiring pattern formed on a surface of the base layer, and a protecting layer formed on the wiring pattern. The protecting layer is formed by printing and solidifying an ink on the wiring pattern. The ink includes a cycloaliphatic epoxy resin, a phenoxyl resin solution, a solvent, a hardener, and an antifoaming agent.

Abstract: The present document discloses motors and motor components that are constructed on a planar substrate. In some implementations, the planar substrate is made from rigid or semi-rigid sheet material, such as a printed circuit board (“PCB”). One or more coils are formed using spiral-shaped conductive traces that overlay the front and/or back surfaces of the substrate. In one implementation, a plurality of alternating right-hand and left-hand spiral-shaped conductive traces are separated by insulating layers, and connected with conductive vias to form inductive coils. Alternative coil-configurations include single-drive counter-wound coils and coils having a central ferrous or magnetic core.

Abstract: A semiconductor device has a module structure in which a semiconductor element and a circuit layer are electrically connected to each other by a wire. A front metal layer is formed on a surface of a top side electrode of the semiconductor element and the wire is bonded to the front metal layer by wire bonding. The front metal layer has a higher hardness than the top side electrode or the wire. A bonding interface of the wire with the metal film has a recrystallization temperature that is equal to or higher than 175° C. According to this structure, it is possible to improve the power cycle resistance of the semiconductor device.

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

Abstract: A printed wiring board includes an insulating substrate having a penetrating hole formed through the substrate, a first conductive pattern formed on first surface of the substrate, a second conductive pattern formed on second surface of the substrate on the opposite side of the first surface, and a through-hole conductor formed in the penetrating hole in the substrate such that the conductor is connecting the first conductive pattern on the first surface of the substrate and the second conductive pattern on the second surface of the substrate. The penetrating hole has a first opening portion opening on the first surface of the substrate, a second opening portion opening on the second surface of the substrate and a third opening portion connecting the first and second opening portions, and the third opening portion has the maximum diameter which is greater than the minimum diameters of the first and second opening portions.

Abstract: A method of forming an implant to be implanted into living bone is disclosed. The method comprises the act of roughening at least a portion of the implant surface to produce a microscale roughened surface. The method further comprises the act of immersing the microscale roughened surface into a solution containing hydrogen peroxide and a basic solution to produce a nanoscale roughened surface consisting of nanopitting superimposed on the microscale roughened surface. The nanoscale roughened surface has a property that promotes osseointegration.

Abstract: A method for preparing a copper alloy given a certain special surface shape yields tremendous bonding strength through compatibility with an epoxy resin adhesive. With a composite part in which this technology is utilized to integrate a copper alloy member as a cover material with a CFRP, it is possible to take advantage of the characteristics of both the copper alloy and the FRP due to the tremendous bonding strength. In a step in which an FRP prepreg is put into a mold and heated and cured, usually the mold is first coated with a release agent to facilitate release from the mold, but with high-technology CFRP, bleeding of the release agent often diminishes the properties. A copper alloy sheet 21 is used as a cover material, and a CFRP 22 is cured.

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract: A layer of a metal selected from titanium, niobium, tungsten, molybdenum, ruthenium, rhodium, arsenic, aluminum and gallium, an oxide of the metal, a nitride of the metal, silicon nitride, hafnium nitride, tantalum nitride, or an alloy of these metals, the layer being provided on an underlying base material selected from glass, silicon, copper and nickel, is selectively etched with an alkaline etching solution containing a predefined complexing agent.

Abstract: A method is described for etching ceramic phosphor converters. The method includes contacting a surface of the converter with a solution of phosphor acid for a time sufficient to etch the converter. The method is applicable to ceramic phosphor converters comprising a phosphor having a general formula MxAlyOz:RE wherein M is a metal and RE is a rare earth element.

Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.

Abstract: A copper foil for producing graphene including Cu having a purity of 99.95% by mass or more.

Abstract: Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.

Abstract: A polishing agent for copper polishing, comprising (A) an inorganic acid with divalent or greater valence, (B) an amino acid, (C) a protective film-forming agent, (D) an abrasive, (E) an oxidizing agent and (F) water, wherein the content of the component (A) is at least 0.08 mol/kg, the content of the component (B) is at least 0.20 mol/kg, the content of the component (C) is at least 0.02 mol/kg, and either or both of the following conditions (i) and (ii) are satisfied. (i): The proportion of the content of the component (A) with respect to the content of the component (C) is 2.00 or greater. (ii): It further comprises (G) at least one kind selected from among organic acids and their acid anhydrides.

Abstract: A polishing agent for copper polishing, comprising (A) an inorganic acid with divalent or greater valence, (B) an amino acid, (C) a protective film-forming agent, (D) an abrasive, (E) an oxidizing agent and (F) water, wherein the content of the component (A) is at least 0.08 mol/kg, the content of the component (B) is at least 0.20 mol/kg, the content of the component (C) is at least 0.02 mol/kg, and either or both of the following conditions (i) and (ii) are satisfied. (i): The proportion of the content of the component (A) with respect to the content of the component (C) is 2.00 or greater. (ii): It further comprises (G) at least one kind selected from among organic acids and their acid anhydrides.

Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.

Abstract: The present invention relates to graphene windows and methods for making same. One method comprises selecting a high purity metal foil, growing a layer of graphene on a first face of the metal foil, patterning the second face of the graphene-modified foil with a polymer, wherein the second face of the graphene-modified foil has an exposed region and etching the second face of the graphene-modified foil in the exposed region until exposing the first layer of graphene.

Abstract: A method of patterning a first material on a polymeric substrate is described. The method includes providing a polymeric film substrate having a major surface with a relief pattern including a recessed region and an adjacent raised region, depositing a first material onto the major surface of the polymeric film substrate to form a coated polymeric film substrate, forming a layer of a functionalizing material selectively on the raised region of the coated polymeric film substrate to form a functionalized raised region and an unfunctionalized recessed region, and etching the first material from the polymeric substrate selectively from the unfunctionalized recessed region.

Abstract: A method of forming a metal pattern on a display substrate includes blanket depositing a copper-based layer having a thickness between about 1,500 ? and about 5,500 ? on a base substrate, and forming a patterned photoresist layer on the copper-based layer. The copper-based layer is over-etched by an etching composition containing an oxidizing moderating agent where the over-etch factor is between about 40% and about 200% while using the patterned photoresist layer as an etch stopping layer, and where the etching composition includes ammonium persulfate between about 0.1% by weight and about 50% by weight, includes an azole-based compound between about 0.01% by weight and about 5% by weight and a remainder of water. Thus, reliability of the metal pattern and that of manufacturing a display substrate may be improved.

Abstract: Disclosed is a composition for and applying said method for micro etching of copper or copper alloys during manufacture of printed circuit boards. Said composition comprises a copper salt, a source of halide ions, a buffer system and a benzothiazole compound as an etch refiner. The inventive composition and method is especially useful for manufacture of printed circuit boards having structural features of ?100 ?m.

Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract: Provided in one embodiment is a method of forming a movable joint or connection between parts that move with respect to one another, wherein at least one part is at least partially enclosed by at least one second part. The method includes positioning an etchable material over an at least one first part, molding or forming an at least one second part over at least the etchable material, and removing the etchable material.

Abstract: A method for processing a surface involves depositing at least one class of enzymes (2) onto the surface (1); introducing at least a reactant (3) into an environment of the surface (1), and causing interaction between the enzymes (2) and the reactant (3), thereby to cause processing of a region of the surface (1), the processed region of the surface (1) being defined with respect to a region thereof that is proximate (4) to where the enzymes (3) have been deposited.

Abstract: A method for providing copper filled features in a layer is provided. A deposition of copper is provided to fill features in the layer. Tops of the copper deposit are cleaned to remove copper or copper oxide at tops of the copper deposit. A selective copper alloy plating on the tops of the copper deposit is provided. The copper deposit and selective copper alloy plating are annealed.

Abstract: A composition for providing acid resistance to copper surfaces in the production of multilayered printed circuit boards. The composition comprises an acid, an oxidizer, a five-membered heterocyclic compound and a thiophosphate or a phosphorous sulfide compound. In a preferred embodiment, the phosphorous compound is phosphorus pentasulfide. The composition is applied to a copper or copper alloy substrate and the copper substrate is thereafter bonded to a polymeric material.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.

Abstract: An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water.

Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.

Abstract: A printed circuit board includes a flexible insulated substrate with a first surface and a second surface at both sides respectively, a wiring layer on the first surface, a reinforcement plate on a part of the second surface and an auxiliary layer between the second surface and the reinforcement plate. A reinforcement edge side of the reinforcement plate is located at the outside of an auxiliary edge side of the auxiliary layer.

Abstract: A Cu-based material 5 is immersed into an alkali hydroxide solution with a concentration of 3.0 to 37.5 mass % and a H2O2 solution with a concentration of 3.0 to 50.0 mass % is added in the alkali hydroxide solution, a temperature of the alkali hydroxide solution when the Cu-based material is immersed ranges from 60 to 105° C., a ratio A/B between a mol number A of alkali hydroxide in the alkali hydroxide solution and a mol number B of H2O2 in the H2O2 solution is 10 or more, and where a mol number of Sn in the Sn layer is C and a mol number of Sn in the CuSn layer is D, B?C×2+D×6.

Abstract: The present invention discloses an etchant for etching at least two different metal layers, the etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—). The present invention also discloses a method of fabricating a metal wiring on a substrate, the method comprising forming a first metal layer on a substrate, forming a second metal layer on the first metal layer, and simultaneously etching the first metal layer and the second metal layer with an etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—).

Abstract: A method for processing a surface involves depositing at least one class of enzymes (2) onto the surface (1); introducing at least a reactant (3) into an environment of the surface (1), and causing interaction between the enzymes (2) and the reactant (3), thereby to cause processing of a region of the surface (1), the processed region of the surface (1) being defined with respect to a region thereof that is proximate (4) to where the enzymes (3) have been deposited.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: A method of manufacturing a wiring substrate of the present invention, includes the steps of forming a seed layer on an underlying layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a copper plating layer in the opening portion by an electroplating, removing the plating resist, wet-etching the seed layer using the copper plating layer as a mask to obtain the wiring layer, roughening a surface of the wiring layer by a blackening process, and forming an insulating layer on the wiring layer, wherein a surface of the copper plating layer is soft-etched simultaneously in the step of etching the seed layer, whereby a soft etching step of the wiring layer carried out prior to the step of the blackening process is omitted.

Abstract: A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH4+) and a chlorine ion (Cl?).

Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.