Abstract: A connector and a manufacturing method of the connector are provided. The connector, comprising an insulator (10), a first conductive layer (11) disposed on one side surface of the insulator (10), and a second conductive layer (12) disposed on the other side surface of the insulator (10), the insulator (10) is further provided with a conductive medium (13) connecting the first conductive layer (11) and the second conductive layer (12), and a protrusion portion (14) is disposed on the surface of the first conductive layer (11) or/and the second conductive layer (12).

Abstract: A method of manufacturing printed circuit boards includes some or all of: chemically or electrically applying metallic layers to a substrate; incorporating bores into the substrate; through-contacting the bores incorporated into the substrate; applying a layer from a photoresist to an electrically conducting layer in a masking step; exposing the photoresist while using an exposure mask in an exposing step; removing exposed or unexposed regions of the layer from the photoresist while in regions laying bare the electrically conducting layer in a developing step; removing the laid-bare regions of the electrically conducting layer in an etching step; cleaning the substrate in a rinsing step; and drying the substrate, wherein the substrate for carrying out the developing step and/or the etching step is set in rotation and a developer solution and/or an etching liquid is applied to the rotating substrate by at least one nozzle.

Abstract: A method of manufacturing printed circuit boards includes some or all of: chemically or electrically applying metallic layers to a substrate; incorporating bores into the substrate; through-contacting the bores incorporated into the substrate; applying a layer from a photoresist to an electrically conducting layer in a masking step; exposing the photoresist while using an exposure mask in an exposing step; removing exposed or unexposed regions of the layer from the photoresist while in regions laying bare the electrically conducting layer in a developing step; removing the laid-bare regions of the electrically conducting layer in an etching step; cleaning the substrate in a rinsing step; and drying the substrate, wherein the substrate for carrying out the developing step and/or the etching step is set in rotation and a developer solution and/or an etching liquid is applied to the rotating substrate by at least one nozzle.

Abstract: A chemical vapor deposition (CVD) process for producing diamond includes providing a CVD Growth Chamber containing a growth substrate, charging the CVD growth chamber with a source gas mixture that includes a carbon source gas, activating the gas mixture to facilitate growth of diamond on the growth substrate, and providing for a period of diamond growth in a static mode during which the gas mixture is sealed within the CVD growth chamber.

Abstract: Improved thin film coatings, cutting tool materials and processes for cutting tool applications are disclosed. A boron-doped graded diamond thin film for forming a highly adhesive surface coating on a cemented carbide (WC—Co) cutting tool material is provided. The thin film is fabricated in a HFCVD reactor. It is made of a bottom layer of BMCD in contact with a surface layer of the cemented carbide, a top layer made of NCD and a transition layer with a decreasing concentration gradient of boron obtained by changing the reaction conditions through ramp up option in hot filament CVD reactor. The top layer has a low friction coefficient. The bottom layer in the coating substrate interface has better interfacial adhesion through cobalt and boron reactivity and decreased cobalt diffusivity in the diamond. The transition layer has minimized lattice mismatch and sharp stress concentration between the top and bottom layers.

Abstract: New Te-salts are provided, including photoactive tellurium salt compounds useful for Extreme Ultraviolet Lithography.

Abstract: A method of aligning scans of a workpiece is disclosed, including coupling a set of reflective boundary targets along an edge of a workpiece having first and second opposing facial surfaces. The boundary targets are detectable by a surface scanning device when scanning the first facial surface and when scanning the second facial surface of the workpiece. The method further includes scanning the first facial surface of the workpiece, generating a first data set and scanning the second facial surface of the workpiece, generating a second data set. The first and second data sets each include spatial points corresponding to locations of the reflective boundary targets. The method further includes aligning the spatial points of the first data set with the spatial points of the second data set.

Abstract: The disclosure relates to a tool for inserting or removing a wire thread insert. The spindle body inserted in the tool has a radial recess, through which an engaging end of the installation blade engages a wire thread insert. The radial recess has a curvilinear circumferential contour or at least one relief notch, which serve for mechanical tension relief in the spindle body.

Abstract: In an example of a 3D printing method, build material particles are applied to form a layer. Each build material particle includes a metal core and a metal oxide outer shell. The layer is patterned by selectively applying a reactive chemical on at least a portion of the layer to initiate a redox reaction with the metal oxide outer shells of the build material particles in contact with the reactive chemical, which reduces the metal oxide outer shells of the build material particles in contact with the reactive chemical and exposes the metal cores of the build material particles in contact with the reactive chemical. The patterned layer is exposed to rapid thermal processing to sinter the exposed metal cores to form a part layer. Any intact build material particles remain unsintered.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

Abstract: A sensor array can differentiate acceptable tensile and flexural stresses in a beam from stress patterns that indicate a fracture in the beam. At least three strain gauges, with additional pairs of strain gauges added for redundancy, can be used. The single, central strain gauge is adhered to the beam directly over, and with the sensing elements parallel to the neutral axis of the beam. The pairs of strain gauges are adhered to the beam parallel to the sensing elements of the single strain gauge on opposite sides of and equidistant from the neutral axis. The single strain gauge senses the tensile stress in the beam. The pairs of gauges sense the bending strain in the beam. A non-zero value in the sum of the strains measured by each of the pair of strain gauges indicates a potential structural health issue with the beam.

Abstract: Provided is a method for manufacturing a solid oxide and a device therefor, capable of manufacturing a solid oxide used as an optical material without introducing damaged layers caused by machining, which does not use any polishing agent or abrasive grains including rare earth elements, or does not use any solution, such as hydrogen fluoride, for which handling is difficult and which imposes a heavy environmental burden.

Abstract: A coil component includes a body in which a coil part is embedded. The coil part includes a support member having trenches, pattern walls extending from the trenches in the support member, and coil patterns extending between the pattern walls on the support member.

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

Abstract: An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.

Abstract: Methods to remove metal oxides from substrate surfaces are described. Some embodiments of the disclosure utilize an aqueous alkaline solution to remove metal oxides from substrate surfaces using a wet method. Some embodiments of the disclosure are performed at atmospheric pressure and lower temperatures. Methods of forming self-aligned vias are also described.

Abstract: Provided is a rotor system including: a rotating shaft structure including a shaft and a thrust disc formed in a radial direction of the shaft; at least one journal air bearing including a journal bearing support which is made of a rigid body to support a load applied to the shaft by air, a journal spring which encloses an outer surrounding surface of the journal bearing support to provide a elastic support force to the journal bearing support, and a journal damper which encloses the outer surrounding surface of the journal bearing support to dissipate energy from vibration applied to the journal bearing support; and at least one thrust air bearing including a thrust bearing support which is made of a rigid body to support a load applied to the thrust disc by air, a thrust spring which is positioned on one surface of the thrust bearing support to provide a elastic support force to the thrust bearing support, and a thrust damper which is positioned on one surface of the thrust bearing support to dissipate ener

Abstract: Described are slurry compositions useful in chemical-mechanical processing of a nickel layer of a substrate, wherein the slurry compositions contain abrasive particles that include silica particles that are cationically charged at a low pH.

Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.

Abstract: Apparatus and methods are disclosed to provide arrays of substantially oxide-free structures, such as titanium nanotubes or microwells. In one aspect, a hot wire chemical vapor deposition (HWCVD) chamber includes a metal chamber liner manufactured from one or more of aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), zirconium (Zr), strontium (Sr), cerium (Ce), barium (Ba), beryllium (Be), lanthanum (La), thorium (Th), and alloys thereof. In one aspect, a method includes positioning a substrate having an array of titanium oxide structures with an oxide layer on surfaces thereof in the HWCVD chamber having the metal chamber liner, exposing the titanium oxide structures with the oxide layer on surfaces thereof to hydrogen (H) radicals, and removing the oxide layer to form well-ordered titanium structures.

Abstract: Indium electroplating compositions containing amine compounds in trace amounts to electroplate substantially defect-free uniform indium which has a smooth surface morphology. The indium electroplating compositions can be used to electroplate indium metal on metal layers of various substrates such as semiconductor wafers and as thermal interface materials.

Abstract: Methods and devices for etching patterns on interior surfaces of hollow objects are described. The method may include preparation of the interior surface of the object, such as pre-cleaning, and coating the interior surface of the object. A pattern may then be generated on the interior surface of the object by any of mechanical or manual scribing and peeling, laser ablation, or photoresist coating and laser exposure, development and hardening. The pattern is then etched using chemical etchants, and finished to remove remaining coating, provide surface passivation and/or protectant application. Mechanical and laser devices which may facilitate pattern generation are also described.

Abstract: A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Abstract: A component carrier includes a base structure and an electrically conductive wiring structure on the base structure. The wiring structure has a nonrectangular cross-sectional shape configured so that an adhesion promoting constriction is formed by at least one of the group consisting of the wiring structure and a transition between the base structure and the wiring structure.

Abstract: A CMP slurry including a carrier, a particulate material within the carrier including an oxide, carbide, nitride, boride, diamond or any combination thereof, an oxidizer including at least one material selected from the group of peroxides, persulfates, permanganates, periodates, perchlorates, hypocholorites, iodates, peroxymonosulfates, cerric ammonium nitrate, periodic acid, ferricyanides, or any combination thereof, and a material removal rate index (MRR) of at least 500 nm/hr and an average roughness index (Ra) of not greater than 5 Angstroms according to the Standardized Polishing test.

Abstract: A tensioning device for attaching to the anterior capsule of an eye, and accommodative intraocular lens systems employing the device. The tensioning device includes a biocompatible, elastically reconfigurable ring for restoring at least a portion of the anterior capsule centripetal forces lost by capsulorhexis. The tensioning device also includes a plurality of penetrators configured for attaching the ring to the anterior capsule. The plurality of penetrators is biocompatible with the eye and partially embedded in a part of the ring configured for facing the anterior capsule.

Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) silica particles, (b) a polymer comprising sulfonic acid monomeric units, (c) optionally, a buffering agent, and (d) water, wherein the polishing composition has a pH of about 2 to about 5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate comprises silicon carbide and silicon nitride.

Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.

Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer arranged over the semiconductor die and the protection layer and partially covering the conductive feature. The conductive feature is arranged accessibly from the protection layer and the dielectric layer. The chip package further includes a conductive layer penetrating through the dielectric layer and electrically connected to the conductive feature of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion accessibly exposed from the dielectric layer, and the second portion has a surface roughness greater than that of the first portion.

Abstract: A deposition apparatus includes a deposition chamber, a deposition source, and a deposition mask. The deposition source is disposed in the deposition chamber and provides a deposition material to a deposition substrate. The deposition mask includes a body portion and a carbon layer. The carbon layer is disposed on a first surface making contact with the deposition mask and includes at least one of carbon nanotube or graphene.

Abstract: According to one embodiment, a pressure sensor includes a base, and a first sensor unit. The first sensor unit includes a first transducer thin film, a first strain sensing device and a second strain sensing device. The first strain sensing device includes a first magnetic layer, a second magnetic layer, and a first intermediate layer provided between the first and the second magnetic layers. The second strain sensing device is provided apart from the first strain sensing device on the first membrane surface and provided at a location different from a location of the barycenter, the second strain sensing device including a third magnetic layer, a fourth magnetic layer, and a second intermediate layer provided between the third and the fourth magnetic layers, the first and the second intermediate layers being nonmagnetic. The first and the second strain sensing devices, and the barycenter are in a straight line.

Abstract: A method of forming low-energy x-ray absorbers. Sensors may be formed on a semiconductor, e.g., silicon, wafer. A seed metal layer, e.g., gold, is deposited on the wafer and patterned into stem pads for electroplating. Stems, e.g., gold, are electroplated from the stem seed pads through a stem mask. An absorber layer, e.g., gold, is deposited on the wafer, preferably e-beam evaporated. After patterning the absorbers, absorber and stem mask material is removed, e.g., in a solvent bath and critical point drying.

Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.

Abstract: The present invention provides a deposition mask for forming a thin-pattern by depositing a deposition material on a substrate, the deposition mask includes: a thin plate-shaped magnetic metal member 1 in which a through-hole 4 having shape and dimensions greater than those of the thin-film pattern is provided at a position corresponding to the thin-film pattern; and a resin film 2 which is provided in close contact with one surface of the magnetic metal member 1 and in which an opening pattern 5 having shape and dimensions identical to those of the thin-film pattern is formed at a position corresponding to the thin-film pattern in the through-hole 4, the resin film 2 being permeable to visible light. The opening pattern 5 is provided within an opening pattern formation region 7 surrounded by a deposition shadow region 6 defined by the thickness of the magnetic metal member 1 and the maximum angle of incidence of the deposition material to the film surface in the through-hole 4.

Abstract: Methods and systems for optical assemblies are disclosed. Optical assemblies can comprise optical elements that may not require active alignment and allow for reduced performance variations. To allow for passive assembly with a machine like a bonder tool, assembly components can have bonding pads and/or fiducial markers that are fabricated using laser micromachining techniques.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.

Abstract: A lighted assembly includes a perforated member having a plurality of relatively small openings therethrough. The openings are arranged to provide areas forming letters, designs, or the like. A light source may be positioned adjacent the perforated member whereby light from the light source travels through the openings to form illuminated letters, designs or the like. The perforations may be filled with a light-transmitting polymer material. The light source may comprise an LED and a light guide that distributes light along a lower side of the perforated member. The light source may be positioned in a waterproof housing that is sealed to the perforated member.

Abstract: A microfluidic device (1000-1005), comprising: a semiconductor body (2) having a first side (2a) and a second side (2b) opposite to one another, and housing, at the first side, a plurality of wells (4), having a first depth; an inlet region (30) forming an entrance point for a fluid to be supplied to the wells; a main channel (6a) fluidically connected to the inlet region, and having a second depth; and a plurality of secondary channels (6b) fluidically connecting the main channel to a respective well, and having a third depth. The first depth is higher than the second depth, which in turn is higher than the third depth.

Abstract: A manufacturing method of a thin film transistor comprises: sequentially forming a pattern of gate, a gate insulation layer film, an active layer film and an ohmic contact layer film, a first etching resist module within a channel region to be formed, and a source and drain metallic layer film on a substrate; forming a pattern comprising the source and drain by wet etching process by shielding the active layer film and the ohmic contact layer film positioned within the channel region to be formed, by use of the first etching resist module; and forming a pattern comprising the ohmic contact layer and the active layer by dry etching process. A thin film transistor, an array substrate comprising the thin film transistor and a display device comprising the array substrate are also disclosed.

Abstract: The invention relates to a method for processing a structured surface of an embossing tool, in which the entire surface is provided with a first metallic coating and said surface having, in selected regions, at least one additional metallic coating that has a differing degree of lustre. To improve the optical properties of the material boards produced using the embossing tools, particularly if reproducing a wood texture, the invention suggests that additional differing degrees of lustre should be produced in multiple selected regions on the first coating, and be produced by a combination of metallic coatings and mechanical or chemical after-treatments. Therefore, for example, a wood pore with a defined structure can be substantially better reproduced, and the optical and haptic properties of the wood composite board produced using the press plates can thus be improved.

Abstract: A semiconductor device includes an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.

Abstract: A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.

Abstract: A packaging apparatus is provided for packaging one or more deposition masks. The apparatus comprises a base comprising a first surface and a first recess; a cover disposed over the base and comprising a second surface facing the first surface and a second recess; a first film placed over the first surface to cover the first recess; a second film placed over the second surface to cover the second recess; and a plurality of insertion sheets interposed between the first film and the second film. The one or more deposition masks comprise a first mask interposed between first and second insertion sheets, the first mask having a width defining a width direction. Each of the first and second insertion sheets comprises a plurality of openings, each extending along the width direction when viewed in a viewing direction perpendicular to the first surface.

Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.

Abstract: A method is provided for cleaning at least a part of a water-steam circuit of a power plant. The method includes introducing a cleaning solution into the part requiring to be cleaned and subsequently draining off the cleaning solution. While the cleaning solution is being drained off or immediately thereafter, steam for flushing is injected via a steam injection device into the part requiring to be cleaned at at least one high point of the part requiring to be cleaned and low-point drains are opened or remain open in the part requiring to be cleaned and steam continues to be injected until steam emerges from the low-point drains and those low-point drains from which steam emerges are closed, and steam continues to be injected until steam has emerged from all low-point drains, upon which the steam injection device is closed and all low-point drains are reopened.

Abstract: A process for chemical mechanical polishing of a substrate having an exposed silicon dioxide feature is provided comprising: providing a chemical mechanical polishing composition, containing, as initial components: water, a colloidal silica abrasive and a zirconyl compound; wherein a pH of the chemical mechanical polishing composition is ?6; providing a chemical mechanical polishing pad with a polishing surface; dispensing the chemical mechanical polishing composition onto the polishing surface of the chemical mechanical polishing pad in proximity to an interface between the chemical mechanical polishing pad and the substrate; and, creating dynamic contact at the interface between the chemical mechanical polishing pad and the substrate; wherein the substrate is polished.