Substrate Contains Elemental Metal, Alloy Thereof, Or Metal Compound Patents (Class 216/100)
  • Patent number: 10808757
    Abstract: Provided is a rotor system including: a rotating shaft structure including a shaft and a thrust disc formed in a radial direction of the shaft; at least one journal air bearing including a journal bearing support which is made of a rigid body to support a load applied to the shaft by air, a journal spring which encloses an outer surrounding surface of the journal bearing support to provide a elastic support force to the journal bearing support, and a journal damper which encloses the outer surrounding surface of the journal bearing support to dissipate energy from vibration applied to the journal bearing support; and at least one thrust air bearing including a thrust bearing support which is made of a rigid body to support a load applied to the thrust disc by air, a thrust spring which is positioned on one surface of the thrust bearing support to provide a elastic support force to the thrust bearing support, and a thrust damper which is positioned on one surface of the thrust bearing support to dissipate ener
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 20, 2020
    Assignee: INDUSTRY-UNIVERSITY COOPERATION-FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventor: Keun Ryu
  • Patent number: 10792785
    Abstract: Described are slurry compositions useful in chemical-mechanical processing of a nickel layer of a substrate, wherein the slurry compositions contain abrasive particles that include silica particles that are cationically charged at a low pH.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 6, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventor: Ke Zhang
  • Patent number: 10522491
    Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Shin-Puu Jeng, Chih-Hang Tung, Cheng-Chang Wei
  • Patent number: 10513778
    Abstract: Apparatus and methods are disclosed to provide arrays of substantially oxide-free structures, such as titanium nanotubes or microwells. In one aspect, a hot wire chemical vapor deposition (HWCVD) chamber includes a metal chamber liner manufactured from one or more of aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), zirconium (Zr), strontium (Sr), cerium (Ce), barium (Ba), beryllium (Be), lanthanum (La), thorium (Th), and alloys thereof. In one aspect, a method includes positioning a substrate having an array of titanium oxide structures with an oxide layer on surfaces thereof in the HWCVD chamber having the metal chamber liner, exposing the titanium oxide structures with the oxide layer on surfaces thereof to hydrogen (H) radicals, and removing the oxide layer to form well-ordered titanium structures.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 24, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Sukti Chatterjee
  • Patent number: 10428436
    Abstract: Indium electroplating compositions containing amine compounds in trace amounts to electroplate substantially defect-free uniform indium which has a smooth surface morphology. The indium electroplating compositions can be used to electroplate indium metal on metal layers of various substrates such as semiconductor wafers and as thermal interface materials.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 1, 2019
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Yi Qin, Kristen Flajslik, Mark Lefebvre
  • Patent number: 10399240
    Abstract: Methods and devices for etching patterns on interior surfaces of hollow objects are described. The method may include preparation of the interior surface of the object, such as pre-cleaning, and coating the interior surface of the object. A pattern may then be generated on the interior surface of the object by any of mechanical or manual scribing and peeling, laser ablation, or photoresist coating and laser exposure, development and hardening. The pattern is then etched using chemical etchants, and finished to remove remaining coating, provide surface passivation and/or protectant application. Mechanical and laser devices which may facilitate pattern generation are also described.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 3, 2019
    Assignee: Tech Met, Inc.
    Inventors: Michael Vidra, James Ringer, Robert Vaccaro, Mark Megela, Edward Palanko
  • Patent number: 10396012
    Abstract: A method providing a high aspect ratio through substrate via in a substrate is described. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A first metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process converts a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer is deposited to fill the through substrate via. A selective etch creates a recess in the first metal layer in the through substrate via. A second barrier layer is deposited over the recess. A second metal layer is patterned over the second barrier layer filling the recess and creating a contact. Another aspect of the invention is a device produced by the method.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10361120
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10349521
    Abstract: A component carrier includes a base structure and an electrically conductive wiring structure on the base structure. The wiring structure has a nonrectangular cross-sectional shape configured so that an adhesion promoting constriction is formed by at least one of the group consisting of the wiring structure and a transition between the base structure and the wiring structure.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: July 9, 2019
    Assignee: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Hannes Voraberger
  • Patent number: 10327889
    Abstract: A tensioning device for attaching to the anterior capsule of an eye, and accommodative intraocular lens systems employing the device. The tensioning device includes a biocompatible, elastically reconfigurable ring for restoring at least a portion of the anterior capsule centripetal forces lost by capsulorhexis. The tensioning device also includes a plurality of penetrators configured for attaching the ring to the anterior capsule. The plurality of penetrators is biocompatible with the eye and partially embedded in a part of the ring configured for facing the anterior capsule.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 25, 2019
    Inventor: Richard F. Honigsbaum
  • Patent number: 10329455
    Abstract: A CMP slurry including a carrier, a particulate material within the carrier including an oxide, carbide, nitride, boride, diamond or any combination thereof, an oxidizer including at least one material selected from the group of peroxides, persulfates, permanganates, periodates, perchlorates, hypocholorites, iodates, peroxymonosulfates, cerric ammonium nitrate, periodic acid, ferricyanides, or any combination thereof, and a material removal rate index (MRR) of at least 500 nm/hr and an average roughness index (Ra) of not greater than 5 Angstroms according to the Standardized Polishing test.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 25, 2019
    Assignee: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Ian T. Sines, Angela Kwapong, Carlijn L. Mulder, Douglas E. Ward, Vianney Le Roux
  • Patent number: 10294399
    Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) silica particles, (b) a polymer comprising sulfonic acid monomeric units, (c) optionally, a buffering agent, and (d) water, wherein the polishing composition has a pH of about 2 to about 5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate comprises silicon carbide and silicon nitride.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Cabot Microelectronics Corporation
    Inventors: Roman Ivanov, Fernando Hung Low, Cheng-Yuan Ko, Glenn Whitener
  • Patent number: 10233547
    Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: March 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Schmiege, Nitin K. Ingle, Srinivas D. Nemani, Jeffrey W. Anthis, Xikun Wang, Jie Liu, David Benjaminson
  • Patent number: 10224256
    Abstract: A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 5, 2019
    Assignee: J-DEVICES CORPORATION
    Inventors: Hirokazu Machida, Kazuhiko Kitano
  • Patent number: 10199572
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yi Jiang, Daxiang Wang, Wei Shao, Juan Boon Tan
  • Patent number: 10161030
    Abstract: A deposition apparatus includes a deposition chamber, a deposition source, and a deposition mask. The deposition source is disposed in the deposition chamber and provides a deposition material to a deposition substrate. The deposition mask includes a body portion and a carbon layer. The carbon layer is disposed on a first surface making contact with the deposition mask and includes at least one of carbon nanotube or graphene.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 25, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jeongwon Han
  • Patent number: 10163801
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer arranged over the semiconductor die and the protection layer and partially covering the conductive feature. The conductive feature is arranged accessibly from the protection layer and the dielectric layer. The chip package further includes a conductive layer penetrating through the dielectric layer and electrically connected to the conductive feature of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion accessibly exposed from the dielectric layer, and the second portion has a surface roughness greater than that of the first portion.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo
  • Patent number: 10082430
    Abstract: According to one embodiment, a pressure sensor includes a base, and a first sensor unit. The first sensor unit includes a first transducer thin film, a first strain sensing device and a second strain sensing device. The first strain sensing device includes a first magnetic layer, a second magnetic layer, and a first intermediate layer provided between the first and the second magnetic layers. The second strain sensing device is provided apart from the first strain sensing device on the first membrane surface and provided at a location different from a location of the barycenter, the second strain sensing device including a third magnetic layer, a fourth magnetic layer, and a second intermediate layer provided between the third and the fourth magnetic layers, the first and the second intermediate layers being nonmagnetic. The first and the second strain sensing devices, and the barycenter are in a straight line.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Fukuzawa, Akihiko Enamito, Osamu Nishimura, Michiko Hara, Hiromi Yuasa, Yoshihiko Fuji, Masayuki Kii, Eizo Fujisawa
  • Patent number: 10074764
    Abstract: A method of forming low-energy x-ray absorbers. Sensors may be formed on a semiconductor, e.g., silicon, wafer. A seed metal layer, e.g., gold, is deposited on the wafer and patterned into stem pads for electroplating. Stems, e.g., gold, are electroplated from the stem seed pads through a stem mask. An absorber layer, e.g., gold, is deposited on the wafer, preferably e-beam evaporated. After patterning the absorbers, absorber and stem mask material is removed, e.g., in a solvent bath and critical point drying.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 11, 2018
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Thomas R. Stevenson, Manuel A. Balvin, Kevin L. Denis, John E. Sadleir, Peter C. Nagler
  • Patent number: 10035162
    Abstract: The present invention provides a deposition mask for forming a thin-pattern by depositing a deposition material on a substrate, the deposition mask includes: a thin plate-shaped magnetic metal member 1 in which a through-hole 4 having shape and dimensions greater than those of the thin-film pattern is provided at a position corresponding to the thin-film pattern; and a resin film 2 which is provided in close contact with one surface of the magnetic metal member 1 and in which an opening pattern 5 having shape and dimensions identical to those of the thin-film pattern is formed at a position corresponding to the thin-film pattern in the through-hole 4, the resin film 2 being permeable to visible light. The opening pattern 5 is provided within an opening pattern formation region 7 surrounded by a deposition shadow region 6 defined by the thickness of the magnetic metal member 1 and the maximum angle of incidence of the deposition material to the film surface in the through-hole 4.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: July 31, 2018
    Assignee: V TECHNOLOGY CO., LTD.
    Inventor: Michinobu Mizumura
  • Patent number: 10037973
    Abstract: A method for manufacturing a semiconductor package structure is provided. A semiconductor substrate comprising a conductive pad is provided, wherein the conductive pad is coupled with a circuitry of the semiconductor substrate. A patterned passivation layer exposing a portion of the conductive pad is formed. An uneven surface of the conductive pad is formed. A photoresist is formed on the semiconductor substrate. The photoresist is exposed under a light beam, wherein the light beam is scattered by the uneven surface. The photoresist is developed to form an opening in the photoresist so as to expose the conductive pad and form a plurality of cavities in the remaining photoresist. A conductive material is formed in the opening and the plurality of cavities.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: July 31, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
  • Patent number: 10014657
    Abstract: Methods and systems for optical assemblies are disclosed. Optical assemblies can comprise optical elements that may not require active alignment and allow for reduced performance variations. To allow for passive assembly with a machine like a bonder tool, assembly components can have bonding pads and/or fiducial markers that are fabricated using laser micromachining techniques.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: July 3, 2018
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Gregory David Miller, Gennady Imeshev, James Thomas Triplett
  • Patent number: 9972506
    Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 15, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Donald C. Abbott
  • Patent number: 9896770
    Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 20, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Schmiege, Nitin K. Ingle, Srinivas D. Nemani, Jeffrey W. Anthis, Xikun Wang, Jie Liu, David Benjaminson
  • Patent number: 9812042
    Abstract: A lighted assembly includes a perforated member having a plurality of relatively small openings therethrough. The openings are arranged to provide areas forming letters, designs, or the like. A light source may be positioned adjacent the perforated member whereby light from the light source travels through the openings to form illuminated letters, designs or the like. The perforations may be filled with a light-transmitting polymer material. The light source may comprise an LED and a light guide that distributes light along a lower side of the perforated member. The light source may be positioned in a waterproof housing that is sealed to the perforated member.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 7, 2017
    Assignees: Innotec Corp., Vestatec (U.K.) Limited
    Inventors: Jason R. Mulder, David L. Hiemstra, Antony John Skirrow
  • Patent number: 9777317
    Abstract: A microfluidic device (1000-1005), comprising: a semiconductor body (2) having a first side (2a) and a second side (2b) opposite to one another, and housing, at the first side, a plurality of wells (4), having a first depth; an inlet region (30) forming an entrance point for a fluid to be supplied to the wells; a main channel (6a) fluidically connected to the inlet region, and having a second depth; and a plurality of secondary channels (6b) fluidically connecting the main channel to a respective well, and having a third depth. The first depth is higher than the second depth, which in turn is higher than the third depth.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: October 3, 2017
    Assignees: STMicroelectronics S.r.l., bioMérieux S.A.
    Inventors: Giuseppe Emanuele Spoto, Luigi Giuseppe Occhipinti, Cristian Dall'Oglio, Crocifisso Marco Antonio Renna, Laurent Drazek
  • Patent number: 9561524
    Abstract: The invention relates to a method for processing a structured surface of an embossing tool, in which the entire surface is provided with a first metallic coating and said surface having, in selected regions, at least one additional metallic coating that has a differing degree of lustre. To improve the optical properties of the material boards produced using the embossing tools, particularly if reproducing a wood texture, the invention suggests that additional differing degrees of lustre should be produced in multiple selected regions on the first coating, and be produced by a combination of metallic coatings and mechanical or chemical after-treatments. Therefore, for example, a wood pore with a defined structure can be substantially better reproduced, and the optical and haptic properties of the wood composite board produced using the press plates can thus be improved.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: February 7, 2017
    Assignee: Hueck Rheinische GmbH
    Inventors: Martin Marxen, Wolfgang Stoffel
  • Patent number: 9564460
    Abstract: A manufacturing method of a thin film transistor comprises: sequentially forming a pattern of gate, a gate insulation layer film, an active layer film and an ohmic contact layer film, a first etching resist module within a channel region to be formed, and a source and drain metallic layer film on a substrate; forming a pattern comprising the source and drain by wet etching process by shielding the active layer film and the ohmic contact layer film positioned within the channel region to be formed, by use of the first etching resist module; and forming a pattern comprising the ohmic contact layer and the active layer by dry etching process. A thin film transistor, an array substrate comprising the thin film transistor and a display device comprising the array substrate are also disclosed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: February 7, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Shengnan Xiong, Yunyou Zheng, Wei Li, Yicun Zhang
  • Patent number: 9559063
    Abstract: A semiconductor device includes an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: January 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Watanabe, Junya Ishii, Hirofumi Saitou, Hiroyasu Kitajima, Tatsuki Kojima, Yoshitsugu Kawashima
  • Patent number: 9536696
    Abstract: A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 3, 2017
    Assignee: Elwha LLC
    Inventors: Roderick A. Hyde, Jordin T. Kare, Tony S. Pan, Lowell L. Wood, Jr.
  • Patent number: 9522764
    Abstract: A packaging apparatus is provided for packaging one or more deposition masks. The apparatus comprises a base comprising a first surface and a first recess; a cover disposed over the base and comprising a second surface facing the first surface and a second recess; a first film placed over the first surface to cover the first recess; a second film placed over the second surface to cover the second recess; and a plurality of insertion sheets interposed between the first film and the second film. The one or more deposition masks comprise a first mask interposed between first and second insertion sheets, the first mask having a width defining a width direction. Each of the first and second insertion sheets comprises a plurality of openings, each extending along the width direction when viewed in a viewing direction perpendicular to the first surface.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 20, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Daewon Baek
  • Patent number: 9406629
    Abstract: A semiconductor package structure includes a first semiconductor substrate including a conductive pad; and a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor substrate. The conductive pad is coupled with a circuitry of the first semiconductor substrate. The conductive pillar extends along a longitudinal axis and toward the second semiconductor substrate. The conductive pillar includes a sidewall with a rough surface notching toward the longitudinal axis.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hua-Wei Tseng, Shang-Yun Tu, Hsu-Hsien Chen, Hao-Juin Liu, Chen-Shien Chen, Ming Hung Tseng, Chita Chuang
  • Patent number: 9302300
    Abstract: A method is provided for cleaning at least a part of a water-steam circuit of a power plant. The method includes introducing a cleaning solution into the part requiring to be cleaned and subsequently draining off the cleaning solution. While the cleaning solution is being drained off or immediately thereafter, steam for flushing is injected via a steam injection device into the part requiring to be cleaned at at least one high point of the part requiring to be cleaned and low-point drains are opened or remain open in the part requiring to be cleaned and steam continues to be injected until steam emerges from the low-point drains and those low-point drains from which steam emerges are closed, and steam continues to be injected until steam has emerged from all low-point drains, upon which the steam injection device is closed and all low-point drains are reopened.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: April 5, 2016
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Klaus-Dieter Kuhnke
  • Patent number: 9293339
    Abstract: A process for chemical mechanical polishing of a substrate having an exposed silicon dioxide feature is provided comprising: providing a chemical mechanical polishing composition, containing, as initial components: water, a colloidal silica abrasive and a zirconyl compound; wherein a pH of the chemical mechanical polishing composition is ?6; providing a chemical mechanical polishing pad with a polishing surface; dispensing the chemical mechanical polishing composition onto the polishing surface of the chemical mechanical polishing pad in proximity to an interface between the chemical mechanical polishing pad and the substrate; and, creating dynamic contact at the interface between the chemical mechanical polishing pad and the substrate; wherein the substrate is polished.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: March 22, 2016
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, David Mosley
  • Patent number: 9257387
    Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 9, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Isamu Nishimura, Michihiko Mifuji, Kazumasa Nishio
  • Patent number: 9039916
    Abstract: A method for removing copper-oxide from copper powder, the method comprising: providing a copper powder defined by each particle having a copper core and a copper-oxide layer surrounding the copper core; disposing the particles in an etching solution in a container, wherein the etching solution removes the copper-oxide layer from each particle; decanting the etching solution and by-products; washing the particles; disposing the washed particles in an organic solvent; coating each copper core with an organic material from the organic solvent; dispersing the particles in the organic solvent; and providing the copper powder as dispersed copper cores that are absent a copper-oxide layer and have an organic coating, wherein the steps of dispersing in the etching solution, decanting, washing, disposing in the organic solvent, coating, and dispersing are performed in situ with the plurality of particles disposed in liquid, absent any exposure of the copper cores to air.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 26, 2015
    Assignee: SDCmaterials, Inc.
    Inventor: Stephen Edward Lehman, Jr.
  • Publication number: 20150136737
    Abstract: Methods of growing a multilayer graphene film (10) include flowing a weak oxidizing vapor (OV) and a gaseous carbon source (CS) over a surface (SGC) of a carbonizing catalyst (GC) in a CVD reaction chamber (2). Carbon atoms (C) deposit on the carbonizing catalyst surface to form sheets of single-layer graphene (12) upon cooling. The method generates a substantially uniform stacking of graphene layers to form the multilayer graphene film. The multilayer graphene film is substantially uniform and has a relatively large scale as compared to graphene films formed by prior-art methods.
    Type: Application
    Filed: May 17, 2013
    Publication date: May 21, 2015
    Inventors: Kian Ping Loh, Kai Zhang, Antonio Helio Castro Neto
  • Publication number: 20150140314
    Abstract: Chemically and mechanically protective oxide film was formed on Mg alloys using micro-arc oxidation (MAO) methods. Further modification of the obtained MAO surfaces was made in various aspects and the processes thereof were described. Firstly, the protection is enhanced by forming super-hydrophobic surfaces, with water contact angle higher than 140°, attributed to hierarchical nano-micro structures. Secondly, the electrical property of the MAO surfaces is modified. A film with sheet resistance as low as 0.05 ?/sq is achieved by electro-less Ni deposition on MAO surfaces. Thirdly, black colors are achieved by the sol-gel process on MAO samples.
    Type: Application
    Filed: November 18, 2014
    Publication date: May 21, 2015
    Inventors: Hong TAO, King Ho SO, Siyue LI, Xuezhu ZHANG, Kwok Cheong LAI
  • Patent number: 9023217
    Abstract: A patterned transparent conductor including a conductive layer coated on a substrate is described. More specifically, the transparent conductor can be patterned by screen-printing an acidic etchant formulation on the conductive layer. A screen-printable etchant formulation is also disclosed.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 5, 2015
    Assignee: Cambrios Technologies Corporation
    Inventors: Adrian Winoto, Jeffrey Wolk
  • Patent number: 9017569
    Abstract: A method for preparing a copper alloy given a certain special surface shape yields tremendous bonding strength through compatibility with an epoxy resin adhesive. With a composite part in which this technology is utilized to integrate a copper alloy member as a cover material with a CFRP, it is possible to take advantage of the characteristics of both the copper alloy and the FRP due to the tremendous bonding strength. In a step in which an FRP prepreg is put into a mold and heated and cured, usually the mold is first coated with a release agent to facilitate release from the mold, but with high-technology CFRP, bleeding of the release agent often diminishes the properties. A copper alloy sheet 21 is used as a cover material, and a CFRP 22 is cured.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 28, 2015
    Assignee: Taisei Plas Co., Ltd.
    Inventors: Masanori Naritomi, Naoki Andoh
  • Publication number: 20150107473
    Abstract: Banks, as well as a plurality of recess-shaped cells defined by the banks, are provided in an image section formed in a gravure printing plate. A projecting portion is provided in each of the cells so as to protrude from a part of the base surface of that cell. The projecting portions are in positions distanced from the banks. Like the banks, the projecting portions can serve as starting points for the transfer of a printing paste. Accordingly, printing paste that would, in the case where the projecting portions are not provided, remain in the bases of the cells is transferred to the printing target material via the projecting portions, which increases the transfer efficiency. As a result, a paste film that is smooth and has the required thickness can be printed.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 23, 2015
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Kazuhiro YOSHIDA
  • Patent number: 9012329
    Abstract: A nanogap of controlled width in-between noble metals is produced using sidewall techniques and chemical-mechanical-polishing. Electrical connections are provided to enable current measurements across the nanogap for analytical purposes. The nanogap in-between noble metals may also be formed inside a Damascene trench. The nanogap in-between noble metals may also be inserted into a crossed slit nanopore framework. A noble metal layer on the side of the nanogap may have sub-layers serving the purpose of multiple simultaneous electrical measurements.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Yann Astier, Jingwei Bai, Michael F. Lofaro, Satyavolu S. Papa Rao, Joshua T. Smith, Chao Wang
  • Patent number: 8992787
    Abstract: Anode foils suitable for use in electrolytic capacitors, including those having multiple anode configurations, have improved strength, reduced brittleness, and increased capacitance compared to conventional anode foils for electrolytic capacitors. Exemplary methods of manufacturing an anode foil suitable for use in an electrolytic capacitor include disposing a resist material in a predetermined pattern on an exposed surface of an anode foil substrate such that a first portion of the exposed surface of the anode foil substrate is covered by the resist material, and a second portion of the exposed surface remains uncovered; polymerizing the resist material; exposing at least the second portion of the exposed surface to one or more etchants so as to form a plurality of tunnels; stripping the polymerized resist material; and widening at least a portion of the plurality of tunnels. The resist material may be deposited, for example, by ink-jet printing, stamping or screen printing.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 31, 2015
    Assignee: Pacesetter, Inc.
    Inventors: David R. Bowen, Ralph Jason Hemphill, Xiaofei Jiang, Corina Geiculescu, Tearl Stocker
  • Patent number: 8974681
    Abstract: A method for balancing a rotor, notably of a turbomachine, includes a step of determining an unbalancing mass, and a step of balancing by chemical machining of the rotor. The chemical machining includes arranging a bath containing a chemical machining agent so that the bath has a capacity of heterogeneous material removal as a function of the depth in the bath, an amount of material removal at a first depth in the bath is greater than an amount of material removal at a second depth in the bath; immersing the rotor in the bath; and orienting the rotor in the bath taking account of the capacity of heterogeneous material removal so that the quantity of material removed from the rotor in a zone of the unbalancing mass is sufficient to balance the rotor.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 10, 2015
    Assignee: SNECMA
    Inventors: Gabriela Rodriguez Elizondo, Stephane Vitrac, Marcial Suarez Cabrera, Patrick Momier
  • Publication number: 20150048053
    Abstract: A layer of a metal selected from titanium, niobium, tungsten, molybdenum, ruthenium, rhodium, arsenic, aluminum and gallium, an oxide of the metal, a nitride of the metal, silicon nitride, hafnium nitride, tantalum nitride, or an alloy of these metals, the layer being provided on an underlying base material selected from glass, silicon, copper and nickel, is selectively etched with an alkaline etching solution containing a predefined complexing agent.
    Type: Application
    Filed: September 3, 2012
    Publication date: February 19, 2015
    Applicant: JCU CORPORATION
    Inventors: Christopher Cordonier, Mitsuhiro Nabeshima, Shingo Kumagai, Naoki Takahashi
  • Patent number: 8951425
    Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki, Onoriu Puscasu, Christophe Maitre
  • Patent number: 8945406
    Abstract: A method for manufacturing a symbol on an exterior of an electronic device is provided. The method includes preparing a support layer, preparing a nanograting layer on the support layer, the nanograting layer including a first nanograting area corresponding to a preset symbol and a second nanograting area corresponding to an area other than the preset symbol, wherein each of the first nanograting area and the second nanograting area includes three-dimensional (3D) nanostructures and a pitch between the 3D nanostructures arranged in the first nanograting area is different from a pitch between the 3D nanostructures arranged in the second nanograting area.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-eun Chung, Il-yong Jung
  • Patent number: 8945415
    Abstract: A method is described for etching ceramic phosphor converters. The method includes contacting a surface of the converter with a solution of phosphor acid for a time sufficient to etch the converter. The method is applicable to ceramic phosphor converters comprising a phosphor having a general formula MxAlyOz:RE wherein M is a metal and RE is a rare earth element.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 3, 2015
    Assignee: OSRAM SYLVANIA Inc.
    Inventor: Alan Piquette
  • Patent number: 8932476
    Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 13, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kunstmann, Stefan Willkofer, Anja Gissibl, Johann Strasser, Matthias Mueller, Eva-Maria Hess
  • Patent number: 8926853
    Abstract: Aspects of the invention are directed to a method of forming graphene structures. Initially, a cluster of particles is received. The cluster of particles comprises a plurality of particles with each particle in the plurality of particles contacting one or more other particles in the plurality of particles. Subsequently, one or more layers are deposited on the cluster of particles with the one or more layers comprising graphene. The plurality of particles are then etched away without substantially etching the deposited one or more layers. Lastly, the remaining one or more layers are dried. The resultant graphene structures are particularly resistant to the negative effects of aggregation and compaction.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 6, 2015
    Inventors: Xin Zhao, Yu-Ming Lin