Abstract: The wall of each supply path formed in a silicon substrate has such a shape that a plurality of regions distinguished from each other due to different inclinations to a first surface of the silicon substrate are connected to each other between the first surface and a second surface of the silicon substrate and the width of the supply path is maintained or expands from the first surface to second surface of the silicon substrate. An internal opening is formed by one of the regions that is most steeply inclined to the first surface of the silicon substrate. A region reducing the squeezing of an adhesive into the internal opening is placed between the internal opening and the second surface of the silicon substrate.

Abstract: An example system comprises a microelectromechanical system (MEMS) sensor, a strain gauge, and a strain compensation circuit. The MEMS sensor is operable to generate a sensor output signal that corresponds to a sensed condition (e.g., acceleration, orientation, and/or pressure). The strain gauge is operable to generate a strain measurement signal indicative of a strain on the MEMS sensor. The strain compensation circuit is operable to modify the sensor output signal to compensate for the strain based on the strain measurement signal. The strain compensation circuit stores sensor-strain relationship data indicative of a relationship between the sensor output signal and the strain measurement signal. The strain compensation circuit is operable to use the sensor-strain relationship data for the modifying of the sensor output signal. The modification of the sensor output signal comprises one or both of: removal of an offset from the sensor signal, and application of a gain to the sensor signal.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

Abstract: A substrate structure is provided. The substrate structure includes a substrate and a carrier. The substrate includes a first through hole, a first surface and a second surface opposite to the first surface. The first through hole penetrates the substrate for connecting the first surface and the second surface. The carrier includes a second through hole, a release layer, an insulating paste layer and a metal layer. The insulating paste layer is disposed between the release layer and the metal layer. The carrier is attached to the second surface with the release layer thereof. The second through hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: A component-embedded resin substrate includes a resin structure including a plurality of laminated resin layers and having an end surface surrounding an outer periphery of the resin layers and a plurality of embedded components arranged as embedded in the resin structure. The plurality of embedded components include a first embedded component and a second embedded component. When viewed in a planar view, the first embedded component has a first outer side extending along a portion of an end surface 5 closest to the first embedded component. When viewed in a planar view, the second embedded component has a second outer side extending along a portion of the end surface closest to the second embedded component. When viewed in a planar view, the outer side is oblique to the second outer side.

Abstract: A method of producing a structure containing a phase-separated structure, including a step in which a layer including an Si-containing block copolymer having a plurality of blocks bonded is formed between guide patterns on a substrate; a step in which a solution of a top coat material is applied to the layer and the guide patterns so as to form a top coat film; and a step in which the layer including the Si-containing block copolymer and having the top coat film formed thereon is subjected to annealing treatment so as to conduct a phase separation of the layer; in which a solvent of the solution of the top coat material contains no basic substance.

Abstract: A method for forming a patterned topography on a substrate is provided. The substrate is initially provided with an exposed plurality of lines formed atop. An embodiment of the method includes aligning and preparing a first directed self-assembly pattern (DSA) pattern immediately overlying the plurality of lines, and transferring the first DSA pattern to form a first set of cuts in the plurality of lines. The embodiment further includes aligning and preparing a second DSA pattern immediately overlying the plurality of lines having the first set of cuts formed therein, and transferring the second DSA pattern to form a second set of cuts in the plurality of lines. The first and second DSA patterns each comprise a block copolymer having a hexagonal close-packed (HCP) morphology and a characteristic dimension Lo that is between 0.9 and 1.1 times the spacing between individual lines of the plurality of lines.

Abstract: A rigid-flexible substrate includes a plurality of rigid portions, and a flexible portion connecting the plurality of rigid portions and including a portion of a first resin sheet including at least one layer of a thermoplastic resin sheet, the rigid portions including a portion of the first resin sheet other than the flexible portion, and a second resin sheet including a plurality of thermoplastic resin sheets laminated on one surface or both surfaces of the portion of the first resin sheet other than the flexible portion, and a tapered portion is provided at an end edge of the second resin sheet on a side close to the flexible portion, and a thickness of the tapered portion in a direction in which the second resin sheet is laminated decreases toward the flexible portion and is substantially 0 at a position in contact with the flexible portion.

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material that has been covered with catalytic adhesive material on both faces of the dielectric laminate material. The layer of catalytic adhesive coats a portion of the dielectric laminate material around the hole. The patterned metal layer is placed over the catalytic adhesive material on both faces of the dielectric laminate material and within the hole.

Abstract: A material (M) includes a substrate one of the surfaces of which is covered with a layer based on a block copolymer having a block (B) consisting of a polysaccharide and to its uses for electronics, in order to prepare organic electroluminescent diodes (OLEDs) or organic photovoltaic cells (OPV) or for designing detection devices (nanobiosensors, biochips).

Abstract: According to an embodiment, a guide pattern having a first opening pattern and a second opening pattern shallower than the first opening pattern, is formed on a film to be processed. A directed self-assembly material is set into the first and second opening patterns. The directed self-assembly material is phase-separated into first and second phases in the first and second opening patterns. A third opening pattern is formed by removing the first phase. The third opening pattern in the second opening pattern is eliminated, and the second and third opening patterns are transferred to the film to be processed, by one etching to be processed from the tops of the second and third opening patterns.

Abstract: Provided herein is a method, including etching a first pattern into a mask, wherein the first pattern includes a first set of features corresponding to features of an imprint template; forming a second set of features over and in-between the first set of features by directed self-assembly of a block copolymer composition, wherein the first and second sets of features combine to form a second pattern; and etching the second pattern into a substrate.

Abstract: Structures including alternating first U-shaped electrodes and second U-shaped electrodes and contact pads interconnecting the first and the second U-shaped electrodes are provided. Each of the first U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on one end of a substrate. Each of the second U-shaped electrodes includes substantially parallel straight portions connected by a bent portion located on an opposite end of the substrate. Every adjacent straight portions of neighboring first and second U-shaped electrodes constitute an electrode pair having a sub-lithographic pitch. Each of the contact pads overlaps and contacts the bent portion of one of the first and the U-shaped electrodes.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

Abstract: Copper electroplating liquid which does not use formaldehyde, which is harmful to the environment, and which exhibits excellent via filling ability is offered. The copper electroplating liquid of this invention includes the compound that has the structure of —X—S—Y— where X and Y are each an atom selected from the group of hydrogen atoms, carbon atoms, sulfur atoms, nitrogen atoms and oxygen atoms, and X and Y can be the same only when they are carbon atoms, and a specific urea derivative. When the copper electroplating liquid is used, deterioration of the appearance will not occur and a good filled via can be formed.

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming an MRAM device, and a method of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a second layer over a first layer, and performing a first etch process on the second layer to define a feature, wherein the first etch process forms a film on a surface of the feature. The method further comprises performing an ion beam etch process on the feature, wherein the ion beam etch removes the film from the surface of the feature.

Abstract: A functional device according to an embodiment of the invention includes: an insulating substrate; a movable section; movable electrode fingers provided in the movable section; and fixed electrode fingers provided on the insulating substrate and arranged to be opposed to the movable electrode fingers. The fixed electrode fingers include: first fixed electrode fingers arranged on one side of the movable electrode fingers; and second fixed electrode fingers arranged on the other side of the movable electrode fingers. The first fixed electrode fingers and the second fixed electrode fingers are arranged to be spaced apart from each other.

Abstract: A method for manufacturing a PCB includes certain steps. A printed circuit board sheet is provided. The printed circuit board includes an unwanted portion and a printed circuit board unit which includes a plurality of contact pads. An imaginary boundary line is defined between the printed circuit board unit and the unwanted portion. Each of the contact pads defines an outline. A nearest distance between the outline and the imaginary boundary line is less than 4 millimeters. The printed circuit board sheet is punched along the imaginary boundary line, forming one hollow portion or a plurality of through slots. A plurality of burrs is generated on an inner surface of the hollow portion or the through slots. The burrs are removed using a low-energy laser cutting process, thereby obtaining a printed circuit board. A laser power used in the low-energy laser cutting process is 5-8 watts.

Abstract: A vibration layer is formed by the AD method on a cavity plate before forming pressure chambers, a common electrode is formed on the vibration layer, and a piezoelectric layer is formed on the common electrode by the AD method. Subsequently, the pressure chambers are formed in the cavity plate by the etching. After that, individual electrodes are formed on the piezoelectric layer. Subsequently, the stack of the cavity plate, the vibration layer, the common electrode, the piezoelectric layer, and the individual electrodes is heated at about 850° C. to simultaneously perform the annealing of the piezoelectric layer and the sintering of the individual electrodes and the common electrode. Accordingly, the atoms of the cavity plate are suppressed from being diffused into the driving portions of the piezoelectric layer.

Abstract: A method and system for integrated circuit fabrication is disclosed. In an example, the method includes determining a first process parameter of a wafer and a second process parameter of the wafer, the first process parameter and the second process parameter corresponding to different wafer characteristics; determining a variation of a device parameter of the wafer based on the first process parameter and the second process parameter; constructing a model for the device parameter as a function of the first process parameter and the second process parameter based on the determined variation of the device parameter of the wafer; and performing a fabrication process based on the model.

Abstract: A pressure sensor comprises a first substrate containing a processing circuit integrated thereon and a cap attached to the first substrate. The cap includes a container, a holder, and one or more suspension elements for suspending the container from the holder. The container includes a cavity and a deformable membrane separating the cavity and a port open to an outside of the pressure sensor. The container is suspended from the holder such that the deformable membrane faces the first substrate and such that a gap is provided between the deformable membrane and the first substrate which gap contributes to the port. Sensing means are provided for converting a response of the deformable membrane to pressure at the port into a signal capable of being processed by the processing circuit.

Abstract: A manufacturing method of a touch panel includes the steps of providing a substrate, forming a first conductive film on the substrate, forming a first mask on the first conductive film, etching the first conductive film to form electrode portions and lower intersect portions of the touch panel, forming an insulating film made of a negative resist on the first conductive film, and forming a contact hole above the electrode portion by removing the insulating film. The steps further include forming a second conductive film on the insulating film, forming a second mask on the second conductive film, etching the second conductive film to form an upper intersect portion connected between two adjacent electrode portions via the contact hole and intersecting with the lower intersect portion, and forming protective film on the second conductive film.

Abstract: The present invention relates to a method for realizing a short-circuited slot-line on a multilayer substrate comprising at least a first conductive layer, a dielectric layer and a second conductive layer, the method comprising the following steps: etching in the first conductive layer a slot-line (2) having an electrical length L, etching in the first conductive layer, around the slot-line, a first portion of a first band having an electrical length L1?L, etching in the first conductive layer, around the slot-line, a second portion of said first band, having an electrical length L2?L, etching in the second conductive layer, a second band in the form of a loop having an electrical length L3, one end of the second band being connected to the first part of the first band and the other end of the second band being connected to the second part of the first band so as to form a conductive loop. The method is used notably to realize isolating slot-lines and slot-antennae.

Abstract: Anode foils suitable for use in electrolytic capacitors, including those having multiple anode configurations, have improved strength, reduced brittleness, and increased capacitance compared to conventional anode foils for electrolytic capacitors. Exemplary methods of manufacturing an anode foil suitable for use in an electrolytic capacitor include disposing a resist material in a predetermined pattern on an exposed surface of an anode foil substrate such that a first portion of the exposed surface of the anode foil substrate is covered by the resist material, and a second portion of the exposed surface remains uncovered; polymerizing the resist material; exposing at least the second portion of the exposed surface to one or more etchants so as to form a plurality of tunnels; stripping the polymerized resist material; and widening at least a portion of the plurality of tunnels. The resist material may be deposited, for example, by ink-jet printing, stamping or screen printing.

Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).

Abstract: The present disclosure relates to a method of fabricating a capacitive touch pane where a plurality of groups of first conductive patterns are formed along a first direction, a plurality of groups of second conductive patterns are formed along a second direction, and a plurality of connection components are formed on a substrate. Each first conductive pattern is electrically connected to another adjacent first conductive pattern in the same group by each connection component and each group of the second conductive patterns is interlaced with and insulated from each group of the first conductive patterns. Next, a plurality of curved insulation mounds are formed to cover the first connection components. Then, a plurality of bridge components are formed to electrically connect each second conductive pattern with another adjacent second conductive pattern in the same group.

Abstract: A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front side, a back side and partially etched and metalized through silicon vias each extending from a portion of the front side through a portion of the back side, terminating before reaching an end surface of the back side. A region of the back side of the wafer is patterned and etched to expose and reveal a portion of each of the plurality of through silicon vias. A metal layer is deposited on the back side of the wafer to form a back side metallization. The metal layer covers all of the back side including the etched region of the back side and the exposed portions of each of the through silicon vias.

Abstract: There is provided a method for manufacturing a printed circuit board including: preparing a substrate having a conductive layer formed on at least a portion thereof; forming an insulating layer formed with an opening through which a portion of the conductive layer is exposed on the substrate; forming a plating seed layer on the insulating layer and the exposed conductive layer; forming an electroplating layer on the plating seed layer by overplating the plating seed layer; and etching the overplated portion in a lump to form a circuit layer in the opening.

Abstract: A method of forming a particulate material comprising silicon, the method comprising the step of reducing a particulate starting material comprising silica-containing particles having an aspect ratio of at least 3:1 and a smallest dimension of less than 15 microns, or reducing a particulate starting material comprising silica-containing particles comprising a plurality of elongate structural elements, each elongate structural element having an aspect ratio of at least 3:1 and a smallest dimension of less than 15 microns.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention may include: an insulating layer; a first via depressed from one surface of the insulating layer; a second via depressed from the other surface of the insulating layer; and a circuit pattern formed in the insulating layer and bonded to the first and second vias.

Abstract: A method of forming a conductive via in a substrate includes forming a via hole covered by a dielectric layer followed by an annealing process. The dielectric layer can getter the mobile ions from the substrate. After removing the dielectric layer, a conductive material is formed in the via hole, forming a conductive via in the substrate.

Abstract: A system for the manufacture of an end effector assembly which is configured for use with an electrosurgical instrument configured for performing an electrosurgical procedure is provided. The system includes a photolithography module that is configured to etch one or more pockets on a seal surface of the seal plate. A vacuum module is configured to raise, transfer and lower a spacer from a location remote from the pocket(s) on the seal plate to the pocket on the seal plate(s). An adhesive dispensing module is configured to dispense an adhesive into the pocket on the seal plate. An optical module is configured to monitor a volume of the adhesive dispensed within the pocket and monitor placement of the spacer within the pocket.

Abstract: Flexible electronic substrate systems relating to providing a system for dimensionally-stable substrate systems to support electronic systems is provided.

Abstract: A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer.

Abstract: A technique is provided for a structure. A substrate has a nanopillar vertically positioned on the substrate. A bottom layer is formed beneath the substrate. A top layer is formed on top of the substrate and on top of the nanopillar, and a cover layer covers the top layer and the nanopillar. A window is formed through the bottom layer and formed through the substrate, and the window ends at the top layer. A nanopore is formed through the top layer by removing the cover layer and the nanopillar.

Abstract: A microfluidic chip for a microfluidic system includes a PDMS substrate having a first thickness, at least one microfluidic pathway in the substrate, a coating along the microfluidic pathway, and a glass layer having a second thickness on the substrate and above the microfluidic pathway, wherein the coating contains an optically transparent material, and the first thickness is greater than the second thickness. The coating includes cyanoacrylates, an UV curable epoxy adhesive, a gel epoxy or epoxy under trade name of EPO-TEK 0G175, MasterBond EP30LV-1 or Locite 0151.

Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, a conductor layer formed on the insulating layer, and a cover layer covering the conductor layer. The insulating layer and the cover layer are formed from different materials, whose coefficients of hygroscopic expansion are in the range between 3×10?6/% RH and 30×10?6/% RH. The difference between the coefficients of hygroscopic expansion of the two materials is 5×10?6/% RH or less.

Abstract: A method of forming a window cap wafer (WCW) structure for semiconductor devices includes machining a plurality of cavities into a front side of a first substrate; bonding the first substrate to a second substrate, at the front side of the first substrate; removing a back side of the first substrate so as to expose the plurality of cavities, thereby defining the WCW structure comprising the second substrate and a plurality of vertical supports comprised of material of the first substrate.

Abstract: Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines.

Abstract: The present invention discloses a touch screen panel and a method for manufacturing the same, and a display device. The method comprises: forming patterns of a bridging layer and a shielding layer on a substrate by one patterning process; then forming a pattern of an insulating layer on the shielding layer; and forming a pattern of a touch electrode layer on the insulating layer. In the embodiments of the invention, the patterning of the bridging layer and the shielding layer is accomplished simultaneously in one patterning process, thereby the number of patterning times during the manufacture process can be reduced, the manufacture efficiency of the touch screen panel can be improved, and the production cost can be lowered.

Abstract: A bulk boron doped diamond electrode comprising a plurality of grooves disposed in a surface of the bulk boron doped diamond electrode. The bulk boron doped diamond electrode is formed by growing a bulk boron doped diamond electrode using a chemical vapour deposition technique and forming a plurality of grooves in a surface of the bulk boron doped diamond electrode. According to one arrangement, the plurality of grooves are formed by forming a pattern of carbon solvent metal over a surface of the bulk boron doped diamond electrode and heating whereby the carbon solvent metal dissolves underlying diamond to form grooves in the surface of the bulk boron doped electrode. The invention also relates to an electrochemical cell comprising one or more grooved bulk boron doped diamond electrodes. The or each bulk boron doped diamond electrode is oriented within the electrochemical device such that the grooves are aligned in a direction substantially parallel to a direction of electrolyte flow.

Abstract: A technique is provided for forming a nanodevice for sequencing. A bottom metal contact is disposed at a location in an insulator that is on a substrate. A nonconducting material is disposed on top of the bottom metal contact and the insulator. A carbon nanotube is disposed on top of the nonconducting material. Top metal contacts are disposed on top of the carbon nanotube at the location of the bottom metal contact, where the top metal contacts are formed at opposing ends of the carbon nanotube at the location. The carbon nanotube is suspended over the bottom metal contact at the location, by etching away the nonconducting material under the carbon nanotube to expose the bottom metal contact as a bottom of a trench, while leaving the nonconducting material immediately under the top metal contacts as walls of the trench.

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: A micromechanical solid-electrolyte sensor device includes a micromechanical carrier substrate having a front side and a back side. The micromechanical solid-electrolyte sensor device also includes a first porous electrode and a second porous electrode. The micromechanical solid-electrolyte sensor device also includes a solid-electrolyte embedded between the first porous electrode and the second porous electrode.

Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.

Abstract: A particular device includes a coil and a discontinuous magnetic core. The discontinuous magnetic core includes a first elongated portion, a second elongated portion, and at least two curved portions, where the portions are coplanar and physically separated from each other. The discontinuous magnetic core is arranged to form a discontinuous loop. The discontinuous magnetic core is deposited as a first layer above a dielectric substrate. A first portion of the coil extends above a first surface of the magnetic core. A second portion of the coil extends below a second surface of the magnetic core. The second portion of the coil is electrically coupled to the first portion of the coil. The second surface of the magnetic core is opposite the first surface of the magnetic core.

Abstract: A method for forming copper on a substrate including inputting a copper source solution into a mixer, inputting a reducing solution into the mixer, mixing copper source solution and the reducing solution to form a plating solution having a pH of greater than about 6.5 and applying the plating solution to a substrate, the substrate including a catalytic layer wherein applying the plating solution to the substrate includes forming a catalytic layer, maintaining the catalytic layer in a controlled environment and forming copper on the catalytic layer. A system for forming copper structures is also disclosed.