Filling Or Coating Of Groove Or Through Hole With A Conductor To Form An Electrical Interconnection Patents (Class 216/18)
  • Patent number: 10978383
    Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 13, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa
  • Patent number: 10971393
    Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: Kevin Lin
  • Patent number: 10968523
    Abstract: A method to partially decrease a reflectivity of a region on a mirror platform includes isolating the region on a surface of the mirror platform and removing a first material from the surface of the mirror platform within the region. The reflectivity of the mirror platform is decreased within the region.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 6, 2021
    Assignee: ELECTRIC MIRROR, LLC
    Inventors: James V. Mischel, Jr., James V. Mischel, Sr.
  • Patent number: 10964552
    Abstract: A method for producing a laminate that includes at least the following: providing a first intermediate laminate comprising a carrier substrate including a support therein and a peelable metal layer formed on at least one surface of the carrier substrate; forming, in a section not serving as a product of the first intermediate laminate, a first hole reaching at least the support in the carrier substrate from a surface of the first intermediate laminate, to prepare a second intermediate laminate with the first hole; stacking and disposing on the surface where the first hole is formed of the second intermediate laminate, an insulating material and a metal foil in this order when viewed from the surface; and pressurizing the second intermediate laminate, the insulating material and the metal foil in the stacking direction thereof with heating, to prepare a third intermediate laminate where the first hole is filled with the insulating material; and performing treatment with a chemical agent on the third intermedia
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 30, 2021
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Yoshihiro Kato, Takaaki Ogashiwa, Yoichi Nakajima, Takaaki Ichikawa, Kazuaki Kawashita
  • Patent number: 10886278
    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias individually having an upper horizontal perimeter. The conductive vias individually have an upper horizontal perimeter. Masking material is formed directly above the conductive vias. An opening is formed in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Sanh D. Tang
  • Patent number: 10856424
    Abstract: A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Sri Ranga Sai Boyapati, Amanda E. Schuckman, Sashi S. Kandanur, Srinivas Pietambaram, Mark Hlad, Kristof Darmawikarta
  • Patent number: 10852614
    Abstract: The present disclosure is directed to a method of forming a layered structure including a nanostructure layer having nanostructures. The method includes: forming a coating layer on the surface of the nanostructure layer, reflowing the coating layer, depositing one or more conductive plugs into the coating layer, and hardening the coating layer. The one or more conductive plugs each has a first portion configured to be placed in electrical communication with the nanostructure layer and a second portion not covered by the coating layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Paul Mansky, Kalpesh Biyani
  • Patent number: 10840101
    Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 17, 2020
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Mark J. Willey
  • Patent number: 10817641
    Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 27, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chung-Do Yang, Hoi-Kuen Lam, John Mario Wilkosz
  • Patent number: 10743424
    Abstract: The present invention provides a method for manufacturing a flexible array substrate. The method includes, first, successively forming an adhesive layer, a passivation layer, a back-side drive circuit, a planarization layer, a flexible backing plate, and a front-side drive circuit and a display circuit, in a stacked arrangement, on a rigid support plate and then peeling off the rigid support plate and the adhesive layer to form a flexible array substrate having a double-sided circuit structure. The entire process requires no steps of peeling, reversing, and then re-attaching of the flexible backing plate so that it is possible to avoid the issues of poor flatness and low yield resulting from improper or wrongful re-attachment of the flexible backing plate and thus, fabrication difficulty of a flexible array substrate having a double-sided circuit structure may be lowered down to thereby improve fabrication yield of the flexible array substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 11, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lixuan Chen, Yungjui Lee
  • Patent number: 10642152
    Abstract: A method of designing a feature guiding template for guiding self-assembly of block copolymer to form at least two features in a design layout for lithography, the feature guiding template including at least two portions joined by a bottleneck, the method including determining a characteristic of the feature guiding template based on at least a function of geometry of the feature guiding template including a value of a first width of at least one of the portions, a value of a second width of the bottleneck, or a value based on both the first width and the second width.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 5, 2020
    Assignee: ASML Netherlands B.V
    Inventors: Sander Frederik Wuister, Davide Ambesi
  • Patent number: 10559982
    Abstract: Various techniques are described herein for efficiently transmitting and receiving wireless power and/or data signals. In one example, a transmitter includes multiple antennas, a dielectric material in proximity to the multiple antennas, and multiple scattering elements embedded in the dielectric material. One or more of the multiple scattering elements are configured to be excited by one or more signals emitted by the multiple antennas.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 11, 2020
    Assignee: Ossia Inc.
    Inventors: Hatem Zeine, Siamak Ebadi, Douglas Wayne Williams
  • Patent number: 10553672
    Abstract: A metal-insulator-metal (MIM) capacitor includes a semiconductor substrate and a capacitor device. The capacitor device includes a first conductor upright on the semiconductor substrate, a second conductor upright on the semiconductor substrate, and an insulator disposed used for insulating the first conductor from the second conductor. In a method for fabricating the capacitor device, a mask including a test line pattern and a capacitor pattern with a first trench pattern and a second trench pattern is used to form a test line and the first conductor and the second conductor of the capacitor device, thereby decreasing the cost of for fabricating the MIM capacitor.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Jhih Huang, Chun-Yuan Hsu, Chien-Chung Chen, Yung-Hsieh Lin
  • Patent number: 10453886
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 10429892
    Abstract: An electronic device may have a housing formed from a rigid material such as metal or fiber-composite material. A display such as an organic light-emitting diode display may be attached to a planar wall portion of the housing using a layer of adhesive. A display cover layer may be attached to the organic light-emitting diode with a layer of adhesive. The adhesive layers may be rigid to enhance device stiffness. The housing may have curved sidewall portions that extend outwardly from the planar wall portion to enhance stiffness. The organic light-emitting diode display may have an array of pixels formed from thin-film transistor circuitry. The thin-film transistor circuitry may be formed on a substrate such as a glass substrate that is attached to the planar wall portion. The organic light-emitting diode display may have a circular polarizer that is attached to the thin-film transistor circuitry.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 1, 2019
    Assignee: Apple Inc.
    Inventors: Dinesh C. Mathew, Adam T. Garelli, Mikael M. Silvanto
  • Patent number: 10366951
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Patent number: 10362687
    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 23, 2019
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Dale Kersten
  • Patent number: 10340205
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Patent number: 10301738
    Abstract: Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: May 28, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan L. Buckalew, Steven T. Mayer, Thomas A. Ponnuswamy, Robert Rash, Brian Paul Blackman, Doug Higley
  • Patent number: 10283445
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 7, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10264185
    Abstract: The electronic apparatus includes a first circuit board on which a circuit mounted, a second circuit board arranged close to the circuit on the first circuit board, and a conductive terminal, which is in contact with a ground pattern on the first circuit board, and is arranged at a location between the circuit and the second circuit board so as to extend over the circuit.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 16, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Jun Hirabayashi
  • Patent number: 10236257
    Abstract: A method for constructing an advance conductor structure is described. A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10178781
    Abstract: An electronic device including: an electronic circuit accommodated in a circuit housing having a first thermal expansion coefficient, and a molded body which surrounds the circuit housing, the body having a second thermal expansion coefficient that differs from the first thermal expansion coefficient. The molded body is fixed to the circuit housing at least at two different mutually spaced fixing points on the circuit housing.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: January 8, 2019
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Jakob Schillinger, Ulrich Schrader, Dietmar Huber
  • Patent number: 10167559
    Abstract: A method for manufacturing a gap device includes forming a template structure on a substrate, depositing an active material layer on the substrate and on the template structure, wherein the active material layer covers at least top and side surfaces of the template structure, planarizing the active material layer, and selectively removing the template structure with respect to the active material layer and the substrate.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emanuel Loertscher, Marcel Mayor, Gabriel Fernando Puebla Hellman
  • Patent number: 10169504
    Abstract: A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatus's include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Keiji Matsumoto
  • Patent number: 10147637
    Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 4, 2018
    Assignee: IMEC vzw
    Inventors: Youssef Drissi, Ryan Ryoung han Kim, Stephane Lariviere, Praveen Raghavan, Darko Trivkovic
  • Patent number: 10144185
    Abstract: Methods, systems and apparatuses are disclosed for making and post-processing a 3-D printed object for laminate-forming tooling, and components made using post-processed 3-D printed laminate-forming tooling.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: December 4, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Benjamin J. Stephenson, Scott K Frankenbery, William H Ingram, Jr., William S. Hollensteiner
  • Patent number: 10138558
    Abstract: The ampholytic surfactants show the nature of anionic surfactants in an alkaline region and the nature of cationic surfactants in an acidic region. As described below, the pretreatment solution of the present invention may preferably indicate alkalinity of pH 8.5 or higher, and therefore, it exhibits the nature of cationic surfactants by the use of ampholytic surfactants. As the ampholytic surfactants, those disclosed in JP 2011-228517 A can be used.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: November 27, 2018
    Assignee: C. UYEMURA & CO., LTD.
    Inventors: Yoshikazu Saijo, Hisamitsu Yamamoto, Tetsuji Ishida, Takuya Komeda, Masayuki Utsumi
  • Patent number: 10134675
    Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10115661
    Abstract: Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The filler is laterally located between the first inductor winding and the second inductor winding. The filler is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: James Thomas Doyle, Farsheed Mahmoudi, Amirali Shayan Arani
  • Patent number: 10109564
    Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 23, 2018
    Assignee: NXP B.V.
    Inventors: Roelf Groenhuis, Leo Van Gemert, Tonny Kamphuis, Jan Gulpen
  • Patent number: 10106896
    Abstract: A method to create a media display device viewing area in a mirror platform includes isolating the media display device viewing area from the rest of a glass layer of the mirror platform. The glass layer has a backing layer and an optional paint layer. A solvent is applied to remove optional protective paint, if present, from a backing layer within the media display device viewing area. The protective paint, if present, is scraped from the media display device viewing area. An etching solution is applied to the media display device viewing area to remove the backing layer. The media display device viewing area is rinsed.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: October 23, 2018
    Assignee: ELECTRIC MIRROR, LLC
    Inventors: James V. Mischel, Jr., James V. Mischel, Sr.
  • Patent number: 10096624
    Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: October 9, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Yong Park, Tae-Gon Kim
  • Patent number: 10098223
    Abstract: A sensor device for integration in an electrical circuit, including a support layer (12?), which is formed with a release layer; at least one flexible insulating layer (14?, 32), which is made using a printing method; and at least one flexible electrical conductor structure (20?, 34), which is applied with a printing method onto the insulating layer (14). The insulating layer (14?, 32) and the conductor structure (20?, 34) form a flexible unit, which is removable without damage from the support layer (12?).
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: October 9, 2018
    Assignee: SCHREINER GROUP GMBH & CO. KG
    Inventors: Peter Seidl, Sebastian Gepp, Thomas Weik, Manfred Hartmann
  • Patent number: 10056332
    Abstract: This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at the back surface of the board. The back-surface ground pattern is provided with a notch overlapping a region of an upper wiring layer at which a board member is exposed and which is encircled by a wide pattern, the notch permitting the release of water vapor from the region.
    Type: Grant
    Filed: June 17, 2017
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Shibuya
  • Patent number: 9981457
    Abstract: The stack manufacturing apparatus includes a first supporting body supply unit which is configured to intermittently unroll a roll sheet-shaped first supporting body and includes one of a pair of tension applying devices capable of applying tension to the unrolled first supporting body; a first adhesive layer formation unit configured to form a first adhesive layer over the first supporting body while the first supporting body supply unit suspends unrolling of the first supporting body; a first bonding unit configured to bond the first supporting body and a sheet-shaped member using the first adhesive layer; and a control unit which is configured to hold an end portion of the first supporting body and includes the other of the pair of tension applying devices.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 29, 2018
    Assignee: Semiconductor Emergy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Satoshi Seo
  • Patent number: 9953864
    Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 9953869
    Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 9942982
    Abstract: A multilayer electrical device, such as a printed circuit board, having a tooth structure including a metal layer set in a dielectric. The device includes a base; a conductive layer adjacent to the base; a dielectric material adjacent to conductive layer; a tooth structure including a metal layer set in the dielectric material to join the dielectric material to the metal layer; and wherein the metal layer forms a portion of circuitry in a circuit board having multiple layers of circuitry.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: April 10, 2018
    Assignee: Continental Circuits, LLC
    Inventors: Brian J. McDermott, Daniel McGowan, Ralph Leo Spotts, Jr., Sid Tryzbiak
  • Patent number: 9929080
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Saikumar Jayaraman
  • Patent number: 9929097
    Abstract: In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a substrate build-up film is introduced having epoxy material and a plurality of epoxy microspheres, wherein an interior of the microspheres is not fully cured. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Nalla, Omar Bchir, Houssam Jomaa
  • Patent number: 9893011
    Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
  • Patent number: 9894773
    Abstract: Embodiments of the invention relates to adding test access to a back-drilled vertical access interconnect (VIA) of a printed circuit board (PCB). A VIA is either formed or provided as an opening through layers of the PCB. The VIA is countersunk from one of the two openings to the PCB prior to plating to form a surface that can be used as a test target. The countersunk VIA is subject to plating so that the interior walls and surfaces of the VIA are covered with a conductive material. The plating is removed along the walls of the countersunk section of the VIA, so that the plating remains on the shoulders and the non-countersunk section of the VIA with the shoulder in communication with a trace internal to the PCB. The back-drilled VIA with the plating configuration provides an internal conducting surface for contact while mitigating interference associated with a VIA stub.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 13, 2018
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Derek Robertson, Vincent M. Rogers
  • Patent number: 9870995
    Abstract: A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first copper layer. The carbon-rich copper layer is sandwiched between the first copper layer and the second copper layer. A carbon concentration of the carbon-rich copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-Nan Nian, Shiu-Ko Jangjian, Chi-Cheng Hung, Yu-Sheng Wang, Hung-Hsu Chen
  • Patent number: 9859433
    Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 9839136
    Abstract: The present disclosure relates, according to some embodiments, to the fabrication of a flexible circuit board, which includes forming a base layer comprising polyimide, forming a polyimide layer on the base layer, the polyimide layer having a first surface and a second surface opposite to each other, the first surface being peelably adhered in contact with the base layer, forming a metal layer on the second surface of the polyimide layer, and peeling the base layer from the polyimide layer with the metal layer remaining on the second surface of the polyimide layer.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 5, 2017
    Assignee: Taimide Technology Incorporation
    Inventors: Paul S. C. Wu, Chun-Ting Lai, Yen-Po Huang, Sheng-Yu Huang
  • Patent number: 9832875
    Abstract: A method for fabricating printed electronics includes printing a trace of an electrical component on a first substrate to form a first layer. The method further includes printing a trace of an electrical component on at least one additional substrate to form at least one additional layer. The first layer is stacked with the at least one additional layer to create an assembled electrical device. At least one of the layers is modified after printing.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: November 28, 2017
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Slade R. Culp, Sameh Dardona, Wayde R. Schmidt
  • Patent number: 9828688
    Abstract: Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 28, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan L. Buckalew, Steven T. Mayer, Thomas A. Ponnuswamy, Robert Rash, Brian Paul Blackman, Doug Higley
  • Patent number: 9831227
    Abstract: A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with an optoelectronic device and a further device, wherein the optoelectronic device and the further device are interconnected to one another in parallel when the semiconductor apparatus is in operation, wherein the optoelectronic device is connected to a first contact and a second contact, the first contact and the second contact being configured to externally contact the semiconductor apparatus, and wherein the further device is connected with at least one further contact of the semiconductor apparatus.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: November 28, 2017
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Siegfried Herrmann
  • Patent number: 9799562
    Abstract: Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: October 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Sarah A. Niroumand