Filling Or Coating Of Groove Or Through Hole With A Conductor To Form An Electrical Interconnection Patents (Class 216/18)
  • Patent number: 11881414
    Abstract: A glass device including a thin glass substrate which has a glass thickness of 300 ?m or less is enabled to be provided more easily. In a method for manufacturing the glass device, one or more through holes are formed in a glass substrate, and a first wiring on a first surface side of the glass substrate and a second wiring on a second surface side of the glass substrate are electrically connected to each other via the through holes. After the first wiring is provided, the through holes are formed while the glass substrate is being thinned by etching. Then, wirings in the through holes and the second wiring are formed. The thinned glass substrate has a thickness of 50 ?m or more and 300 ?m or less. The through holes have the shape of a truncated cone.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: January 23, 2024
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Masashi Sawadaishi
  • Patent number: 11791358
    Abstract: A method of forming a semiconductor device includes forming photodiodes extending from a front-side surface of a semiconductor layer into the semiconductor layer; forming transistors on the front-side surface of the semiconductor layer; forming an interconnect structure over the transistors, the interconnect structure comprising an inter-metal dielectric and metal lines in the inter-metal dielectric; etching first regions of a backside surface of the semiconductor layer to form trenches in the semiconductor layer and non-overlapping the photodiodes; after forming the trenches, etching second regions of the backside surface of the semiconductor layer to form pits in the semiconductor layer and overlapping the photodiodes; and depositing a dielectric material in the trenches and the pits.
    Type: Grant
    Filed: August 7, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11745292
    Abstract: A glass panel processing method includes a first deformed portion formation step in which, in order to form a via-hole in a glass substrate, a first deformed portion is formed to a first depth from the upper surface of the glass substrate through irradiation with a laser beam along a planned via-hole line, a second deformed portion formation step in which, in order to cut the glass substrate into unit cells, a second deformed portion is formed to a second depth in the glass substrate through irradiation with a laser beam along a planned cutting line, and an etching step in which, the glass substrate with the first deformed portion and the second deformed portion formed therein is etched such that etching of the glass substrate along the planned cutting line is completed before completion of etching of the glass substrate along the planned via-hole line.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: September 5, 2023
    Assignees: JOONGWOO NARA CO., LTD., BSP CO., LTD.
    Inventors: Sung Soo Park, Hong Jin Park
  • Patent number: 11460778
    Abstract: Improved stripper solutions for removing photoresists from substrates are provided that exhibit improved compatibility with copper, leadfree solder, and epoxy-based molding compounds. The stripper solutions comprise a primary solvent, a secondary glycol ether solvent, potassium hydroxide, and an amine. The solutions also exhibit reduced potassium carbonate crystal formation compared to conventional formulations containing potassium hydroxide, and extended bath life compared to formulations containing tetramethylammonium hydroxide.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 4, 2022
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Richard Dalton Peters, Yuanmei Cao
  • Patent number: 11444029
    Abstract: A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Prasad Bhosale, Nicholas Anthony Lanzillo, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 11439026
    Abstract: A method for manufacturing a printed circuit board includes forming a through hole in an insulating layer of the printed circuit board, filling the through hole by plating to form a plating layer on the insulating layer, and removing the plating layer from the insulating layer; and forming a circuit pattern on the insulating layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung-Soo Kim, Jin-Won Lee
  • Patent number: 11406018
    Abstract: A double-sided and multilayer flexible printed circuit (FPC) substrate contains: a body, multiple tilted vias passing through the body, a sputtering layer, multiple conductive portions, and multiple copper circuit layers. The sputtering layer is adhered on the body and the multiple tilted vias. A respective conductive portion is formed in a respective titled via and is connected with the sputtering layer. The multiple copper circuit layers are located on a top and a bottom of the body and are connected with the sputtering layer, and the multiple copper circuit layers are connected via the multiple conductive portions.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 2, 2022
    Assignee: APLUS SEMICONDUCTOR TECHNOLOGIES CO., LTD.
    Inventors: Sui-Ho Tsai, Cheng-Neng Chen, Yun-Nan Wang, Chih-Yuan Chao, Hsueh-Tsung Lu
  • Patent number: 11398419
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through the conductive structure. The conductive through via is a monolithic structure, and includes a main portion and an extending portion protruding from the main portion.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11348892
    Abstract: A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-K dielectric material.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehyung Park, Seokho Kim, Hoonjoo Na, Kwangjin Moon, Kyuha Lee, Joohee Jang
  • Patent number: 11328934
    Abstract: Provided is an etching method performed in a substrate-processing apparatus having: a first electrode on which a substrate is placed; and a second electrode facing the first electrode, the method comprising: a first step for introducing a first gas and halfway etching a target film into a pattern of a predetermined film on the target film formed on the substrate; a second step for introducing a second gas including Ar gas, H2 gas, and deposition gas and applying DC voltage to the second electrode to form a protective film, the second step being performed after the first step; and a third step for introducing a third gas and etching the target film, the third step being performed after the step for forming the protective film.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 10, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Sho Oikawa, Wakako Ishida
  • Patent number: 11317511
    Abstract: The present disclosure provides a circuit board. The circuit board may include a number of stacked core boards each having a top surface. At least part core boards of the number of stacked core boards may include circuit layers at top surfaces thereof. A groove may be defined through the at least part core boards. A conductive material may be received in the groove configured to couple to the circuit layers of at least two core boards. A cross section of the groove may include a length in a first direction and a length in a second direction, and the length in the first direction may be greater than the length in the second direction. Electroplating solution may capable of contacting any portions of the groove to electroplate, to form the conductive material.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: April 26, 2022
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Zhi Li, Xuechuan Han, Rong Cui, Zhenbo Liu
  • Patent number: 11281094
    Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 22, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Roman Gouk, Giback Park, Kyuil Cho, Han-Wen Chen, Chintan Buch, Steven Verhaverbeke, Vincent Dicaprio
  • Patent number: 11252814
    Abstract: A grounding structure of the high-frequency circuit board includes a dielectric substrate, a back surface ground electrode, an upper ground electrode, and a microstripline upper electrode. The dielectric substrate has a first surface and a second surface, and is provided with a first through-hole. A first opening of the first through-hole at the first surface is smaller than a second opening of the first through-hole at the second surface. A first grounding conductor layer is provided in the first through-hole. The back surface ground electrode is provided at the second surface and is connected with the first grounding conductor layer. The upper ground electrode is provided at the first surface and is connected with the first ground conductor layer. The microstripline upper electrode is provided at the first surface.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: February 15, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Yasuaki Asahi, Haruo Kojima
  • Patent number: 11234331
    Abstract: A multilayer printed circuit board providing large current and high power includes an inner circuit laminated structure, a first adding-layer circuit base board, and second adding-layer circuit base board. The inner circuit laminated structure includes at least one first type and second type conductive circuit layer alternately stacked. The first and second type conductive circuit layer are respectively made of first and second type metal layer, the first and second type metal layer have different etching ability. The second adding-layer circuit base board and the first adding-layer circuit base board are formed on opposite surfaces of the inner circuit laminated structure. The first and second adding-layer circuit base boards are electrically connected to the inner circuit laminated structure. The disclosure also provides a method for manufacturing such multilayer printed circuit board.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 25, 2022
    Assignees: HongQiSheng Precision Electronics (QingHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Cheng-Jia Li, Mei Yang
  • Patent number: 11222791
    Abstract: A printed wiring board includes a resin insulating layer, a metal post formed in the resin insulating layer such that the metal post is protruding from a first surface of the resin insulating layer, a conductor layer formed on a second surface of the resin insulating layer on the opposite side with respect to the first surface of the resin insulating layer, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the metal post and the conductor layer. The metal post has a protruding portion protruding from the first surface of the resin insulating layer and an embedded portion integrally formed with the protruding portion and embedded in the resin insulating layer.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 11, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoji Sawada, Nobuhisa Kuroda, Kazuyuki Ueda, Shota Tachibana
  • Patent number: 11222812
    Abstract: One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: January 11, 2022
    Assignee: Infineon Technologies AG
    Inventor: Matthias Stecher
  • Patent number: 11197379
    Abstract: The method for producing a printed wiring board according to the present invention with use of a metal-clad laminated sheet including a metal foil laminated on each of both surfaces of an insulating resin base material, the method at least including: a step (1) of irradiating a predetermined position in a surface (A) of the metal-clad laminated sheet with a laser to provide a via hole leading to the metal foil in a surface opposite to the surface (A); and a step (2) of irradiating a predetermined position in a surface (B), located in the opposite side to the surface (A), of the metal-clad laminated sheet with a laser to provide a via hole leading to the metal foil in a surface opposite to the surface (B).
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 7, 2021
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Kazuaki Kawashita, Takaaki Ogashiwa, Syunsuke Hirano, Yoshihiro Kato
  • Patent number: 11195750
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Tawiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Patent number: 11191165
    Abstract: The present disclosure relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 30, 2021
    Assignee: ETHERTRONICS, INC.
    Inventors: Seung Hyuk Choi, Hyun Jun Hong, Tae Wook Kim, Cheong Ho Ryu, Young Sang Kim, Sung Jun Kim
  • Patent number: 11171034
    Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 9, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Gouraud, Delia Ristoiu
  • Patent number: 11168400
    Abstract: At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: November 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Brian Michael Erwin, Chris Muzzy, Thomas Weiss
  • Patent number: 11058002
    Abstract: A method for producing a wired circuit board, the method including the steps of: a first step of providing an insulating layer having an opening penetrating in the thickness direction at one side surface in the thickness direction of the metal plate, a second step of providing a first barrier layer at one side surface in the thickness direction of the metal plate exposed from the opening by plating, a third step of providing a second barrier layer continuously at one side in the thickness direction of the first barrier layer and an inner surface of the insulating layer facing the opening, a fourth step of providing a conductor layer so as to contact the second barrier layer, and a fifth step of removing the metal plate by etching.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 6, 2021
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Hayato Takakura, Masaki Ito, Yoshihiro Kawamura, Shuichi Wakaki
  • Patent number: 10978383
    Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 13, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa
  • Patent number: 10968523
    Abstract: A method to partially decrease a reflectivity of a region on a mirror platform includes isolating the region on a surface of the mirror platform and removing a first material from the surface of the mirror platform within the region. The reflectivity of the mirror platform is decreased within the region.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 6, 2021
    Assignee: ELECTRIC MIRROR, LLC
    Inventors: James V. Mischel, Jr., James V. Mischel, Sr.
  • Patent number: 10971393
    Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventor: Kevin Lin
  • Patent number: 10964552
    Abstract: A method for producing a laminate that includes at least the following: providing a first intermediate laminate comprising a carrier substrate including a support therein and a peelable metal layer formed on at least one surface of the carrier substrate; forming, in a section not serving as a product of the first intermediate laminate, a first hole reaching at least the support in the carrier substrate from a surface of the first intermediate laminate, to prepare a second intermediate laminate with the first hole; stacking and disposing on the surface where the first hole is formed of the second intermediate laminate, an insulating material and a metal foil in this order when viewed from the surface; and pressurizing the second intermediate laminate, the insulating material and the metal foil in the stacking direction thereof with heating, to prepare a third intermediate laminate where the first hole is filled with the insulating material; and performing treatment with a chemical agent on the third intermedia
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 30, 2021
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Yoshihiro Kato, Takaaki Ogashiwa, Yoichi Nakajima, Takaaki Ichikawa, Kazuaki Kawashita
  • Patent number: 10886278
    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias individually having an upper horizontal perimeter. The conductive vias individually have an upper horizontal perimeter. Masking material is formed directly above the conductive vias. An opening is formed in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Sanh D. Tang
  • Patent number: 10856424
    Abstract: A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Sri Ranga Sai Boyapati, Amanda E. Schuckman, Sashi S. Kandanur, Srinivas Pietambaram, Mark Hlad, Kristof Darmawikarta
  • Patent number: 10852614
    Abstract: The present disclosure is directed to a method of forming a layered structure including a nanostructure layer having nanostructures. The method includes: forming a coating layer on the surface of the nanostructure layer, reflowing the coating layer, depositing one or more conductive plugs into the coating layer, and hardening the coating layer. The one or more conductive plugs each has a first portion configured to be placed in electrical communication with the nanostructure layer and a second portion not covered by the coating layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Paul Mansky, Kalpesh Biyani
  • Patent number: 10840101
    Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 17, 2020
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Mark J. Willey
  • Patent number: 10817641
    Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree. The approach captures users' design intent about the topology, and the routing system adhere to that topology intent throughout the layout process.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 27, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chung-Do Yang, Hoi-Kuen Lam, John Mario Wilkosz
  • Patent number: 10743424
    Abstract: The present invention provides a method for manufacturing a flexible array substrate. The method includes, first, successively forming an adhesive layer, a passivation layer, a back-side drive circuit, a planarization layer, a flexible backing plate, and a front-side drive circuit and a display circuit, in a stacked arrangement, on a rigid support plate and then peeling off the rigid support plate and the adhesive layer to form a flexible array substrate having a double-sided circuit structure. The entire process requires no steps of peeling, reversing, and then re-attaching of the flexible backing plate so that it is possible to avoid the issues of poor flatness and low yield resulting from improper or wrongful re-attachment of the flexible backing plate and thus, fabrication difficulty of a flexible array substrate having a double-sided circuit structure may be lowered down to thereby improve fabrication yield of the flexible array substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 11, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lixuan Chen, Yungjui Lee
  • Patent number: 10642152
    Abstract: A method of designing a feature guiding template for guiding self-assembly of block copolymer to form at least two features in a design layout for lithography, the feature guiding template including at least two portions joined by a bottleneck, the method including determining a characteristic of the feature guiding template based on at least a function of geometry of the feature guiding template including a value of a first width of at least one of the portions, a value of a second width of the bottleneck, or a value based on both the first width and the second width.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 5, 2020
    Assignee: ASML Netherlands B.V
    Inventors: Sander Frederik Wuister, Davide Ambesi
  • Patent number: 10559982
    Abstract: Various techniques are described herein for efficiently transmitting and receiving wireless power and/or data signals. In one example, a transmitter includes multiple antennas, a dielectric material in proximity to the multiple antennas, and multiple scattering elements embedded in the dielectric material. One or more of the multiple scattering elements are configured to be excited by one or more signals emitted by the multiple antennas.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 11, 2020
    Assignee: Ossia Inc.
    Inventors: Hatem Zeine, Siamak Ebadi, Douglas Wayne Williams
  • Patent number: 10553672
    Abstract: A metal-insulator-metal (MIM) capacitor includes a semiconductor substrate and a capacitor device. The capacitor device includes a first conductor upright on the semiconductor substrate, a second conductor upright on the semiconductor substrate, and an insulator disposed used for insulating the first conductor from the second conductor. In a method for fabricating the capacitor device, a mask including a test line pattern and a capacitor pattern with a first trench pattern and a second trench pattern is used to form a test line and the first conductor and the second conductor of the capacitor device, thereby decreasing the cost of for fabricating the MIM capacitor.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yan-Jhih Huang, Chun-Yuan Hsu, Chien-Chung Chen, Yung-Hsieh Lin
  • Patent number: 10453886
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 10429892
    Abstract: An electronic device may have a housing formed from a rigid material such as metal or fiber-composite material. A display such as an organic light-emitting diode display may be attached to a planar wall portion of the housing using a layer of adhesive. A display cover layer may be attached to the organic light-emitting diode with a layer of adhesive. The adhesive layers may be rigid to enhance device stiffness. The housing may have curved sidewall portions that extend outwardly from the planar wall portion to enhance stiffness. The organic light-emitting diode display may have an array of pixels formed from thin-film transistor circuitry. The thin-film transistor circuitry may be formed on a substrate such as a glass substrate that is attached to the planar wall portion. The organic light-emitting diode display may have a circular polarizer that is attached to the thin-film transistor circuitry.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 1, 2019
    Assignee: Apple Inc.
    Inventors: Dinesh C. Mathew, Adam T. Garelli, Mikael M. Silvanto
  • Patent number: 10366951
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravindranath V. Mahajan
  • Patent number: 10362687
    Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 23, 2019
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Dale Kersten
  • Patent number: 10340205
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Patent number: 10301738
    Abstract: Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: May 28, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan L. Buckalew, Steven T. Mayer, Thomas A. Ponnuswamy, Robert Rash, Brian Paul Blackman, Doug Higley
  • Patent number: 10283445
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 7, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10264185
    Abstract: The electronic apparatus includes a first circuit board on which a circuit mounted, a second circuit board arranged close to the circuit on the first circuit board, and a conductive terminal, which is in contact with a ground pattern on the first circuit board, and is arranged at a location between the circuit and the second circuit board so as to extend over the circuit.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: April 16, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Jun Hirabayashi
  • Patent number: 10236257
    Abstract: A method for constructing an advance conductor structure is described. A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10178781
    Abstract: An electronic device including: an electronic circuit accommodated in a circuit housing having a first thermal expansion coefficient, and a molded body which surrounds the circuit housing, the body having a second thermal expansion coefficient that differs from the first thermal expansion coefficient. The molded body is fixed to the circuit housing at least at two different mutually spaced fixing points on the circuit housing.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: January 8, 2019
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Jakob Schillinger, Ulrich Schrader, Dietmar Huber
  • Patent number: 10167559
    Abstract: A method for manufacturing a gap device includes forming a template structure on a substrate, depositing an active material layer on the substrate and on the template structure, wherein the active material layer covers at least top and side surfaces of the template structure, planarizing the active material layer, and selectively removing the template structure with respect to the active material layer and the substrate.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emanuel Loertscher, Marcel Mayor, Gabriel Fernando Puebla Hellman
  • Patent number: 10169504
    Abstract: A computer-implemented structure for optimizing a route for power supply and heat dissipation in a multilayer chip. The method includes: setting a heat conductive thermal value for the multilayer chip by way of density, preparing a substrate that contains silicon where a wiring layer is formed facing the upper surface side of the multilayer chip, setting the power from the wiring layer of the substrate that uses silicon, manipulating the value of the power supply, and manipulating the heat conductive thermal value based on density. Both apparatus's include an organic substrate, a multilayer chip, a substrate containing silicon, a wiring layer, and a heat dissipater, wherein the components are configured to perform the steps of the above method. The method of configuring an apparatus ensures that all the multilayer chips are stored in the concave part of the organic substrate.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventor: Keiji Matsumoto
  • Patent number: 10147637
    Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 4, 2018
    Assignee: IMEC vzw
    Inventors: Youssef Drissi, Ryan Ryoung han Kim, Stephane Lariviere, Praveen Raghavan, Darko Trivkovic
  • Patent number: 10144185
    Abstract: Methods, systems and apparatuses are disclosed for making and post-processing a 3-D printed object for laminate-forming tooling, and components made using post-processed 3-D printed laminate-forming tooling.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: December 4, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Benjamin J. Stephenson, Scott K Frankenbery, William H Ingram, Jr., William S. Hollensteiner
  • Patent number: 10138558
    Abstract: The ampholytic surfactants show the nature of anionic surfactants in an alkaline region and the nature of cationic surfactants in an acidic region. As described below, the pretreatment solution of the present invention may preferably indicate alkalinity of pH 8.5 or higher, and therefore, it exhibits the nature of cationic surfactants by the use of ampholytic surfactants. As the ampholytic surfactants, those disclosed in JP 2011-228517 A can be used.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: November 27, 2018
    Assignee: C. UYEMURA & CO., LTD.
    Inventors: Yoshikazu Saijo, Hisamitsu Yamamoto, Tetsuji Ishida, Takuya Komeda, Masayuki Utsumi