Abstract: Methods for adhering polyimide dielectric materials to copper-, titanium-, aluminum-, or copper-and-titanium-containing portions of a substrate are described. The methods include the steps of applying adhesion promoter to a clean surface of the substrate, and curing the adhesion promoter. SPIE varnish is applied over the cured adhesion promoter, and is itself cured. A further layer of adhesion promoter is applied over the cured SPIE varnish, and is cured. The polyimide dielectric material is then laminated to the adhesion promoter. Cleaning of the copper-containing substrate portions is performed by etching with etchant including cupric chloride, cleaning of the titanium-containing substrate portions is performed with etchant including HF, and cleaning of copper- and titanium-containing portions is performed by HF etching followed by cupric chloride etching. Aluminum-containing portions of the substrate are not etched.

Abstract: A printed wiring board, particularly, an interposer 20 for a chip scale package, comprising an outer insulator layer 22 having outer electrodes 31, a conductor layer 21, and an inner insulator layer 23 having inner electrodes 27, the electrodes 31 and/or 27 having been formed by electroplating using, as a negative electrode, a metal plate 32 that has been provided on the outer insulator layer 22 and removed after the electroplating. Having no plating leads, the printed wiring board has the electrodes in an orderly array at a fine pitch and a high density.

Abstract: In the method, a cap wafer surface is lithographically etched at time of fabrication, so that a raised ridge onto which bonding material is placed is formed near a perimeter of a desired cavity region. This is done in order to reduce the bonding area between the cap wafer and electronic device wafers, so as to provide a better defined standoff. In another aspect of the method, the cap wager surface is lithographically etched to form recesses or trenches near the perimeter of a cavity region, each recess being filled with a sealing material, and polished if necessary to be flush with the cap wafer surface. Thereafter, the cap wafer surface is etched so that the filled recesses become the raised ridges which are used to bond a cap wafer to an electronic device wafer.

Abstract: There is provided a method for producing a metal/ceramic bonding article, the method including the steps of: bonding a metal plate 12 of an alloy containing copper and nickel directly to at least one side of a ceramic substrate 10; applying a resist 14 on a predetermined portion of the metal plate 12 to remove an undesired portion of the metal plate 12 by etching; and removing the resist 14 to form a pattern having a predetermined shape of the alloy on the ceramic substrate 10. According to this method, it is possible to reduce the displacement failure of parts to improve productivity and to prevent bonding failure during the mounting of a semiconductor device or the like thereon.

Abstract: A method of manufacturing a thin film piezoelectric element, wherein main electrode layer, piezoelectric thin film, and opposed electrode layer respectively having specified shapes are first formed on first substrate and second substrate, and after that, the opposed electrodes are opposed and bonded to each other, and insulating resin layer is formed over the peripheral portion thereof, and then the second substrate is removed, the insulating resin layer is etched, and connecting electrode pad is formed, and finally, the first substrate is removed to obtain a completely separated thin film piezoelectric element. By this method, it is possible to improve the reproducibility of shapes and to prevent trouble such as shorting between the electrodes which hold the piezoelectric thin film, thereby making it possible to provide a thin film piezoelectric element that may assure high yield without variation in piezoelectric characteristics, and its manufacturing method.

Abstract: A method for reducing wafer surface scratching in a metal CMP process including providing a semiconductor wafer having a process surface comprising a blanket deposited metal layer; dry etching in an etchback process comprising a fluorine containing etching chemistry to remove at least a portion of the metal layer forming a metal and fluorine containing etching residue at the process surface; cleaning the process surface with a hydrofluoric acid (HF) containing cleaning solution; and carrying out a subsequent metal chemical mechanical polishing (CMP) process.

Abstract: The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides of the via holes to a prescribed thickness, forming an anti-reflection layer on the via holes and the insulating layer, forming a mask pattern for trench etching on the insulating layer on which the anti-reflection layer is formed, and forming a damascene pattern using the mask pattern for trench etching. CD uniformity is improved by minimizing change of the critical dimension of the damascene pattern, thereby increasing reliability of the semiconductor device.

Abstract: In a process using a hot phosphoric acid etchant (12) to etch silicon nitride on a semiconductor wafer (15) submerged in a tank (11) of the etchant (12), a recirculating path is established for the etchant (12). A porous filter (35) is coated with silicon nitride and installed in the recirculating path. As the etchant (12) in the recirculating path flows through the porous filter (35), the silicon nitride on the porous filter (35) dissolves into the etchant (12). In the tank (11), the silicon nitride dissolved in the etchant (12) significantly suppresses the etch of silicon dioxide on the semiconductor wafer (15), thereby enhancing the etch selectivity of the process. Monitoring and maintaining the concentration of the silicon nitride in the etchant (12) stabilizes the etch selectivity of the process.

Abstract: An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1).providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure;(2).applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line;(3).washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4).providing means for preventing Cu reduction reactions on the Cu wiring line.

Abstract: Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include etching away unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.

Abstract: A method of manufacturing a wireless suspension blank wherein three-layered laminate formed of a metallic layer having a spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used. The laminate used is a laminate in which an insulating layer is formed of a core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. The metallic layer and the conductive layer are processed by the photo etching method. The insulating layer is processed by the wet etching method.

Abstract: A novel modular muffle etch injector assembly for use in a gas blanketed down-flow chemical vapor deposition apparatus of the type having a muffle and a modular gas injector assembly for introducing chemical vapors into a deposition chamber, the muffle being adapted for receiving and supporting the gas injector assembly, wherein deposition material residue collects on a lower surface of the muffle. The etch injector assembly of the present invention comprises an etch chamber having vertical sidewalls, a closed top end and an open bottom end, a supply mechanism for introducing a liquid etchant into the etch chamber, and a sealing device disposed along the open end of the etch chamber for providing a seal between the etch chamber and the lower surface of the muffle to confine the etchant to the etch chamber. The etch injector assembly preferably also includes an exhaust means for removing chemical vapors from the etch chamber.

Abstract: An etching treatment agent which can etch insulating film with high speeds without damaging the resist pattern, provide realistic throughput when the insulting film etching process in the semiconductor manufacturing process is replaced with the single wafer processing etching treatment method, and prevent roughness on the surface of the semiconductor after etching.

Abstract: It is disclosed a method of forming fine patterns comprising: covering a substrate having photoresist patterns thereon made of a photoresist composition which is sensitive to high energy light rays with wavelength of 200 nm or shorter or electron beam radiation, with an over-coating agent for forming fine patterns, applying heat treatment to cause thermal shrinkage of the over-coating agent so that the spacing between adjacent photoresist patterns is lessened by the resulting thermal shrinking action, and removing the over-coating agent substantially completely. The present invention provides a method of forming fine patterns whereby fine patterns having pattern width or diameter of 100 nm or shorter and being excellent in uniformity (in-plane uniformity), etc. can be formed by ultrafine processing using high energy light rays with wavelength of 200 nm or shorter or electron beams.

Abstract: An evaporation mask, a method of manufacturing an organic electroluminescent device using the evaporation mask, and an organic electroluminescent device manufactured by the method are provided. The evaporation mask is formed of a thin film and is drawn taut by application of tension. The evaporation mask includes at least one mask unit, the mask unit including a plurality of main apertures, and a plurality of first dummy apertures formed adjacent to outermost ones of the main apertures in a direction in which tension is applied to the evaporation mask.

Abstract: A method for making a multi-layer circuit board 116 having apertures 96, 98 which may be selectively and electrically isolated from electrically grounded member 46 and further having selectively formed air bridges and/or crossover members 104 which are structurally supported by material 112. Each of the apertures 96, 98 selectively receives electrically conductive material 114.

Abstract: A method of fabricating a semiconductor package is disclosed in which a first Ni—Au plating is formed on a bonding pad for connection with a semiconductor chip, without a mechanical process or a masking operation. The method applies a copper plating on a through bore and the bonding pad, where the copper plated layer formed on the bonding pad is selectively removed, and then a second Ni—Au plating is formed on the bonding pad and a ball pad.

Abstract: In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.

Abstract: Silicon substrates having Si—H bonds are chemically modified using a fluorinated olefin having the formula: 1

Abstract: A variety of etching bath-based demetallizing processes for making various products involve immersing a web of metal-containing material in a bath of aqueous etchant. The metal-containing material is protected by a pattern of etch-resistant material during the demetallizating process to form functional features having a function in the product in the metal-containing material when the web has been demetallized. The metal-containing material is also protected by a pattern of etch-resistant material over areas of the metal-containing material that serve no function in the product, but rather function in one or more ways to improve the chemical milling process, such as, for example, by extending the etchant bath life, preventing excessive heat generation in the etchant bath, maintaining the etchant bath stable and controllable, increasing web rigidity, and imparting predetermined flex characteristics to the web.

Abstract: A PC board micro hole processing method using plasma technique to etch the substrate of the PC board, and then using chemical etching technique to remove residual material such as glass fibers.

Abstract: The invention is a method of introducing porous membranes into MEMS elements by supporting the membranes by frames to form an heterostructure. This is achieved by attaching to a structured or porous substrate one or more monolithically fabricated frames and membranes. Having membranes disposed on frames enables them to be batch processed and facilitates separation, handling and mounting within MEMS or nanofluidic systems. Applications include, but are not limited to, filters for gases or liquids, electron transmissive windows and scanning electron microscopy (SEM) accessible arrays of nanotest tubes containing liquid phases and other sample states. The invention includes the apparatus made by the method.

Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes an electrical conductor thermally coupled to a cold plate and a thermoelement electrically coupled to the electrical conductor. The thermoelement is constructed from a thermoelectric material and has a plurality of tips through which the thermoelement is electrically coupled to the electrical conductor. The thermoelectric tips provide a low resistive connection while minimizing thermal conduction between the electrical conductor and the thermoelement.

Abstract: A manufacturing method of an MR thin-film magnetic head with an MR film and lead conductors overlapping each other, includes a step of depositing a conductor layer on at least the magnetoresistive effect film, a step of forming a cap layer patterned on the deposited conductor layer, and a step of dry-etching the deposited conductor layer through a mask of the patterned cap layer using an Ar gas and an O2 gas, an O2 gas or a N2 gas so as to pattern the deposited conductor film to form the lead conductors.

Abstract: The present invention discloses a method and apparatus for the directed formation of a re-entrant micro-jet formed upon the collapse of a working cavitation bubble formed proximate to a work surface. A target bubble, formed between the work surface and the working cavitation bubble, is utilized to direct the re-entrant micro-jet to the work surface.

Abstract: A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of the die attach pad. A plurality of wire bonds connect the die attach pad and the contact pads. An overmold covers the semiconductor die and all except one surface of the at least one row of contact pads and the die attach pad.

Abstract: Disclosed are a method for preparing a high performance BGA board containing a plurality of printed circuit boards in which a conductor circuit, a bonding pad electrically connected to a semiconductor chip, and an inner hole for mounting a semiconductor chip are formed, by primary- and secondary-laminating a plurality of boards. The present invention enjoys advantages in that contamination due to an outer layer surface treatment of the board laminate can be prevented, and a process for preventing a contamination of an inner hole can be omitted, and also a defective proportion can be reduced remarkably in comparison with prior arts by applying a pressure uniformly during a secondary lamination. Furthermore, a BGA board according to the invention has an ideal ball pitch and multi-fins, excellent electrical and thermal properties, also can be applied in the case of high current, and can be easily mounted on a chip.

Abstract: Improved methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer or a dielectric film on a substrate, and then forming a conductive laminate on the release layer or the dielectric film. The conductive laminate may be easily separated by the substrate to eventually form a flexible circuit structure.

Abstract: A sheet including lead regions with conductors and a main region surrounding the lead regions is formed on the front surface of a microelectronic element such as a wafer, or assembled thereto, so that the conductors are connected to contacts on the microelectronic element. After the sheet is in place, the sheet is eroded to form gaps partially bounding the lead regions, leaving tip ends of the lead regions moveable with respect to the main region. The tip ends of the lead regions, or the main region, is lifted away from the microelectronic element, thus bending the tip ends away from the main region. Because the gaps are not formed until after the conductors are connected to the contacts, the connecting step is simplified.

Abstract: A microfluidic delivery system substrate is coated with ultra-nanocrystalline diamond (UNCD) or with a thin ceramic film, such as alumina or zirconia, that is applied by ion-beam assisted deposition; assuring that the device is impermeably sealed, to prevent the substrate from being dissolved by hostile environments and to protect the molecules from premature release or undesired reaction with hostile environments. The UNCD coating may be selectively patterned by doping to create electrically conductive areas that can be used as an electrically activated release mechanism for drug delivery. The UNCD coating provides a conformal coating, of approximately uniform thickness, around sharp corners and on high aspect-ratio parts, assuring impermeability and strength despite the need to coat difficult shapes. The microfluidic delivery system is suitable for use as an iontophoresis device, for transport of molecule, having a substrate, a reservoir in the substrate for containing the molecules.

Abstract: An integrated lead suspension is formed from a laminate of three materials in a variety of configurations having from three to five layers. The materials are stainless steel, polyimide and copper. Each layer is essentially homogeneous, but may be formed with one or more holes or voids prior to the formation of the laminate. After the copper layer is etched to form a tab which overhangs the steel layer, the suspension is welded to a load beam. The load beam prevents the downward motion of the suspension. The tab acts as a flexure motion limiter for upward motion of the suspension. The voids allow a precise amount of polyimide undercut between the steel and copper layers which otherwise could not be achieved.

Abstract: A process and composition for treating a metal surface to increase its surface roughness for subsequent adhesion to a polymer layer are disclosed. The composition includes hydrogen peroxide, inorganic acid, at least two corrosion inhibitors.

Abstract: A method and an apparatus for implementing the method produces at least one depression as a microstructure, in particular, a deep trench, in a semiconductor material, in particular, during the production of DRAMs and heats an area of at least one depression in the semiconductor material during an etching step, at least from time to time and/or locally. Such a configuration makes it possible to produce depressions in semiconductor materials efficiently, in particular, those with a high aspect ratio.

Abstract: Packaging of micromechanical and microelectromechanical devices is carried out by mechanical couplers for connecting pairs or arrays of optical fibers in end-to-end alignment. In another embodiment, a coupler interconnects one or more optical components on a substrate. The electrical components may be active elements such as light sources or light sensors, while the optical components may be waveguides. The fibers are secured in a coupler block, and a substrate carrying the light detector or light source is mounted on or in the block and is secured in alignment with the fibers. The fibers are removably secured within the block by spring fingers.

Abstract: A continuous process for forming multilayer circuit structures which includes applying and curing a film forming polymer onto the matte side of a copper foil. The opposite (shiny) side of the foil is optionally but preferably cleaned, and applied with a photoresist which is then optionally but preferably dried. The photoresist is exposed, and developed to remove the nonimage areas but leave the image areas. The foil under the removed nonimage area is then etched to form a copper pattern, and the remaining photoresist is optionally but preferably removed. The foil is then cut into sections, and then optionally but preferably punched with registration holes. The copper pattern is then optionally but preferably treated with a bond enhancing treatment, optionally but preferably inspected for defects, and laminated onto a substrate to form a multilayered circuit structure.

Abstract: A method is provided for forming a patterned layer of resistive material in electrical contact with a layer of electrically conducting material. A three-layer structure is formed which comprises a metal conductive layer, an intermediate layer formed of material which is degradable by a chemical etchant, and a layer of resistive material of sufficient porosity such that the chemical etchant for said intermediate layer may seep through the resistive material and chemically degrade said intermediate layer so that the resistive material may be ablated from said conductive layer wherever the intermediate layer is chemically degraded. A patterned photoresist layer is formed on the resistive material layer. The resistive material layer is exposed to the chemical etchant for said intermediate layer so that the etchant seeps through the porous resistive material layer and degrades the intermediate layer. Then, portions of the resistive material layer are ablated away wherever the intermediate layer has been degraded.

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.

Abstract: Adhesive film useful for the production of semiconductor devices is produced from a siloxane-modified polyamideimide resin composition, comprising 100 parts by weight of a siloxane-modified polyamideimide resin and 1 to 200 parts by weight of a thermosetting resin ingredient.

Abstract: The invention pertains to a new type of process for the manufacture of substrates with textured metalizations and holding and fastening elements for use in this process.

Abstract: A process for the etching of multiple layers of at least two different metals comprisies: forming a resist pattern over a first layer of metal, said resist pattern having a pattern of openings therein, applying a first etch solution onto said resist pattern so that at least some etch solution contacts exposed areas of the first layer of metal, etching away the majority of the depth of the first metal in exposed areas of metal in the first layer of metal, applying a second etch solution onto the resist pattern the second etch solution having a rate of etch towards the first metal as compared to the first etch solution that is at least 20% less than the millimeter/minute rate of etch of the first etch solution at the same etch solution temperature, removing the second etch solution from said resist pattern after at least the first metal layer has been etched sufficiently to expose areas of a second metal layer underlying the first metal layer by forming an etched first metal layer, and applying a third etch so

Abstract: A method for forming sets of tri-metal material involving the use of cladding mills. When multiple sets of tri-metal material are formed, the outside surfaces of each set is prepared by oxidation to prevent each set from adhering to the set above or below. An alternative to oxidation is to provide a removable layer on the outside surface of the tri-metal material. Alternatively bonding materials may be used on the intermediate surfaces; such bonding materials can be selected from a group consisting of tin, nickel, titanium, chromium, silver and zinc.

Abstract: A method of making a printed circuit board whereby a fine wiring pattern can be formed. A through hole is formed in a substrate, both surfaces of the substrate being covered with copper foil. The substrate is treated with a catalyst and plated with copper. The through hole is filled with an insulating material, and the copper layer on the substrate is etched so that the catalyst layer is not exposed, leaving a thinned copper layer. Then, the substrate surfaces are ground and leveled by removing any projecting insulating material. Thereafter, another copper layer is deposited on the surface of the substrate, including surface regions on the fill material and is circuitized to form a wiring pattern. Since the catalyst layer is not exposed when the copper layer on the substrate is thinned, a fine wiring pattern can be obtained without the problem of subsequent peeling of the wiring conductors, or the entrapment of air.

Abstract: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.

Abstract: A multilayer circuit board having air bridge crossover structures and an additive method for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit.

Abstract: A method for making multi-layer electronic circuit board including a pre-circuit assembly 12 and a ground layer 14 which are automatically aligned and bonded together by use of solder material or deposits 26, 28.

Abstract: There are provided a treatment solution for reducing a copper oxide formed on the surface of copper to copper, wherein dimethylamine borane is contained in an amount of 0.3 to 2.0 g/L and the relationship y≧0.232x−0.185 holds between the concentration y (g/L) of dimethylamine borane and an area x (dm2/L) to be treated per unit solution amount, and a treatment method for reducing a copper oxide formed on the surface of a copper material to copper by dipping the copper material in the treatment solution as described above, wherein the addition of dimethylamine borane to water is carried out within 10 minutes before the dipping of the copper material or after the dipping of the copper material.

Abstract: In the method for manufacturing a semiconductor device according to the present invention, after forming a BPSG film 110 on a silicon substrate 100, a preparatory hole 120 that reaches a specific depth and has a larger diameter than a contact hole 118 is formed at a position where the contact hole 118 (see FIG. 4) is to be formed at the BPSG film 110. Thus, polysilicon side walls 114 (see FIG. 4) formed at side portions of a polysilicon film 112 (see FIG. 4) are also formed at the side walls of the preparatory hole 120. As a result, the contact hole 118 (see FIG. 4) free of shape defects can be formed by using an etching mask 116 (see FIG. 4) constituted of the polysilicon film 112 and the polysilicon side walls 114. This structure prevents defects related to the shape of the hole and reduces electrical defects such as shorting.

Abstract: A process for the formation of an article having multiple electrical circuits comprises: providing a first sub-element comprising in sequence a first metal layer of copper in electrical contact with a second metal layer of aluminum in electrical contact with a third metal layer of copper; etching an electrical circuit design in the first metal layer and in a separate etch step, etching away at least 10%, but less than 100% of the second metal layer to provide electrical connections between the first metal layer and the third metal layer; etching an electrical circuit design into the third metal layer; adhering an etched surface comprising the circuit design of the first or third metal layer to a first surface of a support layer to form a circuit board. The process may etch the first and third metal layers simultaneously or sequentially.

Abstract: A multilayer rigid flex printed circuit board wherein the board laminate comprises a basestock composite containing a flexible core, formed by laminating a first conductive layer to a flexible insulator layer, a second insulator layer affixed to the basestock, said second insulator layer having a cutout region proximate to the flexible core of the basestock composite to expose a portion of said first conducting layer on said flexible core, a second conductive layer attached to said second insulator layer said second conductive layer having a cutout region proximate to the flexible core of the basestock composite, and a photo-imageable soldermask applied to the exposed portion said first conducting layer, and to the second conductive layer, wherein said photoimageable soldermask allows for photo definition of openings on the conductive layers to which it is applied.