Adhesive Or Autogenous Bonding Of Self-sustaining Preforms (e.g., Prefabricated Base, Etc.) Patents (Class 216/20)
-
Patent number: 5858255Abstract: A method for manufacturing printed circuit plates, which includes laminating an aluminum rolled leaf on a surface of an insulator base, forming an etching resist coat film on the surface of the aluminum rolled leaf, and then dissolving and removing an unnecessary aluminum leaf in the non-resist area with an etching liquid. The etching liquid is an aqueous solution containing (1) 0.1 to 15 mol/liter of acid of an amine hydrofluoride and (2) 0.02 to 10 mol/liter of a hydrogen peroxide, wherein the amine is one of an aliphatic amine having 12 carbon atoms or less and a heterocyclic amine, the amine having no other acid group or basic group than amino group, the etching liquid having a pH within the range from 4 to 9, wherein the hydrogen peroxide oxidizes aluminum into an aluminum oxide which is dissolved by the amine hydrofluoride.Type: GrantFiled: October 20, 1994Date of Patent: January 12, 1999Assignees: Sharp Kabushiki Kaisha, Oogi Chemical Industry Co., Ltd.Inventors: Ichiro Kohara, Masakatu Takaishi, Hideaki Ishitobi, Kiyoshi Kondo, Hiroya Ito
-
Patent number: 5839193Abstract: Laminate structures for attachment to a head suspension assembly in a hard disk drive. The laminate structures include a spring metal layer, a conductive layer, and an intermediate insulator/adhesive layer. The conductive layer can act as an interconnect assembly, as a gimbal, and as a spring region. The method of manufacture of the laminate structures incorporates manufacture of an interconnect assembly into the manufacture of spring structures such as a load beam or a gimbal. The laminate structures are manufactured by etching the layers from the outside in, using other layers as etching masks. Unique configurations are possible where either or both metal layers can be discontinuous, thanks to the manufacturing support of the second layer. The second layer can also be shaped into a plurality of panels, thus freeing the metal layers to act as the spring elements.Type: GrantFiled: May 25, 1994Date of Patent: November 24, 1998Assignee: Hutchinson Technology IncorporatedInventors: Jeffry S. Bennin, Todd W. Boucher, James H. Dettmann, Lloyd C. Goss, Gary E. Gustafson, Michael T. Hofflander, Brent D. Lien, Dean E. Myers
-
Patent number: 5837153Abstract: A method and system for providing specialized contacts for electronic information on a smart card in the pattern of a source identifier and such that a machine may contact and read the information upon placement of the card in a reading device. The contact points for reading information on the card are formed by etching a substrate attached to the logic element of the smart card. The etching allows both the foreground and the background of an image, in two selected colors, to be included within the contact area of the smart card, with the foreground constituting the conductor and the background the resist.Type: GrantFiled: January 15, 1997Date of Patent: November 17, 1998Inventor: Joseph C. Kawan
-
Patent number: 5837155Abstract: An insulating resin composition for the build-up of multilayer circuits by the procedure of copper foil lamination and a method for the production of a multilayer printed circuit board by the use of the insulating resin composition are disclosed. The insulating resin composition comprises at least one species of epoxy resin having a softening point of not more than 110.degree. C., a monomer or an oligomer possessing an unsaturated double bond, an epoxy resin curing agent, and a photopolymerization initiator. The insulating resin composition is applied to a printed circuit board throughout the entire area thereof so as to cover conductor patterns formed thereon and then irradiated with UV light. Subsequently a copper foil is superposed on the applied layer of the insulating resin composition on the printed circuit board by means of a heated pressure roller to effect lamination thereof.Type: GrantFiled: August 14, 1996Date of Patent: November 17, 1998Assignee: Taiyo Ink Manufacturing Co., Ltd.Inventors: Shoji Inagaki, Eiji Takehara
-
Patent number: 5822850Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.Type: GrantFiled: December 22, 1995Date of Patent: October 20, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
-
Patent number: 5800722Abstract: A multilayer printed wiring board wherein an inner-layer copper circuit is provided on one or both of the surfaces of an inner-layer substrate, and subsequent copper circuit is cumulatively provided through an insulating layer on the outside of the inner-layer copper circuit, characterized in that the inner-layer copper circuit has a cuprous oxide film formed on the surface thereof the insulating layer which remarkably facilitate the interlayer adhesion between the inner-layer copper circuit. This multilayer printed wiring board has high interlayer adhesiveness and moistureproofness without causing any haloing phenomena when soaked with an acidic solution.Type: GrantFiled: May 1, 1996Date of Patent: September 1, 1998Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Hiroaki Tsuyoshi, Tetsuro Sato
-
Patent number: 5798050Abstract: A process for fabrication of an electrically conductive adhesive film having a pattern of microscopic elongate metal particles which extend from one surface to the other to provide an interconnection between confronting conductive metal pads abutting the surface. The particles have sharp ends to penetrate the oxide coating on the conductive metal pads of an electronic module when force is applied to press the module against the film.Type: GrantFiled: July 17, 1997Date of Patent: August 25, 1998Assignee: International Business Machines CorporationInventors: Michael A. Gaynes, Jaynal A. Molla
-
Patent number: 5798014Abstract: A method for making multi-tier laminate substrates for electronic device packaging is provided wherein a spacing mechanism is used to protect the bond fingers of a trace on a lower tier of the laminated substrate when a milling bit is used to cut an opening above a die cavity in the multi-tier substrate.Type: GrantFiled: October 16, 1996Date of Patent: August 25, 1998Assignee: Hestia Technologies, Inc.Inventor: Patrick O. Weber
-
Patent number: 5792375Abstract: Two copper containing surfaces are bonded together by microetching at least one of the surfaces, followed by abutting the two surfaces together, and then laminating them at a temperature of at least about 300.degree. C. and below the decomposition temperature of the copper-containing surfaces, and at a pressure of at least about 1500 psi.Type: GrantFiled: February 28, 1997Date of Patent: August 11, 1998Assignee: International Business Machines CorporationInventor: Donald Seton Farquhar
-
Patent number: 5779921Abstract: The present invention relates to a process for metallizing features of an electronic component, where the metallized features, conductive pads, conductive traces, are coated and encapsulated with at least one metal layer and the features on the front side and the back side of the component have different thicknessesType: GrantFiled: November 8, 1996Date of Patent: July 14, 1998Assignee: W. L. Gore & Associates, Inc.Inventors: Randy E. Haslow, Donald G. Hutchins, Michael R. Leaf
-
Patent number: 5761802Abstract: A method for electrically interconnecting a first electrical conductor to a second electrical conductor through a via formed in an insulating layer disposed between the conductors. A refractory metal layer is formed over: an upper surface of the insulating layer; sidewalls of the insulating layer formed by the via; and, portions of the first electrical conductor exposed by the via. Gold is deposited on a portion of the refractory metal layer formed on the exposed portion of the first electrical conductor. The deposited gold has a planar surface and is preferably spaced from portions of the conductive layer disposed on the sidewalls of the insulating layer to provide an plating site. Additional gold is electroplated onto the electroplating site to fill the via to a level co-planar with the upper level of the insulating layer. A photoresist layer is formed over the co-planar surfaces of the insulating layer and the filled via.Type: GrantFiled: June 10, 1996Date of Patent: June 9, 1998Assignee: Raytheon CompanyInventor: Michelle A. Grigas
-
Patent number: 5746927Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.Type: GrantFiled: December 12, 1996Date of Patent: May 5, 1998Assignee: Fujitsu LimitedInventors: Kaoru Hashimoto, Tatuo Chiyonobu, Kyoichiro Kawano, Koji Watanabe, Masato Wakamura, Joe Yamaguchi
-
Patent number: 5741430Abstract: A method of electrically and mechanically bonding conductive surfaces with conductive adhesives, wherein at least one of the conductive surfaces is of the type upon which unstable oxides readily form. The conductive adhesives having a predetermined amount of conductive particles. The conductive particles having a rigidity at least as hard as the materials composing the conductive surfaces and any oxide formed thereon. The bonding method including the step of preparing the conductive surfaces so that a microscopically roughened oxide surface is formed thereon. The method further including the step of simultaneously applying a predetermined amount of heat and pressure to cure the conductive surface-conductive adhesive-conductive surface joint such that the conductive particles in the conductive adhesive pierce through the oxide to make direct contact with the conductive surfaces thereunder. The method controls the mechanical strength of the bond and the electrical characteristics of the bond joint.Type: GrantFiled: April 25, 1996Date of Patent: April 21, 1998Assignee: Lucent Technologies Inc.Inventors: Donald William Dahringer, Alan Michael Lyons
-
Patent number: 5738797Abstract: A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut.Type: GrantFiled: May 17, 1996Date of Patent: April 14, 1998Assignee: Ford Global Technologies, Inc.Inventors: Robert E. Belke, Jr., Michael G. Todd, Andrew Z. Glovatsky, Alice D. Zitzmann
-
Patent number: 5733467Abstract: A conductive paste compound for via hole filling includes a conductive filler at 80 to 92 weight percent with an average particle size of from 0.5 to 20 .mu.m and specific surface of from 0.1 to 1.5 m.sup.2 / g, a liquid epoxy resin at 4.5 to 20 weight percent containing 2 or more epoxy groups with room temperature viscosity of 15 Pa.sec or less, and a hardener at 0.5 to 5 weight percent, wherein the viscosity is 2,000 Pa.sec or less and the volatile amount is 2.0 weight percent or less. A filling paste and a printed circuit board with use thereof are provided which can conduct an inner-via-hole connection between electrode layers without using a through-hole plating technique. The conductive paste comprises a metallic particle such as copper, an epoxy resin, a hardener, and if necessary, a dispersant. The paste having low viscosity and low volatility under high shear is used to fill holes disposed in a laminated substrate.Type: GrantFiled: March 10, 1997Date of Patent: March 31, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kouji Kawakita, Seiichi Nakatani, Tatsuo Ogawa, Masatoshi Suehiro, Kouichi Iwaisako, Hideo Akiyama
-
Patent number: 5709805Abstract: A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.Type: GrantFiled: November 20, 1996Date of Patent: January 20, 1998Assignee: International Business Machines CorporationInventors: Charles Robert Davis, Thomas P. Gall
-
Patent number: 5690837Abstract: In a process for producing a multilayer printed circuit board comprising drilling holes for via holes in a composite film material containing at least a copper foil and an insulating half-cured adhesive layer, laminating the resulting film material on an innerlayer circuit substrate, ad electrically connecting an innerlayer circuit with an outer layer copper foil, when an adhesive resin flowed into the holes is roughened, or when a composite film material having a copper foil of less than 12 .mu.m thick formed on a carrier is used, or a special cushion material is further laminated on the laminate of the innerlayer circuit substrate and the film material, electrical connection reliability is enhanced and circuit density can be increased with easy steps.Type: GrantFiled: December 21, 1995Date of Patent: November 25, 1997Assignee: Hitachi Chemical Company, Ltd.Inventors: Akishi Nakaso, Koichi Tsuyama, Kazuhisa Otsuka, Haruo Ogino, Yoshihiro Tamura, Teiichi Inada, Kazunori Yamamoto, Akinari Kida, Atsushi Takahashi, Yoshiyuki Tsuru, Shigeharu Arike
-
Patent number: 5681485Abstract: A method of producing multilayer circuit boardschar comprising repeating a procedure comprising the steps of (1) laminating a photosensitive film composition shaped in a film form onto an insulating material carrying a conductor pattern formed thereon, (2) exposing the laminated photosensitive film composition to light through a negative type photomask, (3) dissolving the domains not irradiated in the above exposure step, (4) heat-curing the domains not dissolved in step (3), (5) forming a copper plating layer on the surface of the photosensitive film composition heat-cured in step (4) by electroless copper plating with or without further electroplating of copper, and (6) forming, on the plated copper layer formed in step (5), a photosensitive etch resist layer and subjecting said layer to light exposure through a photomask having a circuit pattern drawn thereon, developing and etching to thereby form a conductor pattern, said photosensitive film composition for lamination containing at least 50% by weight ofType: GrantFiled: November 30, 1995Date of Patent: October 28, 1997Assignee: Nippon Paint Co., Ltd.Inventors: Yoshikazu Yamagami, Shinji Seo, Akio Kashihara
-
Patent number: 5679194Abstract: A substantially continuous layer of a first metal such as copper is provided with strips of a second metal such as gold by selective electroplating of the second metal. A dielectric support layer is provided in contact with the first metal layer, and the first metal layer is etched to leave strips of the first metal contiguous with the strips of the second metal, thereby providing composite leads with the first and second metal strips connected in series. The process provides simple end economical methods of making microelectronic connection components with leads having a flexible, fatigue resistant lead potion formed from a precious metal.Type: GrantFiled: May 4, 1995Date of Patent: October 21, 1997Assignee: Tessera, Inc.Inventors: Joseph Fjelstad, John W. Smith
-
Patent number: 5679267Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A shallow etch stop trench (46) is first ion milled around each ceramic island on the front side and then filled with an etch step material (e.g. parylene 48). An optical coat (e.g transparent metal layer 54, transparent organic layer 56 and conductive metallic layer 58) is elevated above the etch step material by an elevation layer (e.g. polyimide 49). For some applications, it has been experimentally verified that there is no loss, and sometimes a measured increase, in optical efficiency when the optical coating is not planar in topology. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 86) containing a massive array of sensing circuits.Type: GrantFiled: January 16, 1996Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: James F. Belcher, Robert A. Owen
-
Patent number: 5679266Abstract: A method of assembling a printed circuit (PC) boards with ultrafine pitch components. The method comprises: attaching a coarse pitch components on the PC board; applying solvent to the thermal pads of the ultrafine pitch components; mounting a die-attach film on the thermal pads; curing the die-attach film; applying solvent to the die-attach film; forming component leads for the ultrafine pitch components; aligning the ultrafine pitch components to the solder pads; attaching the component leads to the solder pads and the ultrafine pitch components to the thermal pads. Other devices, systems and methods are also disclosed.Type: GrantFiled: January 16, 1996Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Vijay S. Darekar, Chris N. Thornton, John W. Krueger
-
Patent number: 5673484Abstract: A magnetic head suspension assembly, wherein a wiring member for connecting a magnetic head element with a read/write amplifier circuit board is integrally formed with the suspension for supporting the magnetic head element. The suspension is equipped integrally with a circuit wiring pattern via a flexible insulating base material. The flexible insulating base material is made as wide as the circuit wiring pattern. The top surface of the circuit wiring pattern has a surface protecting layer which is wider than the circuit wiring pattern.Type: GrantFiled: June 6, 1995Date of Patent: October 7, 1997Assignee: Nippon Mektron, Ltd.Inventors: Inaba Masaichi, Matsumoto Hirofumi, Tanaka Yasuyuki
-
Patent number: 5665650Abstract: Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.Type: GrantFiled: May 30, 1996Date of Patent: September 9, 1997Assignee: International Business Machines CorporationInventors: John Matthew Lauffer, Donald Herman Glatzel, David John Russell
-
Patent number: 5653892Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A front side optical coating (e.g. transparent metal layer 44, transparent organic layer 46 and conductive metallic layer 48) is elevated above the substrate between the ceramic islands. This allows additional material (e.g. polyimide 38) between the optical coating and the substrate above the regions where cavities are to be etched. Etching of the cavities (72) is performed from the back side of the substrate without damaging the front side optical coating. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 80) containing a massive array of sensing circuits.Type: GrantFiled: January 16, 1996Date of Patent: August 5, 1997Assignee: Texas Instruments IncorporatedInventors: James F. Belcher, Robert A. Owen
-
Patent number: 5645735Abstract: A method for manufacturing a head suspension including separately manufacturing a load beam and a set of traces. The traces are formed from a sheet of conductive material and include an elongated conductor portion and a gimbal portion. Portions of the traces which are configured to be mounted to the load beam are coated with dielectric before being mounted to the load beam. The gimbal portion of the traces provides both mechanical and electrical connections to the conductor portion.Type: GrantFiled: October 31, 1995Date of Patent: July 8, 1997Assignee: Hutchinson Technology IncorporatedInventors: Jeffry S. Bennin, Todd Boucher, Jeffrey W. Green, Gary E. Gustafson, Ryan Jurgenson, Brent D. Lien
-
Patent number: 5639389Abstract: A process for the production of printed circuit boards and film circuit boards includes providing a starting product with a layer of insulating material between layers of metal. Openings are formed at desired locations through the metal and, at selected ones of those openings, openings are formed through the insulating material by plasma etching or chemical etching. The result of this is back-etching leaving projecting webs of metal extending partly across the openings. The projecting edges are removed by subjecting all of the metal surfaces to etching or electrodeplating which also thins the metal layers. The resulting structure is then plated, adding reinforcing thickness to the thinned metal layers and coating the openings through the insulating material with metal, providing interracial connections between the metal layers. The resulting intermediate can then be formed into a circuit board by forming circuit patterns in the metal layers.Type: GrantFiled: February 16, 1995Date of Patent: June 17, 1997Assignee: Dyconex Patente AGInventors: Walter Schmidt, Marco Martinelli
-
Patent number: 5635334Abstract: The invention relates to an improved method for making a plasma display apparatus comprising a plurality of stripe-shaped electrodes arranged in a matrix, a dot-shaped discharge area or pixel area at each solid intersection between the stripe-shaped electrodes and a fluorescent film formed on each of the discharge areas and adapted to emit light when the fluorescent film is excited by ultraviolet rays from the corresponding discharge area wherein the improvement is fabricating a ridge on one of the substrates utilizing a negative-working or positive-working diffusion patterning process.Type: GrantFiled: March 1, 1995Date of Patent: June 3, 1997Assignee: E. I. Du Pont de Nemours and CompanyInventors: William Borland, Ryosuke Kuwada, Noboru Nishii, Carl B. Wang, Yasuo Yamamoto
-
Patent number: 5630948Abstract: Integrated conductor suspensions are fabricated by progressively etching a suspension shape in a preformed laminate of copper, and stainless steel adhering to an intermediate resin layer, including defining pairs of signal lines in the copper layer having exposed sides and top, and coating these exposed sides and top with an adherent layer of gold down to the resin layer against corrosion in ambient corrosive environments.Type: GrantFiled: November 21, 1995Date of Patent: May 20, 1997Assignee: Magnecomp Corp.Inventors: Susumu Ueda, Daniel Vera
-
Patent number: 5628919Abstract: A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.Type: GrantFiled: May 12, 1995Date of Patent: May 13, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiro Tomura, Yoshihiro Bessho, Yasuhiko Hakotani
-
Patent number: 5626771Abstract: A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first and second optical absorbencies being different from each other. A first layer of one of the organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of a different organic polymeric material with a different optical absorbency to the material in the first layer overlays the first layer.Type: GrantFiled: June 6, 1995Date of Patent: May 6, 1997Assignee: International Business Machines CorporationInventors: Charles R. Davis, Frank D. Egitto, Eugene R. Skarvinko
-
Patent number: 5626774Abstract: A permanent solder mask is applied to the surface of a printed circuit board using a copper foil carrier. The solder mask preferably is one or two layers of a thermosetting resin e.g. epoxy resin. Selected circuit features are exposed by etching away portions of the copper foil and removing the underlying thermosetting resin. Then, the remaining copper foil is removed, leaving the solder mask on the surface of the printed circuit board.Type: GrantFiled: December 11, 1995Date of Patent: May 6, 1997Assignee: AlliedSignal Inc.Inventor: James R. Paulus
-
Patent number: 5622586Abstract: Method of fabricating a device made of a thin diamond film having a thickness of less than 10 .mu.m which is difficult to handle. The method is initiated by forming a thin diamond film on a silicon substrate to a thickness of about 5 .mu.m by chemical vapor deposition. Then, paraffin is applied. The substrate is removed with hydrofluoric acid. Thus, the diamond film is retained on the paraffin that is made to act as a base. A required circuit is formed on the surface of the diamond film. Finally, the paraffin is removed. In this way, a device using the diamond film is completed. This structure can be used as a device for measuring thermal effect, using a thin diamond film. For example, the structure can be used for fabrication of a flowsensor.Type: GrantFiled: December 30, 1994Date of Patent: April 22, 1997Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Rimantas Vaitkus, Takashi Inushima, Masaya Kadono
-
Patent number: 5622588Abstract: A method is disclosed for making multi-tier laminate substrates for electronic device packaging including providing a first laminating layer and a second laminating layer, each having a trace on a first side. These layers are laminated with a spacer layer and dielectric layers. A window is made in each of the spacer and the dielectric layers. After laminating the layers together, vias are formed. Then an opening is made in the first laminating layer that corresponds to the window openings in order to produce a cavity in the laminated structure for placing an electronic device therein.Type: GrantFiled: February 2, 1995Date of Patent: April 22, 1997Assignee: Hestia Technologies, Inc.Inventor: Patrick O. Weber
-
Patent number: 5620933Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.Type: GrantFiled: May 19, 1995Date of Patent: April 15, 1997Assignee: Brooktree CorporationInventors: Christopher D. James, Henry S. Katzenstein
-
Patent number: 5609773Abstract: In a multilayer wiring board comprising a substrate on which two or more layers of wiring or insulation film are formed of different materials, for example, the wiring layer is processed so that the processed side faces of the board contour a stepped shape in the cross-sectional view of the board, whereby coverage of a film formed thereon can be improved. Specifically, first, insulation film 2 is formed on a substrate 1 and then, resistor film 3 and resistor electrode film 4 are continuously formed thereon to form a film of multiple structure. Mask 9 is formed thereon. Then, the layers is etched successively in the order of from the top layer and thereafter only the resistor electrode film 4 is further etched with an etching solution which selectively etches only the resistor electrode film 4 to form a stepwise patterned side face. Finally, the mask is removed and wiring electrode film 5 is formed.Type: GrantFiled: October 31, 1994Date of Patent: March 11, 1997Assignee: Hitachi, Ltd.Inventors: Mitsuru Usui, Tetsuya Watanabe
-
Patent number: 5597470Abstract: A method for providing a flexible lead for a microelectronic device. A lead such as nickel or a nickel alloy is provided in elongated strips on a base material such as copper, which in turn overlies a dielectric sheet. The base material is etched from beneath bond regions of the lead material strips and a cover layer of a bondable material such as gold selectively provided around the lead material strips. The lead material strips act as plating mandrels, and allow rapid deposition of the cover material. A detachment area may be provided in each lead so that the leads may be detached and displaced within a bonding window in the dielectric sheet for attachment to chip contacts.Type: GrantFiled: June 18, 1995Date of Patent: January 28, 1997Assignee: Tessera, Inc.Inventors: Konstantine Karavakis, Thomas H. DiStefano, Joseph Fjelstad
-
Patent number: 5597494Abstract: Disclosed herein is a method of manufacturing a multilayer ceramic electronic component by forming external electrodes on a pair of opposite side surfaces of a sintered body (1) obtained by sintering a laminate prepared by stacking a plurality of ceramic green sheets through internal electrodes to be electrically connected with prescribed ones of the internal electrodes. The method of manufacturing a multilayer ceramic electronic component comprises a step of forming the internal electrodes on single major surfaces of the ceramic green sheets by a thin film forming method, a step of electrochemically etching the opposite side surfaces (1a', 1b) of the sintered body (1) for forming gap regions between the internal electrodes and those of the external electrodes which must not be electrically connected with the internal electrodes and a step of filling up clearance portions (A) defined by dissolution/removing of the internal electrodes by the etching with an insulating material.Type: GrantFiled: February 1, 1995Date of Patent: January 28, 1997Assignee: Murata Manufacturing Co., Ltd.Inventors: Yoshiaki Kohno, Tatsuya Suzuki
-
Patent number: 5595858Abstract: A photosensitive insulation bonding layer is formed on a conducting layer. The photosensitive insulation bonding layer is subjected to exposure treatment to produce an exposed area and an unexposed area. Another conducting layer is formed on the outer surface of the photosensitive insulation bonding layer which has undergone the exposure treatment, then both conducting layers are photoetched to produce desired wiring patterns. In the next step, the unexposed area is removed from the photosensitive insulation bonding layer by development so as to form an access opening for connecting a circuit component to the wiring patterns. Then, the exposed area of the photosensitive insulation bonding layer is turned into an insulating layer by curing.Type: GrantFiled: February 10, 1995Date of Patent: January 21, 1997Assignee: Nippon Mektron, Ltd.Inventors: Fumio Akama, Yasuyuki Tanaka
-
Patent number: 5591353Abstract: A method of fabricating a printed wiring board (1) and a printed wiring board module (17) by providing a first board (1) having a pair of major opposing surfaces, a via (3) having walls extending between the surfaces and a layer of copper (5) disposed on at least one surface and extending along the walls of the via. The copper disposed in the via is protected against a subsequent etching of the copper on the surface by filling the remaining portion of the via with an epoxy (7) and then reducing the thickness of the layer of copper on the surface. The layer of copper and the epoxy are then planarized. A core layer and a second board are then provided and the first and second boards are secured to opposing sides of the core layer. A second via having walls and extending through the first and second boards and the core layer is then formed and a layer of copper is disposed on the walls of the second via and the surface.Type: GrantFiled: August 18, 1994Date of Patent: January 7, 1997Assignee: Texas Instruments IncorporatedInventors: John J. Davignon, Don J. Jermain, Leslie O. Connally
-
Patent number: 5582745Abstract: A printed circuit board and a method for making same is disclosed whereby a very high wiring density is provided in those regions of the printed circuit board in which external components (e.g., semiconductor chips) are to be attached directly. An automated registration routine permits very precise registration and positioning in said regions.Type: GrantFiled: January 10, 1995Date of Patent: December 10, 1996Assignee: International Business Machines CorporationInventors: Arnold Hans, Peter Lueck, Guenther Mohr, Theis ZurNieden
-
Patent number: 5569390Abstract: A multi-layered printed circuit board forms a base of a sensor board. Sensor chips are mounted on the multi-layered printed circuit board. The multi-layered printed circuit board is composed of a substrate, a first conductor layer, an internal insulator layer, a second conductor layer, and a surface insulator layer. An analog ground line is formed of the electrolytic copper foil of the first conductor layer by chemical etching. A signal line is formed of the electrolytic copper foil of the second conductor layer by chemical etching. Insulator layers are formed between the first conductor layer and the second conductor layer to generate a distributed capacitance between the signal line and the analog ground line for filtering out noise and improving performance.Type: GrantFiled: June 1, 1995Date of Patent: October 29, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takafumi Endo
-
Patent number: 5567328Abstract: A process to manufacture disposable medical flat flexible printed circuits 10. The process entails depositing conductive metal in the range of 1000 to 2500 Angstroms thick onto a flexible film having a thickness in the range of 0.1 to 10 mils. The first portions of the conductive metal are covered with a resist material arranged in a pattern. Metal circuit material is deposited onto second portions of the conductive metal. Overplating the metal circuit material with a corrosion resistant metal. Lastly, removing the resist material and the first portions of the metal and laminating the circuit.Type: GrantFiled: June 8, 1995Date of Patent: October 22, 1996Assignee: The Whitaker CorporationInventors: Paul F. Engle, Thomas J. Lynch, Roger T. Banks
-
Patent number: 5562837Abstract: The multi-chip module comprises a co-fired substrate, and, on at least ont face of the substrate, a set of superimposed ceramic insulating layers, fired at a temperature substantially smaller than the firing temperature of the substrate. Conducting interconnection lines are formed in thick layers deposited between said ceramic insulating layers. Electronic components are mounted at the surface of the set of ceramic layers.Type: GrantFiled: February 8, 1995Date of Patent: October 8, 1996Assignee: Matra Marconi Space FranceInventor: Jacques De Givry
-
Patent number: 5545466Abstract: The present invention provides a copper-clad laminate characterized in that an electrolytic copper foil on the glossy (shiny) surface side of which a copper electrodeposit is formed, is bonded at its glossy surface side to one side or each of both sides of a substrate, which has a fine-pitch wiring (circuit) pattern and exhibits a high etching factor. The present invention further provides a copper-clad laminate which can be suitably employed in the production of such a printed wiring board.Type: GrantFiled: July 11, 1995Date of Patent: August 13, 1996Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Muneo Saida, Yutaka Hirasawa, Katsuhiro Yoshimura
-
Patent number: 5521104Abstract: This is a system and method of fabricating hybrid integrated circuits (IC). The method may comprise: forming internal IC structures on a substrate; forming IC interlevel insulation on top of the internal IC structures; forming IC top level metal connections on top of the IC interlevel insulation; depositing a protective overcoat over the IC top level metal and the IC interlevel insulation; depositing a dry etch protective layer over the protective overcoat; and dry etching the etch protective layer and the protective overcoat to expose portions of the IC top level metal. The deposition of the protective overcoat may include depositing silicon dioxide or silicon nitride. In addition, the deposition of the dry etch protective layer may include depositing a photosensitive polymide layer. Furthermore, the dry etching may include photolithography.Type: GrantFiled: January 31, 1995Date of Patent: May 28, 1996Assignee: Texas Instruments IncorporatedInventor: William K. Walker
-
Patent number: 5512117Abstract: A charge plate fabrication process provides a charge plate assembly having minimal distortion caused by shifts in temperature and humidity. The fabrication process includes the steps of forming a charge plate coupon having a plurality of charging electrodes and electrical connections on an etchable substrate and providing a ceramic charge plate substrate. An adhesive layer is then applied between the charge plate coupon and the charge plate substrate before assembling the charge plate coupon and the charge plate substrate in a fixture. Finally, the assembly is cured in the fixture.Type: GrantFiled: April 18, 1994Date of Patent: April 30, 1996Assignee: Scitex Digital Printing, Inc.Inventor: Brian G. Morris
-
Patent number: 5505321Abstract: Multilayer rigid flex printed circuits are fabricated from a novel basestock composite comprising two copper conducting sheets, bonded to insulator layers comprised of fiberglass sheets impregnated with an adhesive such as epoxy, wherein the insulator layers are both affixed to Kapton layers wherein said Kapton layers are not coextensive with the borders of the insulator layers. The basestock composite can then be imaged and etched on the conductor layers to form conductor patterns, laminated or coated with a coverlay of dielectric material, and the basestock can be cut at a point internal to its borders and into the Kapton layers thereby separating two imaged and etched conductor layers.Type: GrantFiled: December 5, 1994Date of Patent: April 9, 1996Assignee: Teledyne Industries, Inc.Inventors: A. Roland Caron, Lee J. Millette, John G. King
-
Patent number: 5501350Abstract: A process for producing a printed wiring board, comprising the steps of forming a photosensitive resist layer on a copper layer provided on an insulating substrate, patterning the photosensitive resist layer, and etching the copper layer made bare from the photosensitive resist layer to form a copper wiring layer, wherein the surface of the copper layer is subjected to pretreatment comprising the steps of black-oxide treating the surface by the use of an alkaline oxidizing solution and subsequently finely surface-roughening the black-oxide treated surface by the use of an acidic treating solution comprised of phosphoric acid or an organic acid, followed by drying in the presence of oxygen, and thereafter the photosensitive resist layer is formed thereon. Such pretreatment enables formation of fine and uniform roughness on the copper layer surface to bring about an improvement in its adhesion to the resist layer, so that ethcing solutions can be prevented from penetrating the interface between these layers.Type: GrantFiled: January 5, 1995Date of Patent: March 26, 1996Assignee: Toppan Printing Co., Ltd.Inventors: Risaburo Yoshida, Kiyotomo Nakamura, Akitsu Ota, Mitsuaki Taguchi
-
Patent number: 5498311Abstract: A method for manufacture of printed circuit boards uses plasma etch back/desmear, carbon deposits on board surfaces to be plated and panel plating. The plated board is abrasively pre-treated, imaged, developed, etched, and stripped for final preparation before drilling. The pre-treating, imaging, developing, etch back and stripping used for inner panel boards is the same as the process steps and equipment used for the final process of the panel plated boards. The process is environmentally conscious in that it produces waste products which contain only one metal in solutions easily treated by conventional and non-conventional waste treatment technologies and eliminates or reuses by-products produced by other printed circuit board and produces waste products which contain only one metal.Type: GrantFiled: June 15, 1994Date of Patent: March 12, 1996Assignee: Quatro CorporationInventors: David L. Durgin, Robert J. Malins, Richard T. Hoke
-
Patent number: 5470644Abstract: A laminated sheet allows circuit boards to be fabricated without any special equipment. The laminated sheet can be printed using an ordinary laser printer on a personal computer. The sheet has a conductive layer, such as copper, attached to a nonconductive flexible substrate, such as Kapton. The outer surface of the copper is coated with an ink which provides a receiving surface for toner when the laminated sheet is fed through a printer. The other side of the flexible substrate is attached to a removable layer of paper which provides support for the laminated sheet during the printing process. The paper is removed after printing and the adhesive which held the paper is used to attach the flexible substrate to a rigid substrate. Alcohol is used to remove the ink and expose the copper for etching. The alcohol does not remove the toner which acts as a mask during the etching process. The toner is removed after board fabrication.Type: GrantFiled: April 21, 1994Date of Patent: November 28, 1995Inventor: David Durant